blob: 1346eafbf89a28795c73102858795fc952bfb95d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
|
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <memlayout.h>
/* This file is included inside a SECTIONS block */
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_program = .;
_text = .;
*(.text._start);
*(.text.stage_entry);
*(.text);
*(.text.*);
#if ENV_RAMSTAGE || ENV_ROMSTAGE
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_cbmem_init_hooks = .;
KEEP(*(.rodata.cbmem_init_hooks));
_ecbmem_init_hooks = .;
#endif
#if ENV_RAMSTAGE
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_pci_drivers = .;
KEEP(*(.rodata.pci_driver));
_epci_drivers = .;
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_cpu_drivers = .;
KEEP(*(.rodata.cpu_driver));
_ecpu_drivers = .;
#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
*(.rodata);
*(.rodata.*);
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_etext = .;
} : to_load
#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE)
.ctors : {
. = ALIGN(0x100)
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
LONG(0);
__CTOR_END__ = .;
}
#endif
/* Include data, bss, and heap in that order. Not defined for all stages. */
#if ARCH_STAGE_HAS_DATA_SECTION
.data : {
. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
_data = .;
*(.data);
*(.data.*);
#ifdef __PRE_RAM__
PROVIDE(_preram_cbmem_console = .);
PROVIDE(_epreram_cbmem_console = _preram_cbmem_console);
#elif ENV_RAMSTAGE
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bs_init_begin = .;
KEEP(*(.bs_init));
LONG(0);
LONG(0);
_ebs_init_begin = .;
#endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_edata = .;
}
#endif
#if ARCH_STAGE_HAS_BSS_SECTION
.bss : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_ebss = .;
}
#endif
#if ARCH_STAGE_HAS_HEAP_SECTION
.heap : {
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_heap = .;
. += CONFIG_HEAP_SIZE;
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
_eheap = .;
}
#endif
_eprogram = .;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.comment.*)
*(.note)
*(.note.*)
*(.eh_frame);
}
|
