1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
|
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <trace.h>
#include "uart8250reg.h"
/* Should support 8250, 16450, 16550, 16550A type UARTs */
/* Expected character delay at 1200bps is 9ms for a working UART
* and no flow-control. Assume UART as stuck if shift register
* or FIFO takes more than 50ms per character to appear empty.
*
* Estimated that inb() from UART takes 1 microsecond.
*/
#define SINGLE_CHAR_TIMEOUT (50 * 1000)
#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
static int uart8250_can_tx_byte(unsigned int base_port)
{
return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE;
}
static void uart8250_tx_byte(unsigned int base_port, unsigned char data)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while (i-- && !uart8250_can_tx_byte(base_port));
outb(data, base_port + UART8250_TBR);
}
static void uart8250_tx_flush(unsigned int base_port)
{
unsigned long int i = FIFO_TIMEOUT;
while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT));
}
static int uart8250_can_rx_byte(unsigned int base_port)
{
return inb(base_port + UART8250_LSR) & UART8250_LSR_DR;
}
static unsigned char uart8250_rx_byte(unsigned int base_port)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while (i && !uart8250_can_rx_byte(base_port))
i--;
if (i)
return inb(base_port + UART8250_RBR);
else
return 0x0;
}
static void uart8250_init(unsigned int base_port, unsigned int divisor)
{
DISABLE_TRACE;
/* Disable interrupts */
outb(0x0, base_port + UART8250_IER);
/* Enable FIFOs */
outb(UART8250_FCR_FIFO_EN, base_port + UART8250_FCR);
/* assert DTR and RTS so the other end is happy */
outb(UART8250_MCR_DTR | UART8250_MCR_RTS, base_port + UART8250_MCR);
/* DLAB on */
outb(UART8250_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART8250_LCR);
/* Set Baud Rate Divisor. 12 ==> 9600 Baud */
outb(divisor & 0xFF, base_port + UART8250_DLL);
outb((divisor >> 8) & 0xFF, base_port + UART8250_DLM);
/* Set to 3 for 8N1 */
outb(CONFIG_TTYS0_LCS, base_port + UART8250_LCR);
ENABLE_TRACE;
}
static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
uintptr_t uart_platform_base(int idx)
{
if (idx < ARRAY_SIZE(bases))
return bases[idx];
return 0;
}
void uart_init(int idx)
{
if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT)) {
unsigned int div;
div = uart_baudrate_divisor(get_uart_baudrate(),
uart_platform_refclk(), uart_input_clock_divider());
uart8250_init(uart_platform_base(idx), div);
}
}
void uart_tx_byte(int idx, unsigned char data)
{
uart8250_tx_byte(uart_platform_base(idx), data);
}
unsigned char uart_rx_byte(int idx)
{
return uart8250_rx_byte(uart_platform_base(idx));
}
void uart_tx_flush(int idx)
{
uart8250_tx_flush(uart_platform_base(idx));
}
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_IO_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = get_uart_baudrate();
serial.regwidth = 1;
serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
}
|
