index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
x86
/
tsc
/
Makefile.inc
blob: 44bfe85170e40d4202b1737609931545ddb29484 (
plain
)
1
2
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
