blob: 4300c3d0e4f3835e78797d2685ec370c2459a5e5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
config SERIAL_CPU_INIT
bool
default y
config UDELAY_IO
bool
default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2
default n
config UDELAY_LAPIC
bool
default n
config UDELAY_TSC
bool
default n
config UDELAY_TIMER2
bool
default n
config TSC_CALIBRATE_WITH_IO
bool
default n
config TSC_SYNC_LFENCE
bool
default n
help
The CPU driver should select this if the CPU needs
to execute an lfence instruction in order to synchronize
rdtsc. This is true for all modern AMD CPUs.
config TSC_SYNC_MFENCE
bool
default n
help
The CPU driver should select this if the CPU needs
to execute an mfence instruction in order to synchronize
rdtsc. This is true for all modern Intel CPUs.
config XIP_ROM_SIZE
hex
default ROM_SIZE if ROMCC
default 0x10000
config CPU_ADDR_BITS
int
default 36
config LOGICAL_CPUS
bool
default y
config CACHE_ROM
bool
default n
config SMM_TSEG
bool
default n
config SMM_TSEG_SIZE
hex
default 0
|