blob: 477ee51453def03e4704c5ba54b22d644dc867be (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
|
config BOOTBLOCK_CPU_INIT
string
default "cpu/samsung/exynos5250/bootblock.c"
help
CPU/SoC-specific bootblock code. This is useful if the
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
config EXYNOS_ACE_SHA
bool
default n
config SATA_AHCI
bool
default n
# Example SRAM/iRAM map for Exynos5250 platform:
#
# 0x0202_0000: vendor-provided BL1
# 0x0202_3400: bootblock, assume up to 32KB in size
# 0x0202_7000: ID section, assume 2KB in size. This will be
# within the bootblock section.
# 0x0203_0000: romstage, assume up to 128KB in size.
# 0x0207_7f00: stack pointer
# this may be used to calculate offsets
config IRAM_BOTTOM
hex
default 0x02020000
config IRAM_TOP
hex
default 0x02077fff
config BOOTBLOCK_BASE
hex
default 0x02023400
config ID_SECTION_BASE
hex
default 0x02027e00
config ROMSTAGE_BASE
hex
default 0x02030000
config ROMSTAGE_SIZE
hex
default 0x10000
# TODO Change this to some better address not overlapping bootblock when
# cbfstool supports creating header in arbitrary location.
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x2040
# TODO We may probably move this to board-specific implementation files instead
# of KConfig values.
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x02060000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x000017000
# FIXME: This is for copying SPI content into SRAM temporarily and
# will be removed when we have the SPI streaming driver implemented.
config SPI_IMAGE_HACK
hex
default 0x02060000
config IRAM_STACK
hex
default 0x02077f00
# FIXME: other magic numbers that should probably go away
config XIP_ROM_SIZE
hex
default ROMSTAGE_SIZE
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x40000000
config SPL_BUILD
bool
default n
config SYS_TEXT_BASE
hex "Executable code section"
default 0x43e00000
config RAMBASE
hex
default SYS_SDRAM_BASE
# according to stefan, this is RAMBASE + 1M.
config RAMTOP
hex
default 0x40100000
|
