blob: 4976bee57897fd04d5f9817b7d13be19f8f448fc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
|
/* Needed so the AMD K8 runs correctly. */
#include <console/console.h>
#include <mem.h>
#include <cpu/p6/msr.h>
#include <cpu/k8/mtrr.h>
#include <device/device.h>
#include <device/chip.h>
#include "chip.h"
void k8_cpufixup(struct mem_range *mem)
{
unsigned long mmio_basek, tomk;
unsigned long i;
msr_t msr;
/* Except for the PCI MMIO hold just before 4GB there are no
* significant holes in the address space, so just account
* for those two and move on.
*/
mmio_basek = tomk = 0;
for(i = 0; mem[i].sizek; i++) {
unsigned long topk;
topk = mem[i].basek + mem[i].sizek;
if (tomk < topk) {
tomk = topk;
}
if ((topk < 4*1024*1024) && (mmio_basek < topk)) {
mmio_basek = topk;
}
}
if (mmio_basek > tomk) {
mmio_basek = tomk;
}
/* Setup TOP_MEM */
msr.hi = mmio_basek >> 22;
msr.lo = mmio_basek << 10;
wrmsr(TOP_MEM, msr);
/* Setup TOP_MEM2 */
msr.hi = tomk >> 22;
msr.lo = tomk << 10;
wrmsr(TOP_MEM2, msr);
/* zero the IORR's before we enable to prevent
* undefined side effects.
*/
msr.lo = msr.hi = 0;
for(i = IORR_FIRST; i <= IORR_LAST; i++) {
wrmsr(i, msr);
}
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_TOM2En;
wrmsr(SYSCFG_MSR, msr);
}
static
void k8_enable(struct chip *chip, enum chip_pass pass)
{
struct cpu_k8_config *conf = (struct cpu_k8_config *)chip->chip_info;
switch (pass) {
case CONF_PASS_PRE_CONSOLE:
break;
default:
/* nothing yet */
break;
}
}
struct chip_control cpu_k8_control = {
enable: k8_enable,
name: "AMD K8"
};
|
