aboutsummaryrefslogtreecommitdiff
path: root/src/cpu/intel/socket_mPGA478MN/Makefile.inc
blob: 407861e1641f33e334fbda145ea8e1d4db1368a0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
subdirs-y += ../model_6fx
subdirs-y += ../model_1067x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep

# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
romstage-y += ../car/romstage.c