blob: 72e363009e73212416b96e80a8221a2742b0ac0c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
|
config CPU_ALLWINNER_A10
bool
default n
if CPU_ALLWINNER_A10
config CPU_SPECIFIC_OPTIONS
def_bool y
select HAVE_INIT_TIMER
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
select EARLY_CONSOLE
config BOOTBLOCK_CPU_INIT
string
default "cpu/allwinner/a10/bootblock.c"
help
CPU/SoC-specific bootblock code. This is useful if the
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
# The "eGON.BT0" header takes 32 bytes
config BOOTBLOCK_BASE
hex
default 0x20
config BOOTBLOCK_ROM_OFFSET
hex
default 0x00
config CBFS_HEADER_ROM_OFFSET
hex
default 0x10
# This is the maximum size bootblock that the BROM will load. If the bootblock
# gets larger, this will generate a build failure, rather than a silent
# "coreboot won't run" failure.
# Normally, we would place romstage at 0x5fe0, but we place it a little lower to
# satisfy the 64 byte alignment.
config CBFS_ROM_OFFSET
default 0x5fc0
# 16 MiB above ramstage, so there is no overlap
config ROMSTAGE_BASE
hex
default 0x41000000
# Keep the stack in SRAM block A2.
# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
# CPU. This gives us 32KiB of SRAM to boot with. The BROM bootloader will use up
# to 24KiB to load our bootblock, which leaves us the area from 24KiB to 32KiB
# to use however we see fit.
config STACK_TOP
hex
default 0x00008000
config STACK_BOTTOM
hex
default 0x00006000
config STACK_SIZE
hex
default 0x00002000
## TODO Change this to some better address not overlapping bootblock when
## cbfstool supports creating header in arbitrary location.
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x40
config SYS_SDRAM_BASE
hex
default 0x40000000
choice CONSOLE_SERIAL_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_UART0
depends on CONSOLE_SERIAL_UART
config CONSOLE_SERIAL_UART0
bool "UART0"
help
Serial console on UART0
config CONSOLE_SERIAL_UART1
bool "UART1"
help
Serial console on UART1
config CONSOLE_SERIAL_UART2
bool "UART2"
help
Serial console on UART2
config CONSOLE_SERIAL_UART3
bool "UART3"
help
Serial console on UART3
config CONSOLE_SERIAL_UART4
bool "UART4"
help
Serial console on UART4
config CONSOLE_SERIAL_UART5
bool "UART5"
help
Serial console on UART5
config CONSOLE_SERIAL_UART6
bool "UART6"
help
Serial console on UART6
config CONSOLE_SERIAL_UART7
bool "UART7"
help
Serial console on UART7
endchoice
endif # if CPU_ALLWINNER_A10
|