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if ARCH_X86
source src/cpu/amd/Kconfig
source src/cpu/intel/Kconfig
source src/cpu/via/Kconfig
source src/cpu/x86/Kconfig
config CACHE_AS_RAM
bool
default !ROMCC
config DCACHE_RAM_BASE
hex
config DCACHE_RAM_SIZE
hex
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
default 0x0
config MAX_PHYSICAL_CPUS
int
default 1
config SMP
bool
default y if MAX_CPUS != 1
default n
help
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.
config MMX
bool
help
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.
config SSE
bool
help
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.
config SSE2
bool
default n
help
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
config VAR_MTRR_HOLE
bool
default y
help
Unset this if you don't want the MTRR code to use
subtractive MTRRs
endif # ARCH_X86
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