1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
|
# Warning: This file is included whether or not the if is here.
# The if controls how the evaluation occurs.
# (See also src/Kconfig)
if ARCH_ARMV7
source src/cpu/armltd/Kconfig
source src/cpu/samsung/Kconfig
source src/cpu/ti/Kconfig
endif # ARCH_ARM
if ARCH_X86
source src/cpu/amd/Kconfig
source src/cpu/dmp/Kconfig
source src/cpu/intel/Kconfig
source src/cpu/via/Kconfig
source src/cpu/qemu-x86/Kconfig
source src/cpu/x86/Kconfig
config CACHE_AS_RAM
bool
default !ROMCC
config DCACHE_RAM_BASE
hex
config DCACHE_RAM_SIZE
hex
# FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better
# yet be dropped completely.
config MAX_PHYSICAL_CPUS
int
depends on CPU_AMD_MODEL_10XXX || CPU_AMD_MODEL_FXX || CPU_AMD_AGESA
default 1
config SMP
bool
default y if MAX_CPUS != 1
default n
help
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.
config AP_SIPI_VECTOR
hex
default 0xfffff000
help
This must equal address of ap_sipi_vector from bootblock build.
config MMX
bool
help
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.
config SSE
bool
help
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.
config SSE2
bool
default n
help
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
endif # ARCH_X86
config CPU_MICROCODE_IN_CBFS
bool
default n
choice
prompt "Include CPU microcode in CBFS" if ARCH_X86
default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS
default CPU_MICROCODE_CBFS_EXTERNAL if CPU_MICROCODE_IN_CBFS
default CPU_MICROCODE_CBFS_NONE
config CPU_MICROCODE_CBFS_GENERATE
bool "Generate from tree"
help
Select this option if you want microcode updates to be assembled when
building coreboot and included in the final image as a separate CBFS
file. Microcode will not be hard-coded into ramstage.
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
If unsure, select this option.
config CPU_MICROCODE_CBFS_EXTERNAL
bool "Include external microcode file"
help
Select this option if you want to include an external file containing
the CPU microcode. This will be included as a separate file in CBFS.
A word of caution: only select this option if you are sure the
microcode that you have is newer than the microcode shipping with
coreboot.
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
If unsure, select "Generate from tree"
config CPU_MICROCODE_CBFS_NONE
bool "Do not include microcode updates"
help
Select this option if you do not want CPU microcode included in CBFS.
Note that for some CPUs, the microcode is hard-coded into the source
tree and is not loaded from CBFS. In this case, microcode will still
be updated. There is a push to move all microcode to CBFS, but this
change is not implemented for all CPUs.
This option currently applies to:
- Intel SandyBridge/IvyBridge
- VIA Nano
Microcode may be added to the ROM image at a later time with cbfstool,
if desired.
If unsure, select "Generate from tree"
The GOOD:
Microcode updates intend to solve issues that have been discovered
after CPU production. The expected effect is that systems work as
intended with the updated microcode, but we have also seen cases where
issues were solved by not applying microcode updates.
The BAD:
Note that some operating system include these same microcode patches,
so you may need to also disable microcode updates in your operating
system for this option to have an effect.
The UGLY:
A word of CAUTION: some CPUs depend on microcode updates to function
correctly. Not updating the microcode may leave the CPU operating at
less than optimal performance, or may cause outright hangups.
There are CPUs where coreboot cannot properly initialize the CPU
without microcode updates
For example, if running with the factory microcode, some Intel
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
will hang when changing the frequency.
Make sure you have a way of flashing the ROM externally before
selecting this option.
endchoice
config CPU_MICROCODE_FILE
string "Path and filename of CPU microcode"
depends on CPU_MICROCODE_CBFS_EXTERNAL
default "cpu_microcode.bin"
help
The path and filename of the file containing the CPU microcode.
config CPU_MICROCODE_CBFS_LOC
hex "Microcode address in CBFS"
depends on CPU_MICROCODE_IN_CBFS
default 0
config CPU_MICROCODE_CBFS_LEN
hex "Microcode length in CBFS"
depends on CPU_MICROCODE_IN_CBFS
default 0xC000
help
The microcode needs a specific length to get correctly
detected and loaded by all CPUs.
|
