path: root/src/console/Kconfig

## SPDX-License-Identifier: GPL-2.0-only

menu "Console"

config NO_BOOTBLOCK_CONSOLE
	bool
	depends on SEPARATE_ROMSTAGE

config BOOTBLOCK_CONSOLE
	bool "Enable early (bootblock) console output."
	depends on !NO_BOOTBLOCK_CONSOLE
	default y
	help
	  Use console during the bootblock if supported

config POSTCAR_CONSOLE
	bool "Enable console output during postcar."
	depends on POSTCAR_STAGE
	default y
	help
	  Use console during the postcar if supported

config SQUELCH_EARLY_SMP
	bool "Squelch AP CPUs from early console."
	default y
	depends on SMP
	help
	  When selected only the BSP CPU will output to early console.

	  Console drivers have unpredictable behaviour if multiple threads
	  attempt to share the same resources without a spinlock.

	  If unsure, say Y.

config CONSOLE_SERIAL
	bool "Serial port console output"
	default y
	depends on DRIVERS_UART
	help
	  Send coreboot debug output to a serial port.

	  The type of serial port driver selected based on your configuration is
	  shown on the following menu line. Supporting multiple different types
	  of UARTs in one build is not supported.

config FIXED_UART_FOR_CONSOLE
	bool
	help
	  Select to remove the prompt from UART_FOR_CONSOLE in case a
	  specific UART has to be used (e.g. when the platform code
	  performs dangerous configurations).

if CONSOLE_SERIAL || CONSOLE_CBMEM_DUMP_TO_UART

	comment "I/O mapped, 8250-compatible"
	depends on DRIVERS_UART_8250IO

	comment "memory mapped, 8250-compatible"
	depends on DRIVERS_UART_8250MEM

	comment "device-specific UART"
	depends on HAVE_UART_SPECIAL

config OVERRIDE_UART_FOR_CONSOLE
	bool
	help
	  Set to "y" when the platform overrides the index of uart port by providing
	  a get_uart_for_console routine.

if !OVERRIDE_UART_FOR_CONSOLE

config UART_FOR_CONSOLE
	int
	prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE
	default 0
	help
	  Select an I/O port to use for serial console:
	    0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8

# FIXME: Early programming in romstage is incorrect as we should
# program different LDN to actually change the physical port.
config TTYS0_BASE
	hex
	depends on DRIVERS_UART
	default 0x3f8 if UART_FOR_CONSOLE = 0
	default 0x2f8 if UART_FOR_CONSOLE = 1
	default 0x3e8 if UART_FOR_CONSOLE = 2
	default 0x2e8 if UART_FOR_CONSOLE = 3
	help
	  Map the COM port number to the respective I/O port.

comment "Serial port base address = 0x3f8"
depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 0
comment "Serial port base address = 0x2f8"
depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 1
comment "Serial port base address = 0x3e8"
depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 2
comment "Serial port base address = 0x2e8"
depends on DRIVERS_UART_8250IO && UART_FOR_CONSOLE = 3

endif

config UART_OVERRIDE_BAUDRATE
	bool
	help
	  Set to "y" when the platform overrides the baudrate by providing
	  a get_uart_baudrate routine.

if !UART_OVERRIDE_BAUDRATE

choice
	prompt "Baud rate"
	default CONSOLE_SERIAL_115200

config CONSOLE_SERIAL_921600
	bool "921600"
	help
	  Set serial port Baud rate to 921600.
config CONSOLE_SERIAL_460800
	bool "460800"
	help
	  Set serial port Baud rate to 460800.
config CONSOLE_SERIAL_230400
	bool "230400"
	help
	  Set serial port Baud rate to 230400.
config CONSOLE_SERIAL_115200
	bool "115200"
	help
	  Set serial port Baud rate to 115200.
config CONSOLE_SERIAL_57600
	bool "57600"
	help
	  Set serial port Baud rate to 57600.
config CONSOLE_SERIAL_38400
	bool "38400"
	help
	  Set serial port Baud rate to 38400.
config CONSOLE_SERIAL_19200
	bool "19200"
	help
	  Set serial port Baud rate to 19200.
config CONSOLE_SERIAL_9600
	bool "9600"
	help
	  Set serial port Baud rate to 9600.

endchoice

#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
config TTYS0_BAUD
	int
	default 921600 if CONSOLE_SERIAL_921600
	default 460800 if CONSOLE_SERIAL_460800
	default 230400 if CONSOLE_SERIAL_230400
	default 115200 if CONSOLE_SERIAL_115200
	default 57600 if CONSOLE_SERIAL_57600
	default 38400 if CONSOLE_SERIAL_38400
	default 19200 if CONSOLE_SERIAL_19200
	default 9600 if CONSOLE_SERIAL_9600
	help
	  Map the Baud rates to an integer.

endif

# TODO: Allow user-friendly selection of settings other than 8n1.
config TTYS0_LCS
	int
	default 3
	depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM

endif # CONSOLE_SERIAL

config SPKMODEM
	bool "spkmodem (console on speaker) console output"
	default n
	depends on ARCH_X86
	help
	  Send coreboot debug output through speaker

config CONSOLE_USB
	bool "USB dongle console output"
	depends on USBDEBUG
	default y
	help
	  Send coreboot debug output to USB.

	  Configuration for USB hardware is under menu Generic Drivers.

# TODO: Deps?
# TODO: Improve description.
config CONSOLE_NE2K
	bool "Network console over NE2000 compatible Ethernet adapter"
	default n
	depends on PCI
	help
	  Send coreboot debug output to a Ethernet console, it works
	  same way as Linux netconsole, packets are received to UDP
	  port 6666 on IP/MAC specified with options below.
	  Use following netcat command: nc -u -l -p 6666

config CONSOLE_NE2K_DST_MAC
	depends on CONSOLE_NE2K
	string "Destination MAC address of remote system"
	default "00:13:d4:76:a2:ac"
	help
	  Type in either MAC address of logging system or MAC address
	  of the router.

config CONSOLE_NE2K_DST_IP
	depends on CONSOLE_NE2K
	string "Destination IP of logging system"
	default "10.0.1.27"
	help
	  This is IP address of the system running for example
	  netcat command to dump the packets.

config CONSOLE_NE2K_SRC_IP
	depends on CONSOLE_NE2K
	string "IP address of coreboot system"
	default "10.0.1.253"
	help
	  This is the IP of the coreboot system

config CONSOLE_NE2K_IO_PORT
	depends on CONSOLE_NE2K
	hex "NE2000 adapter fixed IO port address"
	default 0xe00
	help
	  This is the IO port address for the IO port
	  on the card, please select some non-conflicting region,
	  32 bytes of IO spaces will be used (and align on 32 bytes
	  boundary, qemu needs broader align)

config CONSOLE_CBMEM
	bool "Send console output to a CBMEM buffer"
	default y
	help
	  Enable this to save the console output in a CBMEM buffer. This would
	  allow to see coreboot console output from Linux space.

if CONSOLE_CBMEM

config CONSOLE_CBMEM_BUFFER_SIZE
	hex "Room allocated for console output in CBMEM"
	default 0x20000
	help
	  Space allocated for console output storage in CBMEM. The default
	  value (128K or 0x20000 bytes) is large enough to accommodate
	  even the BIOS_SPEW level.

config CONSOLE_CBMEM_DUMP_TO_UART
	depends on !CONSOLE_SERIAL
	bool "Dump CBMEM console on resets"
	default n
	help
	  Enable this to have CBMEM console buffer contents dumped on the
	  serial output in case serial console is disabled and the device
	  resets itself while trying to boot the payload.

config CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS
	bool
	help
	  Pre-bootblock stages (i.e., VBOOT_STARTS_BEFORE_BOOTBLOCK) might not
	  have the ability to log to the UART, so their console messages are
	  inaccessible until the boot processes gets into the payload or OS.
	  This feature will dump the pre-bootblock CBMEM console immediately
	  after the bootblock console is initialized.
endif

config CONSOLE_SPI_FLASH
	bool "SPI Flash console output"
	default n
	depends on BOOT_DEVICE_SPI_FLASH
	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if !COMMON_CBFS_SPI_WRAPPER
	help
	  Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area

	  This option can cause premature wear on the SPI flash and should not
	  be used as a normal means of debugging. It is only to be enabled and
	  used when porting a new motherboard which has no other console
	  available (no UART, no POST, no cbmem access(non bootable)). Since
	  a non bootable machine will require the use of an external SPI Flash
	  programmer, the developer can grab the console log at the same time.

	  The flash console will not be erased on reboot, so once it is full,
	  the flashconsole driver will stop writing to it. This is to avoid
	  wear on the flash, and to avoid erasing sectors (which may freeze
	  the SPI controller on skylake).

	  The 'CONSOLE' area can be extracted from the FMAP with :
	  cbfstool rom.bin read -r CONSOLE -f console.log

config CONSOLE_SPI_FLASH_BUFFER_SIZE
	hex "Room allocated for console output in FMAP"
	default 0x20000
	depends on CONSOLE_SPI_FLASH
	help
	  Space allocated for console output storage in FMAP. The default
	  value (128K or 0x20000 bytes) is large enough to accommodate
	  even the BIOS_SPEW level.

config CONSOLE_I2C_SMBUS
	bool "SMBus console output"
	depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
	help
	  Send coreboot debug output to the SMBus.
	  The output can be read with an I2C slave device connected
	  the SMBus. Please refer to the technotes section of the
	  coreboot documentation for more details.

if CONSOLE_I2C_SMBUS
	comment "Set logging device address and data register address"

config CONSOLE_I2C_SMBUS_SLAVE_ADDRESS
	hex "I2C slave address of the logging device"
	default 0x48 if SC16IS7XX_INIT
	help
	  I2C address of the device which logs the data.

config CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER
	bool "Write to a specific data register"
	default y if SC16IS7XX_INIT
	help
	  Select this to provide a register address that will
	  be sent before every data byte.

config CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER
	hex "Data register address of the I2C logging device"
	depends on CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER
	default 0x00 if SC16IS7XX_INIT
	help
	  This an 8-bit data register.

config SC16IS7XX_INIT
	bool "Initialize SC16IS7XX I2C to UART converter chip"
	help
	  SC16IS7XX is a slave I2C to UART converter chip. Enabling
	  this option will initialize the chip.

	  The default I2C slave address value 0x48 is the address of
	  SC16IS7XX I2C to UART converter chip when the A1 and A0 pins
	  are set to Vcc.

	  The default data register address value 0x00 is the data
	  register address of SC16IS7XX I2C to UART converter chip.

endif # CONSOLE_I2C_SMBUS

config CONSOLE_QEMU_DEBUGCON
	bool "QEMU debug console output"
	depends on CPU_QEMU_X86
	default y
	help
	  Send coreboot debug output to QEMU's isa-debugcon device:

	  qemu-system-x86_64 \
	    -chardev file,id=debugcon,path=/dir/file.log \
	    -device isa-debugcon,iobase=0x402,chardev=debugcon

config CONSOLE_QEMU_DEBUGCON_PORT
	hex "QEMU debug console port"
	depends on CONSOLE_QEMU_DEBUGCON
	default 0x402

config EM100PRO_SPI_CONSOLE
	bool "EM100Pro SPI debug console output"
	depends on HAVE_EM100PRO_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
	help
	  Enable support for the debug console on the Dediprog EM100Pro.
	  This is currently working only in ramstage due to how the spi
	  drivers are written.

config CONSOLE_SYSTEM76_EC
	bool "System76 EC console output"
	default n
	depends on EC_SYSTEM76_EC
	help
	  Send coreboot debug output to a System76 embedded controller.

config CONSOLE_AMD_SIMNOW
	bool "AMD SimNow console output"
	default n
	depends on SOC_AMD_COMMON && !POST_IO
	select CONSOLE_POST
	help
	  Send coreboot debug output to IO ports for SimNow

config CONSOLE_OVERRIDE_LOGLEVEL
	bool
	help
	  Set to "y" when the platform overrides the loglevel by providing
	  a get_console_loglevel routine.

if !CONSOLE_OVERRIDE_LOGLEVEL

choice
	prompt "Default console log level"
	default DEFAULT_CONSOLE_LOGLEVEL_8 if CHROMEOS
	default DEFAULT_CONSOLE_LOGLEVEL_7

config DEFAULT_CONSOLE_LOGLEVEL_8
	bool "8: SPEW"
	help
	  Way too many details.
config DEFAULT_CONSOLE_LOGLEVEL_7
	bool "7: DEBUG"
	help
	  Debug-level messages.
config DEFAULT_CONSOLE_LOGLEVEL_6
	bool "6: INFO"
	help
	  Informational messages.
config DEFAULT_CONSOLE_LOGLEVEL_5
	bool "5: NOTICE"
	help
	  Normal but significant conditions.
config DEFAULT_CONSOLE_LOGLEVEL_4
	bool "4: WARNING"
	help
	  Warning conditions.
config DEFAULT_CONSOLE_LOGLEVEL_3
	bool "3: ERR"
	help
	  Error conditions.
config DEFAULT_CONSOLE_LOGLEVEL_2
	bool "2: CRIT"
	help
	  Critical conditions.
config DEFAULT_CONSOLE_LOGLEVEL_1
	bool "1: ALERT"
	help
	  Action must be taken immediately.
config DEFAULT_CONSOLE_LOGLEVEL_0
	bool "0: EMERG"
	help
	  System is unusable.

endchoice

config DEFAULT_CONSOLE_LOGLEVEL
	int
	default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
	default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
	default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
	default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
	default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
	default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
	default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
	default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
	default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
	help
	  Map the log level config names to an integer.

endif

config CONSOLE_USE_LOGLEVEL_PREFIX
	bool "Use loglevel prefix to indicate line loglevel"
	default y
	help
	  When enabled, if the code contains a:
	  `printk(BIOS_DEBUG, "This is a debug message!\n")`,
	  it will show up as:
	  `[DEBUG]  This is a debug message!`

config CONSOLE_USE_ANSI_ESCAPES
	bool "Use ANSI escape sequences for console highlighting"
	default y if !CONSOLE_AMD_SIMNOW
	help
	  If enabled, certain consoles (e.g. UART) that are meant to be read on
	  a terminal will use ANSI escape sequences (like `ESC [1m`) to
	  highlight lines based on their log level. Disable this if your
	  terminal does not support ANSI escape sequences.

config NO_POST
	bool "Don't show any POST codes"
	default n

config CMOS_POST
	bool "Store post codes in CMOS for debugging"
	depends on !NO_POST && PC80_SYSTEM
	default n
	help
	  If enabled, coreboot will store post codes in CMOS and switch between
	  two offsets on each boot so the last post code in the previous boot
	  can be retrieved.  This uses 3 bytes of CMOS.

config CMOS_POST_OFFSET
	hex "Offset into CMOS to store POST codes"
	depends on CMOS_POST
	default 0x0
	help
	  If CMOS_POST is enabled then an offset into CMOS must be provided.
	  If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
	  defined in the mainboard option table.

config CONSOLE_POST
	bool "Show POST codes on the debug console"
	depends on !NO_POST
	default n
	help
	  If enabled, coreboot will additionally print POST codes (which are
	  usually displayed using a so-called "POST card" ISA/PCI/PCI-E
	  device) on the debug console.

config POST_DEVICE
	bool "Send POST codes to an external device"
	depends on !NO_POST
	default y

choice
	prompt "Device to send POST codes to"
	depends on POST_DEVICE
	default POST_DEVICE_LPC if DEFAULT_POST_ON_LPC
	default POST_DEVICE_NONE

config POST_DEVICE_NONE
	bool "None"
config POST_DEVICE_LPC
	bool "LPC"
	depends on PCI
config POST_DEVICE_PCI_PCIE
	bool "PCI/PCIe"
	depends on PCI
endchoice

config DEFAULT_POST_ON_LPC
	bool
	default n

config POST_IO
	bool "Send POST codes to an IO port"
	depends on PC80_SYSTEM && !NO_POST
	default y
	help
	  If enabled, POST codes will be written to an IO port.

config POST_IO_PORT
	depends on POST_IO
	hex "IO port for POST codes"
	default 0x80
	help
	  POST codes on x86 are typically written to the LPC bus on port
	  0x80. However, it may be desirable to change the port number
	  depending on the presence of coprocessors/microcontrollers or if the
	  platform does not support IO in the conventional x86 manner.

config NO_EARLY_BOOTBLOCK_POSTCODES
	def_bool n
	help
	  Some chipsets require that the routing for the port 80h POST
	  code be configured before any POST codes are sent out.  If this is
	  not done, the system can hang on the first POST code.  This
	  initialization can be done in the boot block, but there are a couple
	  of POST codes that go out before the chipset's C bootblock
	  initialization can happen.  This option suppresses all postcodes in
	  the early assembly code.

config HWBASE_DEBUG_CB
	bool
	default y if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
	default n

config HWBASE_DEBUG_NULL
	def_bool y
	depends on !HWBASE_DEBUG_CB

endmenu