path: root/src/arch/x86/Kconfig

## SPDX-License-Identifier: GPL-2.0-only

config ARCH_X86
	bool
	select PCI
	select RELOCATABLE_MODULES
	select HAVE_ASAN_IN_RAMSTAGE

if ARCH_X86

# stage selectors for x86

config ARCH_BOOTBLOCK_X86_32
	bool

config ARCH_VERSTAGE_X86_32
	bool

config ARCH_ROMSTAGE_X86_32
	bool

config ARCH_POSTCAR_X86_32
	bool
	default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE

config ARCH_RAMSTAGE_X86_32
	bool

config ARCH_ALL_STAGES_X86_32
	bool
	default !ARCH_ALL_STAGES_X86_64
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
	select ARCH_ROMSTAGE_X86_32
	select ARCH_RAMSTAGE_X86_32

# stage selectors for x64

config ARCH_BOOTBLOCK_X86_64
	bool
	select SSE2

config ARCH_VERSTAGE_X86_64
	bool
	select SSE2

config ARCH_ROMSTAGE_X86_64
	bool
	select SSE2

config ARCH_POSTCAR_X86_64
	bool
	default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE
	select SSE2

config ARCH_RAMSTAGE_X86_64
	bool
	select SSE2

config ARCH_ALL_STAGES_X86_64
	bool
	select ARCH_BOOTBLOCK_X86_64
	select ARCH_VERSTAGE_X86_64 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
	select ARCH_ROMSTAGE_X86_64
	select ARCH_RAMSTAGE_X86_64

config HAVE_X86_64_SUPPORT
	bool
	help
	  Enable support to build and run coreboot in 64-bit mode.
	  When enabling this option for a new platform, it is recommended to
	  provide a config file for Jenkins to build-test the 64-bit option.

config USE_X86_64_SUPPORT
	bool "Run coreboot in long (64-bit) mode"
	depends on HAVE_X86_64_SUPPORT
	select ARCH_ALL_STAGES_X86_64
	help
	  When set, most of coreboot runs in long (64-bit) mode instead of the
	  usual protected flat (32-bit) mode. 64-bit CPUs and OSes can be used
	  irrespective of whether coreboot runs in 32-bit or 64-bit mode.

config PAGE_TABLES_IN_CBFS
	bool
	default n

config ARCH_X86_64_PGTBL_LOC
	hex "x86_64 page table location in CBFS"
	depends on ARCH_BOOTBLOCK_X86_64 && PAGE_TABLES_IN_CBFS
	default 0xfffe9000
	help
	  The position where to place pagetables. Needs to be known at
	  compile time. Must not overlap other files in CBFS.

config RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT
	bool
	help
	  On some systems, the upper physical address bits are reserved and
	  used as a tag which is typically related to a memory encryption
	  feature. When selecting this option, the SoC code needs to implement
	  get_reserved_phys_addr_bits so that the common code knows how many of
	  the most significant physical address bits are reserved and can't be
	  used as address bits.

# This is an SMP option. It relates to starting up APs.
# It is usually set in mainboard/*/Kconfig.
# TODO: Improve description.
config AP_IN_SIPI_WAIT
	bool
	default n
	depends on ARCH_X86 && SMP

config RESET_VECTOR_IN_RAM
	bool
	depends on ARCH_X86
	select NO_XIP_EARLY_STAGES
	help
	  Select this option if the x86 processor's reset vector is in
	  preinitialized DRAM instead of the traditional 0xfffffff0 location.

# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
# can boot AP CPUs to enable their shared caches.
config SIPI_VECTOR_IN_ROM
	bool
	default n
	depends on ARCH_X86

# Traditionally BIOS region on SPI flash boot media was memory mapped right below
# 4G and it was the last region in the IFD. This way translation between CPU
# address space to flash address was trivial. However some IFDs on newer SoCs
# have BIOS region sandwiched between descriptor and other regions. Turning on
# X86_CUSTOM_BOOTMEDIA disables X86_TOP4G_BOOTMEDIA_MAP which allows the
# soc code to provide custom mmap_boot.c.
config X86_CUSTOM_BOOTMEDIA
	bool

config X86_TOP4G_BOOTMEDIA_MAP
	bool
	depends on !X86_CUSTOM_BOOTMEDIA
	default y

config PRERAM_CBMEM_CONSOLE_SIZE
	hex
	default 0xc00
	help
	  Increase this value if preram cbmem console is getting truncated

config CBFS_MCACHE_SIZE
	hex
	depends on !NO_CBFS_MCACHE
	default 0x4000
	help
	  Increase this value if you see CBFS mcache overflow warnings. Do NOT
	  change this value for vboot RW updates!

config PRERAM_CBFS_CACHE_SIZE
	hex
	default 0x4000
	help
	  Define the size of the Pre-RAM stages CBFS cache. A size of
	  zero disables the CBFS cache feature in pre-memory stages.

config POSTRAM_CBFS_CACHE_IN_BSS
	bool
	default y if !SOC_AMD_COMMON_BLOCK_NONCAR
	help
	  Allocate the post-memory CBFS cache scratchpad in the .bss
	  section. CBFS cache will rely on a simple static C buffer
	  while traditionally CBFS cache memory region is reserved in
	  the device memory layout.

config RAMSTAGE_CBFS_CACHE_SIZE
	hex
	default 0x4000
	depends on POSTRAM_CBFS_CACHE_IN_BSS
	help
	  Define the size of the ramstage CBFS cache. A size of zero
	  disables the CBFS cache feature in ramstage.

config PC80_SYSTEM
	bool
	default y if ARCH_X86

config BOOTBLOCK_DEBUG_SPINLOOP
	bool
	default n
	help
	  Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
	  for a JTAG debugger to break into the execution sequence.

config HAVE_CMOS_DEFAULT
	def_bool n
	depends on HAVE_OPTION_TABLE

config CMOS_DEFAULT_FILE
	string
	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
	depends on HAVE_CMOS_DEFAULT

config HPET_MIN_TICKS
	hex

config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0x40000 if !FIXED_BOOTBLOCK_SIZE
	help
	   This is only the default maximum of bootblock size for linking
	   purposes. Platforms may provide different limit and need to
	   specify this when FIXED_BOOTBLOCK_SIZE is selected.

config FIXED_BOOTBLOCK_SIZE
	bool

# Default address romstage is to be linked at
config ROMSTAGE_ADDR
	hex
	default 0x2000000

# Default address verstage is to be linked at
config VERSTAGE_ADDR
	hex
	default 0x2000000

# Use the post CAR infrastructure for tearing down cache-as-ram
# from a program loaded in RAM and subsequently loading ramstage.
config POSTCAR_STAGE
	def_bool y
	depends on ARCH_X86
	depends on !RESET_VECTOR_IN_RAM

config VERSTAGE_DEBUG_SPINLOOP
	bool
	default n
	help
	  Add a spin (JMP .) in assembly_entry.S during early verstage to wait
	  for a JTAG debugger to break into the execution sequence.

config ROMSTAGE_DEBUG_SPINLOOP
	bool
	default n
	help
	  Add a spin (JMP .) in assembly_entry.S during early romstage to wait
	  for a JTAG debugger to break into the execution sequence.

choice
	prompt "Bootblock behaviour"
	default BOOTBLOCK_SIMPLE
	depends on !VBOOT

config BOOTBLOCK_SIMPLE
	bool "Always load fallback"

config BOOTBLOCK_NORMAL
	bool "Switch to normal if CMOS says so"
	select CONFIGURABLE_CBFS_PREFIX
	select SEPARATE_ROMSTAGE

endchoice

config SKIP_MAX_REBOOT_CNT_CLEAR
	bool "Do not clear reboot count after successful boot"
	depends on BOOTBLOCK_NORMAL
	help
	  Do not clear the reboot count immediately after successful boot.
	  Set to allow the payload to control normal/fallback image recovery.
	  Note that it is the responsibility of the payload to reset the
	  normal boot bit to 1 after each successful boot.

config ACPI_BERT
	bool
	depends on HAVE_ACPI_TABLES
	help
	  Build an ACPI Boot Error Record Table.

config COLLECT_TIMESTAMPS_NO_TSC
	bool
	default n
	depends on COLLECT_TIMESTAMPS
	help
	  Use a non-TSC platform-dependent source for timestamps.

config COLLECT_TIMESTAMPS_TSC
	bool
	default y if !COLLECT_TIMESTAMPS_NO_TSC
	default n
	depends on COLLECT_TIMESTAMPS
	help
	  Use the TSC as the timestamp source.

config PAGING_IN_CACHE_AS_RAM
	bool
	default n
	depends on ARCH_X86
	help
	  Chipsets scan select this option to preallocate area in cache-as-ram
	  for storing paging data structures. PAE paging is currently the
	  only thing being supported.

config NUM_CAR_PAGE_TABLE_PAGES
	int
	default 5
	depends on PAGING_IN_CACHE_AS_RAM
	help
	  The number of 4KiB pages that should be pre-allocated for page tables.

# Provide the interrupt handlers to every stage. Not all
# stages may take advantage.
config IDT_IN_EVERY_STAGE
	bool
	default n
	depends on ARCH_X86

config HAVE_CF9_RESET
	bool

config HAVE_CF9_RESET_PREPARE
	bool
	depends on HAVE_CF9_RESET

config HAVE_CONFIGURABLE_APMC_SMI_PORT
	bool
	help
	  SoCs that have a configurable APMC SMI command port, should select
	  this option and implement pm_acpi_smi_cmd_port() that returns the IO
	  port.

config PIRQ_ROUTE
	bool
	default n

config MAX_PIRQ_LINKS
	int
	default 4
	depends on PIRQ_ROUTE
	help
	  This variable specifies the number of PIRQ interrupt links which are
	  routable. On most chipsets, this is 4, INTA through INTD. Some
	  chipsets offer more than four links, commonly up to INTH. They may
	  also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
	  table specifies links greater than 4, pirq_route_irqs will not
	  function properly, unless this variable is correctly set.

config MEMLAYOUT_LD_FILE
	string
	default "src/arch/x86/memlayout.ld"

config DEBUG_HW_BREAKPOINTS
	bool
	default y
	help
	  Enable support for hardware data and instruction breakpoints through
	  the x86 debug registers

config DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES
	bool
	default y
	depends on DEBUG_HW_BREAKPOINTS && IDT_IN_EVERY_STAGE

config DEBUG_NULL_DEREF_BREAKPOINTS
	bool
	default y
	depends on DEBUG_HW_BREAKPOINTS
	help
	  Enable support for catching null dereferences and instruction execution

config DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES
	bool
	default y
	depends on DEBUG_NULL_DEREF_BREAKPOINTS && DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES

config DEBUG_NULL_DEREF_HALT
	bool
	default n
	depends on DEBUG_NULL_DEREF_BREAKPOINTS
	help
	  When enabled null dereferences and instruction fetches will halt execution.
	  Otherwise an error will be printed.

# Some EC need an "EC firmware pointer" (a data structure hinting the address
# of its firmware blobs) being put at a fixed position. Its space
# (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a
# stage. Different EC may have different format and/or value for it. The actual
# address of EC firmware pointer should be provided in the Kconfig of the EC
# requiring it, and its value could be filled by linking a read-only global
# data object to the section above.

config ECFW_PTR_ADDR
	hex
	help
	   Address of reserved space for EC firmware pointer, which should not
	   overlap other data such as reset vector or FIT pointer if present.

config ECFW_PTR_SIZE
	int
	help
	   Size of reserved space for EC firmware pointer

config DUMP_SMBIOS_TYPE17
	bool "Dump part of SMBIOS type17 dimm information"
	depends on GENERATE_SMBIOS_TABLES

config SOC_PHYSICAL_ADDRESS_WIDTH
	int
	default 0
	help
	  On some System-on-Chip the physical address size available
	  at the SoC level may be different than at the CPU
	  level. This configuration can be use to set the physical
	  address width (in bits) of the SoC.

	  If not set, both CPU and SoC physical address width are
	  assume to be the same.

config X86_BOOTBLOCK_EXTRA_PROGRAM_SZ
	int
	default 1024 if CHROMEOS
	default 0
	help
	  Add extra space to prevent overlap between .text and .init sections.
	  This is necessary for older linkers (pre-binutils 2.4x) like those used
	  on ChromeOS platforms.

	  The default value is 1024 bytes (1 KiB) for ChromeOS and 0 for other platforms.

config DEFAULT_EBDA_LOWMEM
	hex
	default 0x100000
	help
	  The default value of EBDA low memory is (1024 << 10).

config DEFAULT_EBDA_SEGMENT
	hex
	default 0xF600
	help
	  The default value of EBDA segment is 0xF600.

config DEFAULT_EBDA_SIZE
	hex
	default 0x400
	help
	  The default value of EBDA size is 0x400.

config SHADOW_ROM_TABLE_TO_EBDA
	bool
	default n
	help
	  For platforms without writable PAM-F segment support. Put ROM table
	  pointers (e.g. ACPI/SMBIOS low pointers) into EBDA.
endif