path: root/src/arch/x86/Kconfig

##
## This file is part of the coreboot project.
##
## Copyright (C) 2009-2010 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

config ARCH_X86
	bool
	default n
	select PCI
	select RELOCATABLE_MODULES

# stage selectors for x86

config ARCH_BOOTBLOCK_X86_32
	bool
	default n
	select ARCH_X86
	select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK

config ARCH_VERSTAGE_X86_32
	bool
	default n

config ARCH_ROMSTAGE_X86_32
	bool
	default n

config ARCH_RAMSTAGE_X86_32
	bool
	default n

# stage selectors for x64

config ARCH_BOOTBLOCK_X86_64
	bool
	default n
	select ARCH_X86
	select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK

config ARCH_VERSTAGE_X86_64
	bool
	default n

config ARCH_ROMSTAGE_X86_64
	bool
	default n

config ARCH_RAMSTAGE_X86_64
	bool
	default n

config USE_MARCH_586
	def_bool n
	help
	  Allow a platform or processor to select to be compiled using
	  the '-march=i586' option instead of the typical '-march=i686'

# This is an SMP option. It relates to starting up APs.
# It is usually set in mainboard/*/Kconfig.
# TODO: Improve description.
config AP_IN_SIPI_WAIT
	bool
	default n
	depends on ARCH_X86 && SMP

# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
# can boot AP CPUs to enable their shared caches.
config SIPI_VECTOR_IN_ROM
	bool
	default n
	depends on ARCH_X86

# Set the rambase for systems that still need it, only 5 chipsets as of
# Sep 2018. This value was 0x100000, chosen to match the entry point
# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense
# for as long as we need it; with luck, that won't be much longer.
# In the long term, both RAMBASE and RAMTOP should be removed.
# This value leaves more than 1 MiB which is required for fam10
# and broadwell_de.
config RAMBASE
	hex
	default 0xe00000

config RAMTOP
	hex
	default 0x1000000
	depends on ARCH_X86

# Traditionally BIOS region on SPI flash boot media was memory mapped right below
# 4G and it was the last region in the IFD. This way translation between CPU
# address space to flash address was trivial. However some IFDs on newer SoCs
# have BIOS region sandwiched between descriptor and other regions. Turning off
# this option enables soc code to provide custom mmap_boot.c which can be used to
# implement complex translation.
config X86_TOP4G_BOOTMEDIA_MAP
	bool
	default y

# This is something you almost certainly don't want to mess with.
# How many SIPIs do we send when starting up APs and cores?
# The answer in 2000 or so was '2'. Nowadays, on many systems,
# it is 1. Set a safe default here, and you can override it
# on reasonable platforms.
config NUM_IPI_STARTS
	int
	default 2

config CBMEM_TOP_BACKUP
	def_bool n
	help
	  Platform implements non-volatile storage to cache cbmem_top()
	  over stage transitions and optionally also over S3 suspend.

config LATE_CBMEM_INIT
	def_bool n
	select CBMEM_TOP_BACKUP
	help
	  Enable this in chipset's Kconfig if northbridge does not implement
	  early cbmem_top() call for romstage. CBMEM tables will be allocated
	  late in ramstage, after PCI devices resources are known.

	  WARNING: Late CBMEM initialization is deprecated. Platforms that
	  don't support early CBMEM initialization will be removed after
	  the release of coreboot 4.7.

config PRERAM_CBMEM_CONSOLE_SIZE
	hex
	default 0xc00
	help
	  Increase this value if preram cbmem console is getting truncated

config EARLY_EBDA_INIT
	bool
	default n
	help
	  Initialize BIOS EBDA area early in romstage to allow bootloader to
	  use this region for storing data which can be available across
	  various stages. If user is selecting this option then its users
	  responsibility to perform EBDA initialization call during romstage.

config PC80_SYSTEM
	bool
	default y if ARCH_X86

config BOOTBLOCK_DEBUG_SPINLOOP
	bool
	default n
	help
	  Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
	  for a JTAG debugger to break into the execution sequence.

config BOOTBLOCK_MAINBOARD_INIT
	string

config BOOTBLOCK_NORTHBRIDGE_INIT
	string

config BOOTBLOCK_RESETS
	string

config BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP
	bool
	default n
	help
	  Select this value to provide a routine to save the BIST and timestamp
	  values.  The default code places the BIST value in MM0 and the
	  timestamp value in MM2:MM1.  Another file is necessary when the CPU
	  does not support the MMx register set.

config HAVE_CMOS_DEFAULT
	def_bool n
	depends on HAVE_OPTION_TABLE

config CMOS_DEFAULT_FILE
	string
	default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
	depends on HAVE_CMOS_DEFAULT

config BOOTBLOCK_SOUTHBRIDGE_INIT
	string

config IOAPIC_INTERRUPTS_ON_FSB
	bool
	default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS

config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
	bool
	default n

config HPET_ADDRESS_OVERRIDE
	def_bool n

config HPET_ADDRESS
	hex
	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

config ID_SECTION_OFFSET
	hex
	default 0x80

# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK.
config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0x10000

# Default address romstage is to be linked at
config ROMSTAGE_ADDR
	hex
	default 0x2000000

# Default address verstage is to be linked at
config VERSTAGE_ADDR
	hex
	default 0x2000000

# Use the post CAR infrastructure for tearing down cache-as-ram
# from a program loaded in RAM and subsequently loading ramstage.
config POSTCAR_STAGE
	def_bool n
	select NO_CAR_GLOBAL_MIGRATION

config VERSTAGE_DEBUG_SPINLOOP
	bool
	default n
	help
	  Add a spin (JMP .) in assembly_entry.S during early verstage to wait
	  for a JTAG debugger to break into the execution sequence.

config ROMSTAGE_DEBUG_SPINLOOP
	bool
	default n
	help
	  Add a spin (JMP .) in assembly_entry.S during early romstage to wait
	  for a JTAG debugger to break into the execution sequence.

choice
	prompt "Bootblock behaviour"
	default BOOTBLOCK_SIMPLE

config BOOTBLOCK_SIMPLE
	bool "Always load fallback"

config BOOTBLOCK_NORMAL
	bool "Switch to normal if CMOS says so"

endchoice

config BOOTBLOCK_SOURCE
	string
	default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
	default "bootblock_normal.c" if BOOTBLOCK_NORMAL

config SKIP_MAX_REBOOT_CNT_CLEAR
	bool "Do not clear reboot count after successful boot"
	depends on BOOTBLOCK_NORMAL
	help
	  Do not clear the reboot count immediately after successful boot.
	  Set to allow the payload to control normal/fallback image recovery.
	  Note that it is the responsibility of the payload to reset the
	  normal boot bit to 1 after each successsful boot.

config ACPI_CPU_STRING
	string
	default "\\_PR.CP%02d"
	depends on HAVE_ACPI_TABLES
	help
	  Sets the ACPI name string in the processor scope as written by
	  the acpigen function. Default is \_PR.CPxx. Note that you need
	  the \ escape character in the string.

config COLLECT_TIMESTAMPS_NO_TSC
	bool
	default n
	depends on COLLECT_TIMESTAMPS
	help
	  Use a non-TSC platform-dependent source for timestamps.

config COLLECT_TIMESTAMPS_TSC
	bool
	default y if !COLLECT_TIMESTAMPS_NO_TSC
	default n
	depends on COLLECT_TIMESTAMPS
	help
	  Use the TSC as the timestamp source.

config PAGING_IN_CACHE_AS_RAM
	bool
	default n
	depends on ARCH_X86
	help
	  Chipsets scan select this option to preallocate area in cache-as-ram
	  for storing paging data structures. PAE paging is currently the
	  only thing being supported.

config NUM_CAR_PAGE_TABLE_PAGES
	int
	default 5
	depends on PAGING_IN_CACHE_AS_RAM
	help
	  The number of 4KiB pages that should be pre-allocated for page tables.

# Provide the interrupt handlers to every stage. Not all
# stages may take advantage.
config IDT_IN_EVERY_STAGE
	bool
	default n
	depends on ARCH_X86