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- 'git describe --match [0-9].[0-9]*' was giving me an error, so use
the basic 'git describe' command instead.
- If a .coreboot-version file exists, use that to determine the version.
This fixes the problem for coreboot releases.
- Don't run git for the versions unless it's being built from a valid
git repository. Use 0.0 as the default version for timeless or unknown.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5fae2f012cc9b9914d8803af8dd58a885358cb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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`python` as a command isn't universally available anymore after the
python2/python3 drama.
Change-Id: I9d68873d86dc3f044238d921c10fc434a83a76f5
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ifb728ebb5d0e98b0c8a59f3bd8803ce193a05e5f
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I532db49799eadf3214a70297c5fc84aa006bc3f7
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Building of LLVM tests and examples is enabled by default, but they are
not necessary. Thus disable them.
Change-Id: I58b09e276967e97856da65e5876b27f0bae3f0cc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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To improve the readability and visibility of the configure options, move
each of them to a separate line.
Change-Id: Ifc39e4d0849d220d85e1d9ce92fc008fec610694
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: If1b724f9c9b4d2a8ce166946794c1c0882ad1653
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The patches for kconfig need to be in a format compatible with the quilt
tool, and usually also contain a header with some additional info like
the git commit. This header is in the same format as patches produced by
`git format-patch`, but the diff style git uses is incompatible with
quilt and there does not seem to be a straightforward way to format the
diff section to work.
Add some documentation for a method I found to go from a git commit to a
quilt compatible patch with git headers.
Change-Id: I7a8bbe41e0864be1d28116742b6b8b3fc440cc31
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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CPU nodes are now declared in a common chipset.cb.
TESTED: generates a proper devicetree for x220 based on logs.
Change-Id: Ic1f2d3d611aa3979b846706b6f743f79a3c4e54d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69501
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1: binaries stay the same for qemu-i440fx.
Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: Iebccaf984c2c8b449c8f152484a4df1e75e74fd8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69715
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Right now cbmem uses a fix path to reach coreboot src path (../../).
This makes it impossible to compile cbmem out of the coreboot tree (e.g.
copy just the cbmem directory elsewhere and compile).
This patch adapts the technique from cbfstool and adds a variable called
'TOP' which points to coreboot root directory and which can be
overridden at build time by providing it to make as an argument. This
will enable a stand-alone build of cbmem.
Change-Id: I2732f75310e10716e5aa74e094e0bf628ad22f0b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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The download links from acpica.org [1] are not stable, and for some
reason they named the release tarballs with .tar_0.gz. Thus, use the
tarballs from their GitHub repository generated out of the release
tags [2].
Tested locally and also IASL patch applies.
[1] https://www.acpica.org/downloads
[2] https://github.com/acpica/acpica/tags
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I7b10dd1db4299aaef96bc29023bed874b660aba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70021
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GCC 12 incorrectly warns about an array out of bounds issue:
```
$ make V=1 # emulation/qemu-i440fx
[…]
CC ramstage/arch/x86/ebda.o
x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/arch/x86/ebda.o -D__RAMSTAGE__ -c -o build/ramstage/arch/x86/ebda.o src/arch/x86/ebda.c
In file included from src/arch/x86/ebda.c:6:
In function 'write_ble8',
inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2,
inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2,
inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2,
inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds]
27 | *(uint8_t *)dest = val;
| ~~~~~~~~~~~~~~~~~^~~~~
[…]
```
[In GCC 12 the new parameter `min-pagesize` is added and defaults 4 kB.][1]
It treats INTEGER_CST addresses smaller than that as assumed results of
pointer arithmetics from NULL while addresses equal or larger than that
as expected user constant addresses. For GCC 13 we can represent results
from pointer arithmetics on NULL using &MEM[(void*)0 + offset] instead
of (void*)offset INTEGER_CSTs.
[1]: https://web.archive.org/web/20220711061810/https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578
TEST=No compile error with gcc (Debian 12.2.0-3) 12.2.0
Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We don't currently use the artifacts from the Clang or CrOS GCC
builds, so don't bother saving them.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I69fe803e4b4213a199d0b76089da443aa769aa92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Changes: https://acpica.org/node/201
Change-Id: I386a6757a318336bc616091afe0c4ed88cd89583
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I7679c6751fb02ab670ade923b365c6410a6dc118
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This reduce the difference with linux v6.0-rc3.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ica20264d744ea8f77b56c63d29e1fafc2e68a869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This patch extends the available device paths with a new device 'mdio'.
MDIO is the 'Management Data Input/Output' called interface which is
used to access an Ethernet PHY behind a MAC to change settings. The real
payload data path is not handled by this interface.
To address the PHY correctly on the MDIO bus, there is a 5 bit address
needed, which often can be configured via pins on the mainboard.
Therefore, the new introduced device has an 'addr' field to define its
address. If one wants to use a MDIO device in devicetree, the syntax is
straight forward (example):
device mdio 0x2 on end
As the MDIO interface is driven by the MAC, most likely this MDIO device
will be hooked in as a child device of the (PCI attached) MAC device.
With the new introduced ops_mdio a new interface is added to provide an
API for read and write access over MDIO.
Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69382
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No real functional changes, just cleaning up shellcheck issues, putting
braces around variables, add comments and the like.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6e79afc8d725e86ddbf7f4eb4685bed190c20738
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67319
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"../cmake" introduced on Change-Id: I3144a83
Remove "../cmake" when the build is done.
Change-Id: I289bfaca1fd8d3f004455babd99849ca8aa2d6db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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coreboot only supports a small subset of the targets that LLVM supports.
It's not needed to enable all possible targets. Thus limit the targets
to the following ones:
* X86
* RISC-V
* AArch32
* AArch64
* PowerPC
Change-Id: I9938bf176b5fe2b0a631c3b1ae858f988898a196
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69841
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur.heymans@9elements.com>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7cf35132df0bc23f7b6f78014ddd72d58ea2ab8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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With the addition of the clang tests, the jenkins builds are taking a
really long time to run the tests. This change allows the
"what-jenkins-does" build to be split into separate builds on jenkins.
Additionally, some jenkins builds like coverity don't need (or want)
to build clang or even the linters.
Update help with the variables.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0f8ac68c1bc8f8ff9be62d80db850355e742ee74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This tests building a single target with scanbuild so to make sure that
option hasn't been broken. Since it's a different type of build, it
hasn't previously been tested with what-jenkins-does.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8a74dac203f4d38c0cb30a0b64724e6f9095b9dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This gets rid of the duplicated directory and xml filename and uses the
--name argument to abuild instead, which also updates the test name in
the junit xml file.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibe538da42280696190b0a7a0c63fd86a63e40214
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Previously, the testclass variable was only updated with the chromeos
or Kconfig option values, and the output directory and xml file names
were updated independently.
With the --name option, all of these can be set simultaneously. This
also prevents jenkins from seeing clang and gcc tests as the same
because the testclass variable wasn't updated.
If --name is not set, all behavior is as it was previously.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8f52779b92d213386a3eb371d1f30ee32ed48b85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Instead of having duplicate lines in the what-jenkins-does target and
the test-tools target, make test-tools from what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id62d6bb1e729892ec123ea970ca8a31e03a812d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It's hard to tell what is what with the short option names, so use the
long options here.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1371e098bba1077dedfaffa56287a28656197b40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Instead of having duplicate lines in the what-jenkins-does target and
the test-abuild target, make test-abuild from what-jenkins-does.
The test-abuild target had not been updated to use the ABUILD_OPTIONS
variable, so update it with the commands from what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Instead of having duplicate lines in the what-jenkins-does target and
the test-lint target, make test-lint with the --junit argument from
what-jenkins-does.
Now there's only one place to update when changing the call.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Instead of having the what-jenkins-does target clean up before building,
have it call the test_cleanup target.
Clean the tegra targets.
Remove distclean from test_cleanup target - I don't think that's
expected, and people might be upset by having their .config deleted.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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If no boards are tested by abuild, an error is currently shown because
no boards failed, but no boards passed either. Account for this
possibility.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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The change being reverted [1] caused all the Kconfig dependency files
to be generated at the top level of coreboot's build directory.
This reverts that behavior and puts the dependencies back where we're
used to them being.
[1] https://web.archive.org/web/20220316120807/https://github.com/torvalds/linux/commit/1b9e740a81f91ae338b29ed70455719804957b80
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic4b48831705c3206e7c2e09f01d072d1cde9c9c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69535
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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revert commit 1b9e740a8 (kconfig: fix failing to generate auto.conf) [1]
The above change caused all of the enabled kconfig options to be written
into the top level build directory. We don't want that, so go back to
the old behavior for the coreboot tree.
[1] https://web.archive.org/web/20220316120807/https://github.com/torvalds/linux/commit/1b9e740a81f91ae338b29ed70455719804957b80
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2904f69a5d85337ad0a6b48590ccd4b4a6e38b70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Testing for the presence of intel-sec-tools doesn't need to happen
inside the what-jenkins-does target.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6faa5bd5292ac5cceba9a64fe81939c0e25b9f3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The directory names were wrong.
Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69568
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also comment out the SMSC FDC37M602 which has a conflicting
ID and has never had the LDN/register layout anyway.
Tested on a Dell Latitude E6400
Change-Id: I5b1900e6ef599c422a1d6eca7a2ac4691d56d874
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69481
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There doesn't seem to be a datasheet available for the NCT6685D, but
there is one for the NCT6686D. The 85D seems to return the same ID as
the 86D, and the registers do seem to be returning valid data other than
LDN 0xf which returns all 1s. The LDN and register layout appears to be
identical to the NCT6687D-W.
Tested on a Lenovo ThinkCentre M900 with a NCT6685D.
Change-Id: I4de0e7b86422a14ab9ccb15b7571597611d755d5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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-malign-abi does not exist on clang (v15.0.0) and the -ccc-gcc-name
variable is not needed anymore.
TESTED: This also boots on qemu q35
Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Some platforms correctly build and boot with clang. Add this to our CI.
Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Some hardware uses more instances.
Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are used on newer platforms.
Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Document: 614109, 601458
Tested on: Protectli vault_ehl (VP2420)
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Change-Id: I54948741082ca1072642046f64539a4c15ddb578
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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This finds all the boards using a specified Kconfig option and runs both
CrOS and non-CrOS abuilds on them to make sure they're working.
Nobody wants to run the full what-jenkins-does build on their host
machine. Hopefully this can help get some tests run locally before
pushing to coreboot.org.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Handle the possible memory leak scenario.
Foundby=klocwork
BUG=NONE
TEST=Boot to OS on Nivviks
Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69220
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The functions create_bpdt_hdr and create_cse_layout
in bpdt_1_6.c are defined to return pointers but
not integers as was previouly implemented.
Reported-by: Coverity(CID:1469323)
Reported-by: Coverity(CID:1469353)
Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Fix readouts from the hardware monitor on Fintek F71808A Super I/O.
The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61.
Referred to util/superiotool/winbond.c and the Linux kernel driver f71882fg.
Tested on a HP 500-319na (Memphis-S / IPM87-MP).
Signed-off-by: Ravi Mistry <rvstry@protonmail.com>
Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is the script used to generate the list of platforms that were
removed from the master branch at each release. Generate a list for the
old branch, another for the new, and compare the two.
Representative output:
```eval_rst
+-------------------------+-------------------+------------+----------+
| Vendor/Board | Processor | Date added | Brd type |
+=========================+===================+============+==========+
| 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop |
| acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop |
| acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop |
| amd/bilby | AMD_PICASSO | 2021-02-17 | eval |
| amd/birman | AMD_MORGANA | 2022-10-10 | eval |
| system76/whl-u | INTEL_WHISKEYLAKE | 2021-04-14 | laptop |
| ti/beaglebone | TI_AM335X | 2013-05-26 | sbc |
| up/squared | INTEL_APOLLOLAKE | 2019-05-22 | mini |
+-------------------------+-------------------+------------+----------+
```
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4f7265d95df31f3a74aa2aa164f6a094c1139750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Some of the cbmem area names have gotten longer, and were making the
output of cbmem -l look bad, so expand the name area to 20 characters.
Instead of printing a blank area if the name isn't recognized, call it
unknown.
Change the method of printing the title to match the way the actual text
of the table is printed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Co-authored-by is commonly used for changes that have more than one
author. Add it to the list to make Jenkins happy.
Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
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The current tool is a shell script that mixes data collection and HTML
generation and is generally a pain to work with. It takes 15 minutes to
run.
The new tool is written in go, collects all data first, then generates
the output HTML from the data and a single template, and finishes in
10 seconds.
The goal in this version is to produce output as similar as possible to
the output of the shell script. Some difference will remain because the
shell script returns some trash data whose reproduction would require
more effort than is worth.
Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Correct the capitalization of ELOG_CROS_DIAG_TYPE_STORAGE_HEALTH from
"Storage Health Info" to "Storage health info", which is already widely
used in depthcharge diagnostics tools.
BUG=b:254405481
TEST=none
Change-Id: Ia6c1df9e8d2ee6f8ae11b962e76b52f3c6663c42
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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free the memory allocated in lz4_compress
function before returning from it.
Reported-by: Coverity (CID:1469433)
Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: I8698090d519964348e51fc3b6f2023d06d81fcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Instead of using unquoted strings for the command line parameters,
use arrays which naturally split into separate elements inside the
quotes.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1c96d5072b98523af4e407cfff8f4d1d28ec3297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Only minor changes in kconfig this time that shouldn't
affect us.
TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same
Change-Id: I77cc8517128a973c345c41da2c483b78eeaee89f
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Only minor changes in kconfig this time that shouldn't
affect us.
TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same
Change-Id: Icc83c929dd1ea2d98e1a789560ce26886ded1f12
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Only minor changes in kconfig this time that shouldn't affect us.
TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same
Change-Id: I46f43182ce9ec1b6a5923cb77dcd6e335e44c87a
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Another upstream refactoring, another local patch gone!
TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same
Change-Id: I0f99dcbd8ecc7256551f0a6e2c83c060cb1999b6
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Linux 5.16 saw a significant rewrite in the boolean handling which
reduces our change set. On the other hand, it's all new code.
Comparing the config.build and config.h files generated by
`util/abuild/abuild -C`, only a few lines of comment in the header
changed.
Change-Id: I52984e15a48236ddf228707aec85e90f71aa4382
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Automatically fall back to using regular grep if working outside a git
repository and the option to use regular grep is not specified
Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: I0cdecf01a0e74c30947c4fe7e7c7d9457a5165a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Since the RW firmware may contain newer/additional blobs than the
RO COREBOOT region, try using it first, then fall back to
COREBOOT and eventually BOOT_STUB if necessary.
TEST=extract blobs from dedede and brya firmware images
Change-Id: Ia01b37f8c410685de8a17ea4105ca671931a47c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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The line length limit in coreboot's coding style guidelines applies to
the final file, while checkpatch currently checks the patch line length.
Since patches´ lines start with a `+` (only added content is checked),
the line length being checked is one character longer than the actual
content.
Increase max_line_length by 1 to take this into account.
Change-Id: I8da45bb0d5fbe7d0e12c8b181cf01e5685186bf6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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Metadata Hash is usually present inside the first segment of BIOS. On
board where vboot starts in bootblock, it is present in bootblock. On
boards where vboot starts before bootblock, it is present in file
containing verstage. Update cbfstool to check for metadata hash in file
containing verstage besides bootblock.
Add a new CBFS file type for the concerned file and exclude it from CBFS
verification.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 and PSP verstages.
Change-Id: Ib4dfba6a9cdbda0ef367b812f671c90e5f90caf8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66942
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add build rules to build amdfwread tool. Also mark this as a dependency
either while building tools or amdfw.rom.
BUG=None
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories
and list the entries present in them. Accommodate both recovery A/B
layout and normal layout. This is required to identify the location and
size of each entries in the finally built amdfw.rom. This in turn can be
used to perform any platform specific verification on the relevant
components.
BUG=None
TEST=Build and list the contents of AMDFW binary.
/usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin
Table: FW Offset Size
PSPL1: Dir 0x00d97000
+-->PSPL1: 0x48 0x00d98000 0x00001000
+-->PSPL2: Dir 0x00c30000
+-->PSPL2: 0x00 0x00c31000 0x00000440
+-->PSPL2: 0x01 0x00c31500 0x00007580
+-->PSPL2: 0x02 0x00c38b00 0x00019470
+-->PSPL2: 0x08 0x00c52000 0x0001f560
+-->PSPL2: 0x09 0x00c71600 0x00000440
+-->PSPL2: 0x0b 0x430000041(Soft-fuse)
+-->PSPL2: 0x0c 0x00c71b00 0x00023100
+-->PSPL2: 0x12 0x00c94c00 0x00015890
+-->PSPL2: 0x13 0x00caa500 0x000021c0
+-->PSPL2: 0x20 0x00cac700 0x00000640
+-->PSPL2: 0x21 0x00cace00 0x00000030
+-->PSPL2: 0x22 0x00cad000 0x00001000
+-->PSPL2: 0x24 0x00cae000 0x00003b60
+-->PSPL2: 0x28 0x00cb1c00 0x00022890
+-->PSPL2: 0x2d 0x00cd4500 0x00003100
+-->PSPL2: 0x30 0x00cd7600 0x0006b550
+-->PSPL2: 0x3a 0x00d42c00 0x000006d0
+-->PSPL2: 0x3c 0x00d43300 0x000018c0
+-->PSPL2: 0x44 0x00d44c00 0x00006610
+-->PSPL2: 0x45 0x00d4b300 0x00001c70
+-->PSPL2: 0x50 0x00d4d000 0x00001a00
+-->PSPL2: 0x51 0x00d4ea00 0x00001020
+-->PSPL2: 0x52 0x00d4fb00 0x00010180
+-->PSPL2: 0x55 0x00d5fd00 0x00000600
+-->PSPL2: 0x5a 0x00d60300 0x00000570
+-->PSPL2: 0x5c 0x00d60900 0x00000b20
+-->PSPL2: 0x71 0x00d61500 0x00024710
+-->PSPL2: 0x73 0x00d85d00 0x00010640
+-->PSPL2: 0x8d 0x00d96400 0x00000030
+-->PSPL2: 0x49 0x00d99000 0x00001000
+-->BIOSL2: Dir 0x00d99000
+-->BIOSL2: 0x60 0x00d9a000 0x00009924
+-->BIOSL2: 0x68 0x00da4000 0x00009924
+-->BIOSL2: 0x61 0x2001000(DRAM-Address)
+-->BIOSL2: 0x62 0x00dada00 0x00010000
+-->BIOSL2: 0x63 0x00000000 0x0001e000
+-->BIOSL2: 0x64 0x00db4200 0x00006310
+-->BIOSL2: 0x65 0x00dba600 0x000004e0
+-->BIOSL2: 0x64 0x00dbab00 0x00006180
+-->BIOSL2: 0x65 0x00dc0d00 0x00000250
+-->BIOSL2: 0x6b 0x201f000(DRAM-Address)
+-->PSPL1: 0x4a 0x00d98000 0x00001000
Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to
handle it.
Also add a generic read_header function to read different header types.
BUG=None
TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to
dump the Softfuse entry.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Optional arguments that involve printing information from the firmware
image is mapped to bit fields with bit 31 set. But instead of just
setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask.
BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
* AMD_ADDR_PHYSICAL refers to physical address in the memory map
* AMD_ADDR_REL_BIOS is relative to the start of the BIOS image
* AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS
tables
Update the relative_offset implementation accordingly. Though
AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify
the relative_offset implementation so that it can be used for both PSP
and BIOS firmware tables. Hence update the relative_offset function
signature as well.
BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.
Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the
patch adding register definitions for NCT6687D Super I/O chip.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Fix "bad revision" error when we run "update_submodules" with no option.
This adds "origin/trunk" branch name for "util/goswid".
Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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If the coreboot code is not in a git repository, the linters switch
from using `git ls-files` to find. This requires some changes to
prevent the linters from looking at the wrong files which are
automatically excluded by git.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a
subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it.
The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains:
* An uint8_t of subtype code
* Any number of "ChromeOS diagnostics logs" events
Each "ChromeOS diagnostics log" represents the result of one ChromeOS
diagnostics test run. It is stored within an uint8_t raw[3]:
* [23:19] = ELOG_CROS_DIAG_TYPE_*
* [18:16] = ELOG_CROS_DIAG_RESULT_*
* [15:0] = Running time in seconds
Also add support for parsing this event. The parser will first calculate
the number of runs it contains, and try to parse the result one by one.
BUG=b:226551117
TEST=Build and boot google/tomato to OS,
localhost ~ # elogtool list
0 | 2022-09-26 04:25:32 | Log area cleared | 186
1 | 2022-09-26 04:25:50 | System boot | 0
2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery
| recovery_reason=0x2/0 (Recovery button pressed)
| fw_tried=A | fw_try_count=0 | fw_prev_tried=A
| fw_prev_result=Unknown
3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery
4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success
5 | 2022-09-26 04:26:06 | System boot | 0
6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic
| fw_tried=A | fw_try_count=0 | fw_prev_tried=A
| fw_prev_result=Unknown
7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs
| type=Memory check (quick), result=Aborted, time=0m0s
| type=Memory check (full), result=Aborted, time=0m0s
| type=Storage self-test (extended), result=Aborted, time=0m1s
Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Wrap the console logging macros with do { ... } while (0) so they act
more like functions.
Add missing semicolons to calls of these macros.
TEST=compile only
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I721a4a93636201fa2394ec62cbe4e743cd3ad9d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Based on public NCT6686D hardware datasheet revision 0.5 which should
be similar to NCT6687D.
TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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This makes it easier to match the code to the datasheet (55758, NDA
only).
This also removes the duplicate lines:
"{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },
{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },"
TESTED: google/vilboz still boots.
Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
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Add missing Mendocino soc to usage print.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows amdfwtool to recognize the names for the upcoming morgana
and glinda SoCs. It does not yet do anything for those SoCs, but this
allows the morgana SoC to build.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix shell variable "LINTDIR" so that helper_functions.sh can be found.
TEST=`./util/lint/lint lint-stable --junit` no longer prints "cannot
open /helper_functions.sh: No such file"
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Add support for traditional (non-ULT) Broadwell.
Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add the PCI device IDs for 9 series PCHs.
Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Update the README with new instructions for Debian 11 and MX Linux.
Also add the build dependencies.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P
Document number: 626817, 630094, 655258
Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage
can pass it to PSP. The PSP will use these hashes to verify the
integrity of those signed firmwares.
BUG=b:203597980
TEST=Build Skyrim BIOS image.
Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for separating signed firmwares into another CBFS. If
sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware
is signed against AMD chain of trust and will be verified by PSP. If
those firmware binaries are put outside FW_MAIN_[AB], vboot can skip
redundant verification, improving overall verification time.
BUG=b:206909680
TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS.
Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Checkpatch script recommends to use __packed instead of
__attribute__((packed)). Currently the build rule for amdfwtool does not
include the required header file with __packed definition. Update the
compiler flag to include the required header file.
BUG=None
TEST=Build amdfwtool.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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edkII requires ImageMagick's `convert` to compile. The
`graphicsmagick-imagemagick-compat` package provides `convert` without
the full ImageMagick library.
Change-Id: I8fc01526842eb408b0015c0652043c20f826a015
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Each of the tools that used git had similar functionality. This combines
all of that into a single script that gets sourced by each. This makes
maintenance much easier.
By doing this and updating each of the scripts to do the correct thing
if the script isn't being run in a git repository, it makes them work
much better for the releases, which are just released as a tarball,
without any attached git repository.
Change-Id: I61ba1cc4f7205e0d4baf993588bbc774120405cb
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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- Update spelling.txt with Lintian changes
- Remove words that are going to mess up code
- Add comments to the header about what words should be removed, along
with where the files
- Add Makefile to sort the list
Note that this undoes some of the sorting that Patrick introduced in
commit CB:38632 - ID: 805b291830
I just cannot reproduce his sort order, even using the script he put
into the commit message.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic131d5b08409f43eb700dcc8f125af00cff53d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64893
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The parsing of the PMU binary subprogram and instance numbers only
worked correctly for the cases where the ID in the name in the fw.cfg
file was between 0 and 9, but returned wrong results if it was between a
and f. Switch to using strtol with a base of 16 instead of subtracting
the char '0' from the char in the filename in
find_register_fw_filename_bios_dir to fix this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Mendocino supports LP5x but currently doesn't support SPDs that use the
LP5x memory type, 0x15. This commit updates set 1 SPDs, which are
currently only used for mendocino, to use 0x13 for their memory type.
BUG=b:245509394
TEST=Generated SPDs, verified that only set 1 have changed to 0x13
Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Tested on a Dell Venue 8 Pro tablet
Change-Id: Ic8f162ea82b910082af4b4e05fa1408fd24f2c88
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add parameters to support adding the location and size of
the PSP NVRAM area to the PSP directory table.
Verified this change on PCO based Bilby platform.
Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The help text and label for legacy_8254_timer is inverted, so update
this so that it is correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I866a15886d1cfd2b77094742787dee7a36a54e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65348
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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