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2023-06-04crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5Elyes Haouas
Change-Id: I1f227bf55bac51e6226ca5d13156e54220e33629 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75635 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4Elyes Haouas
Change-Id: Id6dca6be8f7a82eadcbc18b4736219faf51b843c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02util/amdfwtool: Add ability to split hash tableKarthikeyan Ramasubramanian
Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-02util/docker: Split coreboot-sdk test into its own docker imageMartin Roth
This allows the coreboot-sdk docker image to build properly even if the testing fails, and keeps the added overhead out of the coreboot-sdk image. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6488799256f57ad64e14c93e7317b7ad2a71781c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenixFred Reitberger
BUG=285390041 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74971 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02amdfwtool: Add --output-manifest optionGrzegorz Bernacki
Passing this option tells amdfwtool to create a text file, containing the versions of the blobs below: - PSP bootloader (type 0x01), - SMU firmware (type 0x08), - AGESA bootloader 0 (type 0x30), - PSP bootloader AB (type 0x73). Created file can be embedded into CBFS which allows to read the version of blobs at runtime. This way version of blobs used to build the coreboot image can be verified at runtime and also from the binary file. Format of manifest file is following: $ cat build/amdfw_manifest type: 0x01 ver:00.35.00.13 type: 0x08 ver:00.5a.23.a6 type: 0x30 ver:2a.14.b0.10 type: 0x73 ver:00.35.00.13 BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-29util/crossgcc: Update nasm from 2.15.05 to 2.16.01Elyes Haouas
Timeless build for QEMU (i440fx/piix4) does not modify the binary. New patch is add to fix the build in a separate directory from the source. Change-Id: Ib69437be8ee69ad62fb1dfbbafabc2c4c885b7b2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-27util/ifdtool: Add support for Intel 800 series chipsetSubrata Banik
This commit adds support for Intel 800 series chipset. The new chipset can be uniquely identified by its SPI speed, eSPI speed, and chipset name. This commit message is clear and concise, and it accurately describes the changes that were made to the code. It also includes the following information: - Specify the correct chipset name. "PCH Revision: 800 series Meteor Lake" - Show the valid eSPI/EC frequency. "Read eSPI/EC Bus Frequency: 20MHz" Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I70619d9e3ed2bcad86f84a0527e3a0ad13acd706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-27libpayload;arch,cpu/x86: drop USE_MARCH_586 Kconfig optionFelix Held
Only the Intel Quark SoC selected this option and that SoC was dropped in commit 531023285ea4 ("soc/intel/quark: Drop support"), so drop this Kconfig option too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4f1c7530cd8ac7a1945b1493a2d53a7904daa06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75473 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26commit-msg: Match the Signed-off-by line with name and mail addressZheng Bao
The previous regular expression only matches the line starting with "Signed-off-by:". If the name and mail address are missing, it can not find out. The following words should be "name <mail@xxx.com>". Change-Id: I42cc399e79b65928a6aef87c51e5476c7158d166 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-26util/crossgcc: Update binutils-2.40 import set_entry_point patchElyes Haouas
Import set_entry_point patch from https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3539414584be0094b0a4fe56dfd64ea79d802edc to fix issue in binutils 2.40 with LTO when applied to PE/PE+ binaries (i.e. UEFI). Change-Id: I3844b53c8761239932ce91c2ff19ed0402321d1a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-25crossgcc: Upgrade IASL from 20221020 to 20230331Elyes Haouas
Changes: https://acpica.org/node/202 Change-Id: I43fc180bd51ff7cb06a67619c8350d28b086bc90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-24util/crossgcc: Add empty directory for tarballsFelix Singer
A directory for tarballs is needed in any case but it's created at build time. However, in reproducible build environments the sources are downloaded before the buildgcc scripts runs and the directory needs to be created. Thus, to simplify that, add an empty tarballs directory. Change-Id: Id3b4bf918c93f10c145f580684e916a4f8bae3b1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-24amdfwtool: Set the minimum size of entry PSPL2 A/BZheng Bao
This is a PSP FW requirement. This is only for recovery A/B without ISH header. That means only Cezanne. Change-Id: I62616d5a866f66fc71e6c0b31a23c62dc11cf3c6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-23crossgcc: Upgrade LLVM version 15.0.7 to 16.0.4Elyes Haouas
Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22util: Use common ARRAY_SIZE defineKonrad Adamczyk
Remove duplicated definitions of ARRAY_SIZE macro across util/ dir. Instead of duplicates, use the one from commonlib/bsd/helpers.h file. BUG=b:231765496 TEST=make -C util/cbfstool; make -C util/cbmem; make -C util/intelmetool; make -C util/superiotool Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74474 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Grzegorz Bernacki Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22util/kconfig: Fix default value getter for integer optionsKrystian Hebel
CB:37152 was supposed to be uprev to Linux's kconfig, but it got this one case wrong, Linux never returned "0" [1]. As a result, when an option has default value different than 0, and it was changed to 0, savedefconfig skips saving it. However, during the build from such defconfig the option is assigned default value. TEST=Set SEABIOS_DEBUG_LEVEL to 0 and see that savedefconfig writes it to defconfig file. [1] https://github.com/torvalds/linux/commit/7cf3d73b4360e91b14326632ab1aeda4cb26308d Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I821e45dcec99904fab85f136298cbd0315237ff6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72650 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-05-17util/docker: Add Dockerfile for Arch LinuxFelix Singer
Add a minimal Dockerfile that pre-installs necessary software which is needed to work with coreboot. Change-Id: I85f3dc7b28b77989f0f1400d1282ed4b17082f65 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-05-16util/chromeos: Add EC header update utilityCaveh Jalali
This adds a new utility for copying ec_commands.h and ec_cmd_api.h from the chrome EC repo with the appropriate copyright header adjustment. It is invoked as: util/chromeos/update_ec_headers.sh [EC-repo] where EC-repo is the top of the EC repo from which header files are to be obtained. The corresponding files in src/ec/google/chromeec are updated but not committed. Also, a commit message is suggested with the original git versions for reference. BUG=b:258126464 Change-Id: Ib43c75d807dd925b2c4bff425c07a36b4b4582c4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-11util/scripts/show_platforms.sh: Fix reStructuredText table outputNicholas Chin
reStructuredText grid tables require row separators otherwise the rows get concatenated into a single cell for each column. Representative output of previous behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Representative output of corrected behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | +-------------------------+-------------------+------------+----------+ | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | +-------------------------+-------------------+------------+----------+ | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Change-Id: I83be58dd2c34c65ae2c65cf2bd98330936fb6f6a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-11util/inteltool: Add ADL-S device identificationsMaximilian Brune
R680E, Q670E, H610E are the ADL-S IoT variants see also: commit a0bc90e4abfe ("Add missing ADL-S device identification") Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1dbfa0464bc22f9bcf91d9e9fa9eb79132600175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-08util/amdfwtool: Consolidate entry line regex patternKarthikeyan Ramasubramanian
There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-04-28amdfwtool: Increase MAX_PSP_ENTRIESFred Reitberger
The MAX_PSP_ENTRIES constant reserves space for the psp directory table entries. This table is aligned to 4K and the next binary is also aligned to 4K. The number of psp directory entries on Birman exceeds the previous limit, so increase it to the maximum that will fit in a 4K block. TEST=timeless builds for Birman unchanged Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I297edc9cccffde0ad1ce7461b375542f9f2f7c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-27util/ifdtool/ifdtool.c: Fix default FMAP generationMaximilian Brune
According to SPI programming guide, a region limit of 0 as well as region base of 7FFFh indicates an unused/reserved region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I790d7f5631ecef3043b2c17c41430dc4fd854f72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-27util/cbmem: Add REG_NEWLINE flag to fix matching patternKonrad Adamczyk
Match-any-character operators (eg. ".*") shall not match newline characters for BANNER_REGEX, since given regular expression matches newline explicitly. Add REG_NEWLINE flag to `regcomp` call. BUG=b:278718871 TEST=Boot firmware on skyrim, reboot. Run `cbmem -2`. `cbmem -2` returns second-to-last boot log. Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-04-25util/docker/jenkins-node: Drop Zephyr SDKFelix Singer
The version of the Zephyr SDK that is used is quite old and Zephyr hasn't been really used. Thus, drop it and also its dependencies from u-boot. Change-Id: Ie498d687e1566133adf650166117d8f68fcfdaf6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-04-25util/docker/jenkins-node: Allow pip to install packages system-wideFelix Singer
Call pip3 with `--break-system-packages` allowing it to install packages system-wide. This fixes building the Docker container. Change-Id: Id093f2c69fec43556c434fbca7b36095a7e6bd97 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-25util/docker/jenkins-node: Merge package installations into first stepFelix Singer
It's not necessary to have multiple steps for installing packages and requirements. Just merge the two install steps to one. Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74245 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-22lib/version: Move board identification stringsKyösti Mälkki
These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21util/inteltool: Add support for Jasper LakeKarol Zmyslowski
Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor) Based on Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 revision 001 (DOC# 634545) Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-04-17crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3Elyes Haouas
Change-Id: Iab8d67632f97c596baa9b430228d4aae6fa48126 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-16util/cbfstool: Qualify struct e820entry as packedBill XIE
In order to accord with grub (see include/grub/i386/linux.h) and comments for offsets of members of struct linux_params, struct e820entry should be defined as __packed, otherwise, sizeof(struct linux_params) will become 4224 (0x1080). Fortunately, the affected area is usually not occupied. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I09955c90e4eec337adca383e628a8821075381d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-04-13mb/google/rex: add variant gpio tables for variant creationYH Lin
BUG=b:276818954 TEST=new_variant_fulltest.sh rex0 BRANCH=None Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-13cbfstool: Add comment to define stability rules for cbfstool print -kJulius Werner
In CB:41119, I sort of made up a mechanism on the fly for how to make the machine-parseable cbfstool print output extensible without breaking backwards compatibility for older scripts. But I only explained it in the commit message which is not very visible. This patch adds a comment to the function that generates that output so that people who want to change it can understand the intent. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0d18d59e7fe407eb34710d6a583cfae667723eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-11util/sconfig: Remove unused ioapic and irq keywordsArthur Heymans
Ioapic information in the devicetree was only used to set up mptables but this generic driver was removed (ca5a793 drivers/generic/ioapic: Drop poor implementation). This removes the unused remainders from mainboard devicetrees. Remove ioapic setup from sconfig. Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-08ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .backlight_enable = 0x01, ^~~~ /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .dock_event_enable = 0x01, ^~~~ Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-07Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS"Arthur Heymans
This reverts commit 89b4f69746ac215e4a7c5f204d1ea807b4ea08b5. SI_BIOS is mostly used to indicate the BIOS region in Intel IFD. Not all platforms are Intel platforms with an IFD, so revert this change. Also tooling often depends on names not changing so renaming things should not be done lightly. The default region should also be in sync with non-x86 and made systematic across the tree. Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74290 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-04-06tree: Replace `egrep` with `grep -E`Felix Singer
For compatibility reasons, egrep is just a wrapper around grep today. Thus, replace it with `grep -E`. Change-Id: Ief08a22e4cd7211a3fee278492c95d37f9e058fa Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-06util/lint/stable-017: Update full config pattern matchingArthur Heymans
CONFIG_ARCH gives false positives for CONFIG_ARCH_X86_64_PGTBL_LOC so use a different string: 'CONFIG_MAINBOARD_DIR'. Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74220 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-05util/spd_tools: Add support for Phoenix platformKarthikeyan Ramasubramanian
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform so that SPD can be generated for the memory parts used in that platform. SPD requirements for Phoenix and Mendocino platforms are identical. BUG=b:273383819 TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms share the platform manifest for LP5 memory parts. Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-03util/crossgcc/buildgcc: Allow bootstrapping CMake with multiple threadsFelix Singer
The main build process already runs multi-threaded, when requested. Apply the same setting to the bootstrap / configure step. Change-Id: I89d6728a0985946b702f83770bedf767afb12690 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74156 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2Elyes Haouas
Change-Id: I62078257fd84a64c699a7f930bc306e38d2f4058 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73791 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-01util/crossgcc: Update binutils from 2.37 to 2.40Felix Singer
Change-Id: I34a20a999f7ea624c1add4750fcd116166953dd8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-04-01util/docker/coreboot-sdk: Remove Python 2 packageFelix Singer
Debian removed Python 2 from their Sid repository and so it needs to be removed from the Dockerfile as well. Built and tested the Dockerfile with Python 2 removed. Still works. Change-Id: If4e298dc275c1dfaf57cd4c3f8e5f89410318ec0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-03-28util/cbfstool: Add usage information about verbose outputMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ica512d21d1cef8ccffbc093016c7a3bfcf901b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73488 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-28cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOSMaximilian Brune
Currently ifdtool --validate will not correctly validate the FMAP against the IFD regions, since it will compare the IFD bios region with an FMAP region called SI_BIOS. It's probably a good idea to define default name for the BIOS FMAP region like we have for 'COREBOOT' or 'FMAP' FMAP region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I55eddfb5641b3011d4525893604ccf87fa05a1e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28util/ifdtool: Add option to create FMAP templateMaximilian Brune
On systems that do not provide their own *.fmd (Flashmap) file, we fall back to a default flashmap file. That file however does not contain the blobs (ME, GBE ...), that are usually placed below the BIOS Flashmap. It can therefore easily happen that the placement of the blobs collides with the placement of the BIOS region (e.g. if CBFS_SIZE is big enough). The fmaptool can't catch that, since it does not know of the blobs placement. This patch basically maps the regions described in the IFD (Intel Firmware Descriptor) to the default Flashmap. Test: Build and see that build/fmap.fmd contains all blobs now (on intel systems that are supported by the ifdtool) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I82cb252fff456773af69943e188480a4998736fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24amdfwtool: Clean up table buffers before combo loopZheng Bao
Keep clean copies of PSP and BIOS table. Refresh the working tables before they are filled with file names and other information at each iteration. Change-Id: Ie8339a4d66c38e02180cbf99e13914bfff66dc0f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Add missing help information for --combo-config1Zheng Bao
Change-Id: I6b69965991daadaf8b4148b06d0715b087021c9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Call wrapper funtion to write fileZheng Bao
Don't call system call directly. Change-Id: I6da31723bc2bfc1197fc31962053671c84ccc397 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Move some funtions to other categorized source filesZheng Bao
To reduce the size of amdfwtool.c which is already too big. Change-Id: Ib80eeb42f59a3dda04402b2feaadc1d178ed989e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-21util/amdfwtool: remove unused union from embedded_firmware structFelix Held
Since commit 2f6b7d557d97 ("amdfwtool: Move the filling of table headers into functions"), the combo_psp_directory union element in the embedded_firmware is unused and the new_psp_directory element is used in all places, so replace the union of new_psp_directory and combo_psp_directory with just the new_psp_directory struct element. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35d339b3084ec8f93210095c233f5e68296d0013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-17util/liveiso: Move NixOS configs to subdirectoryFelix Singer
Move the NixOS configuration into a subdirectory so that configurations for other distros can be added as well. Change-Id: I0462c1a6541878c973be4302c5c5e9e9bfaed2a6 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-03-16amdfwtool: Print which combo entry is being processedZheng Bao
Change-Id: I9e83a3ac56d5c42d8d6839cc4d961adf0b656fb5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73725 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16amdfwtool: Remove meaningless double parenthesesZheng Bao
Change-Id: I4a9192c55d63531621dd7bc49f1ead7f58dff893 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73648 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-16amdfwtool: Check combo_index before checking the combo_configZheng Bao
Otherwise Checking combo_config[++combo_index] causes Out-of-Bounds access. Change-Id: I50d466ee98edfb18c01fc7ba43e929640b33c7c1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73647 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16amdfwtool: Add asserting before accessing array combo_configZheng Bao
Change-Id: Ia98fdbee4c4005562662313ebe2478d0aeb879bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73724 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-15util/amdfwtool: Update config parser to accept full pathsMartin Roth
This allows individual components to be placed in a location other than what is specified by the FIRMWARE_LOCATION line. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a83e52d081a5909d54eacc575dd2b40b09e4038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-15util/amdfwtool: Support not passing recovery/backup APCBKarthikeyan Ramasubramanian
If Recovery/Backup APCB is not passed, then AMD_BIOS_APCB_BK entry is not populated. But PSP expects that bios directory entry to be populated. Also on mainboards where both APCB and recovery APCB are same (eg. Skyrim), 2 copies of the same APCB are added to amdfw*.rom. Update amdfwtool to support not passing recovery/backup APCB. If the recovery APCB is not passed, then populate AMD_BIOS_APCB_BK entry and make it point to the same offset as AMD_BIOS_APCB entry. BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Ensure that the device can enter recovery mode. Perform multiple suspend/resume cycles. Change-Id: I031ba817573cd35160f5e219b1b373ddce69aa6b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73661 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15amdfwtool: Remove the initial alignment on newer SoCsKarthikeyan Ramasubramanian
On newer SoCs the initial alignment is not required. So skip initial alignment. This saves 64 KiB flash space on each firmware slots. This also saves ~5 ms while loading amdfw.rom BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Change-Id: I27cbfde2d7d58b62a4c0039c60babc3fb3bd95fa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73654 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-12util/inteltool: Fix build on musl-libc systemsFabian Groffen
use __linux__ instead of __GLIBC__ guard for Linux-specific includes Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ifbf4552591c0df7811c5b37a9207c0901b6fd68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73666 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-12util/superiotool: Fix build on musl-libc systemsFabian Groffen
- use __linux__ instead of __GLIBC__ guard for Linux-specific includes - use POSIX ioperm instead of deprecated iopl Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I99613007aa9feddcb1041f31085cdeb195ff7a68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-10amdfwtool: Remove the option --list which nobody usesZheng Bao
It was used for printing the dependencies which is now taken by macro DEP_FILES in soc/amd/common/Makefile.inc. TEST=binary identical test on google/guybrush amd/chausie Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10amdfwtool: Move PSP FWs padding into a loop for comboZheng Bao
Move main body of PSP padding into a loop which can add a new combo entry. In the loop, get the FW files from each fw.cfg, create new pack of PSP, and fill the combo header. Currently Feature COMBO is still not fully functional. But the non-combo case will not be affected for sure. The real changes are 1. Add a do-while loop. 2. Remove a "TODO" comment. All other changes are re-indenting and re-filling. Change-Id: I351192a4bc5ed9ec0bfa3f2073c9633b8b44246d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58554 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10amdfwtool: Add combo index and combo config tableZheng Bao
For now, combo index is 0, and only the first entry in config table is used. The index will grow when there are more combo entries. Add a command parameter to give fw.cfg for combo index 1. Process the combo config in the future loop. Change-Id: I00609d91defc08e17f937ac8339575f84b1bd37c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10amdfwtool: Add a wrapper function to open and process config fileZheng Bao
And move the additional processing to this new function. Change-Id: Id101d63e4d30a6e57ac1aa79665a4ba22b2956f1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73509 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09util/amdfwtool: Add option to indicate uncompressed BIOS binaryKarthikeyan Ramasubramanian
amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS directory entry) is always compressed. On boards using vboot, sometimes PSP BIOS binary is uncompressed - specifically when CBFS verification is enabled and verified boot starts in bootblock. Add an option to indicate PSP BIOS binary is uncompressed. BUG=b:261792282 TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled. Boot to OS. Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-09util/ifdtool/ifdtool.c: Clean upMaximilian Brune
- Remove functions that are only called in one place. - Add warning if user doesn't supply a platform, since that can lead to dumps/layouts that do not include all IFD regions without the user even reliazing it. - Inform the User if IFD or Flashmap is not found. - Inform the User if there is not a single match between FMAP and IFD region - Avoid printing usage if not specifically asked by the user. It tends to obfuscate the original error message. - Keep indentation consistent throughout the file. - Remove typedefs (coreboot coding style) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7bbce63ecb2e920530394766f58b5ea6f72852e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-09amdfwtool: move FW_MPIO to PSP Dir Level 2 where it belongsNikolai Vyssotski
Type 0x5d (MPIO Firmware) was mistakenly placed to PSP Level 1 directory. It should be in Level 2 PSP directory instead. Change-Id: Ic5ea00859f1055e0c91600c5f941c5d3acca36e2 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09amdfwtool: Support multiple inst entriesFred Reitberger
Use the inst field when adding entries to the psp tables. Otherwise, entries that differ by the inst field will appear as duplicates with an inst of 0. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4a84a0730976f4c65902b5c24ed13e21e95b03bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-08amdfwtool: combo: Add combo feature for BIOS tableZheng Bao
It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08amdfwtool: Separate two cases of combo and non-combo clearlyZheng Bao
If combo is used, fill the EFS header with address of COMBO header. If not, fill with address of PSP header. The old code fills with PSP headers all the time. Change-Id: I0057165aea553d9dc8e4e719e2804557229a0002 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66855 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08amdfwtool: combo: Create the combo header earlierZheng Bao
There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08amdfwtool: Move the filling of table headers into functionsZheng Bao
It is easier to understand what these statements are about. Change-Id: Ib02c68c9f2ea84020b12682c41fb1a6f8f93d725 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66852 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-07util/lint: Ignore braces around single line statementsMartin Roth
In a recent coreboot leadership meeting, the decision was made to allow (but not require) braces around single line statements if the author wishes to put them in. This patch removes the checks for single line statement blocks, while still checking for other issues in braces. Just because they're allowed now, please do not reformat the entire codebase to add them. coreboot has a policy of not making widespread changes to the entire codebase unless something actually violates the style guidelines. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73515 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04lint/lint-stable-003-whitespace: Fix excludelistMaximilian Brune
Remove the last slash '/' from directories in excludelist, so that they will be correctly filtered by grep. Fixes: grep: util/goswid: Is a directory grep: util/nvidia/cbootimage: Is a directory Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I90cc2cff9a98bbd0af344156332b970bfd6430b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-03-02amdfwtool: Remove the limit of spliting EFS and bodyZheng Bao
To support 32M flash, the non-vboot also need to split amdfw. Just as the deleted comment says, we need this feature now. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-02amdfwtool: Change .rom.efs to .rom and .rom to .rom.bodyZheng Bao
To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-02util/cbfstool/eventlog: Use LocalTime or UTC timestampsWojciech Macek
Add a new flag "--utc" to allow the user to choose if elogtool should print timestamps in Local Time or in UTC. It is useful for generating automated crash reports including all system logs when users are located in various regions (timezones). Add information about timezone to timestamps printed on the console. Signed-off-by: Wojciech Macek <wmacek@google.com> Change-Id: I30ba0e17c67ab4078e3a7137ece69009a63d68fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-03-01amdfwtool:combo: Move the filling of field "lookup" into functionZheng Bao
This filling does not need to be done separately. Change-Id: I53051349923dce40f4fc3f747ab41a93a3798823 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-01amdfwtool: Remove the hints of flag --combo-capableZheng Bao
A few references to "--combo-capable" were left after commit 4bfb36ed68154d8ee6fc77a6b2bf79938cae9e8a Change-Id: I6f425db2a8b86d7ad928baee6bc7b07e5190ba37 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73281 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-01amdfwtool: Clean up the logic sequence of pointer growingZheng Bao
When the EFS data is being packed, the pointer should be at EFS header. After that, it should be at body location. TEST=binary identical test on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: Ia81e2bdf9feb02971723f39e7f223b5055807cd8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-28amdfwtool: Check the validation of EFS & body relative addressZheng Bao
We need to considering the case the EFS header is given as a relative address and the other, body location, is given as an absolute one. So we convert both of them to relative and check the validation. For relative address case, the location should be between 0 and data size. Change-Id: I7898bfbca02f5eb1c0fb7c456dc1935bddf685b1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-28amdfwtool: Fill the address in EFS header as "relative to BIOS"Zheng Bao
If ctx.address_mode is "physical", it will keep as "physical". If ctx.address_mode is "relative to table", it will be changed as "relative to BIOS". Because the "current table" is the whole flash, the code worked well. TEST=Binary identical test on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I9acb54cc5de149d8a705bb05bf351c44b7d3ced1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-27amdfwtool: Add universal cleanup functionZheng Bao
Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24amdfwtool: Add missing parentheses in macro definitionZheng Bao
Change-Id: I1b43dbb8cdc748960f25d7b0629aa81528a2a476 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24amdfwtool: Change the growing pointer with cautionsZheng Bao
Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24amdfwtool: Remove the useless variable "rom"Zheng Bao
Now we use ctx.rom. Remove the wrong statement releasing null pointer. Change-Id: I134335ed741dc067e232621106f2057e50ba6a1a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19crossgcc: Replace binutils no-bfd-doc patch with configure optionElias Souza
It is not more necessary to patch binutils, we can pass an argument during build time to not build docs. Regenerate binutils-2.37_no-makeinfo.patch. Change-Id: If600f0bb46db5f84956940683a7adc83eaca01e5 Signed-off-by: Elias Souza <eliascontato@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73115 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-18util/spd_tools/src/spd_gen/lp5.go: Support LP5X 8533MbpsKyle Lin
Add support for LP5X 8533Mbps in SPD tool. BUG=b:263189532 TEST=None Change-Id: I72b02514f68647dda996822f910db8bc93f61ca4 Signed-off-by: Kyle Lin <kylelinck@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marx Wang <marx.wang@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-17util/crossgcc: Update GCC from 11.2 to 11.3Felix Singer
While the work on updating GCC to version 12 is still WIP, update it to the latest minor release 11.3. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I8810bbb238b01985774ff8da1e246ab1b192e663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70221 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-17lint/checkpatch.pl: Remove check for keyword 'boolean' in KconfigElyes Haouas
We can not use 'boolean' since commit 53ea1d44 "util/kconfig: Uprev to Linux 5.13's kconfig". This also reduce difference with upstream. Change-Id: Iff9fbde46784547c07726816d2fdd71967e0595e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-15util/release: Update build-release scriptMartin Roth
- Make variables for the release name and the tarballs instead of writing them out every time. - Skip some more unnecessary files when creating the tarballs. - Remove unnecessary check for the commit ID. It's now a required field. - Correctly get and save the time of the last release for use in creating the tarballs. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I56cd5e2dcf01ee55e5d45e837db2f89904b06ddd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-14amdfwtool: use SoC ID info instead of misleading comboable flagZheng Bao
Since it actually depends on the SoC type whether the old PSP directory table pointer or the new comboable PSP directory table pointer is used in EFS, get this information from the SoC ID instead of passing the comboable flag for the SoCs that need to use the new comboable PSP directory table pointer. TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-13amdfwtool: Remove command line option soc-nameZheng Bao
5/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Iba2ebd5d0310538e04c07493d28039509ad02321 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-13util/autoport: Fix the typo of ehci2 in bd82x6x.goIru Cai
This corrects the word "echi2" to "ehci2". Change-Id: Id8911de147538f4614627cfca449bad528ab6780 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-11amdfwtool: Put soc name setting to fw.cfg from command lineZheng Bao
The fw.cfg should combine the SOC name. This is for future combo feature. Each entry in combo has its own fw.cfg. The soc_id in struct cb_config can only be available after the fw.cfg is processed. Some functions which take soc_id as a parameter can be simplified. 3/5 (and the key one with same change ID) of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-10util/chromeos/extract_blobs: allow passing dest dir as argMatt DeVillier
Allow user to pass the output dir for the extracted blobs as the 2nd argument to the script; if not provided, fall back to the existing default. Change-Id: I0f120b69e0b6d14c2763b9a3b2a622e77c4fe0d4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-10amdfwtool: Move soc_id to cb_configZheng Bao
Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 17:50:25 +0000