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2024-05-08util/chromeos/crosfirmware: ensure $BOARD is lowercaseMatt DeVillier
If $BOARD is not all lowercase, then certain subfunctions of the script will fail due to case-sensitive comparisons therein. To avoid this, since all matched strings are fully lowercase, set $BOARD to lowercase. TEST: './crosfirmware.sh {akemi/Akemi/AKEMI}' all succeed. Change-Id: I8ecb613a8d9384e2cccaff5183470e2e9956d0a2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-06util/util_readme: Update post_util.md for MyST ParserNicholas Chin
This file is appended to Documentation/util.md by the util_readme.sh script, and contains toctree entries for utilities with more in-depth documentation than the description automatically pulled from the description.md files throughout the util directory. As of commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser), the syntax for creating a toctree has changed, so update this post_util.md accordingly. Change-Id: Ia7ae3c513781e53512763578fd97db7e2f75e65c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-05-04docker/coreboot-sdk: Replace 'pkg-config' with 'pkgconf'Elyes Haouas
Replace transitional 'pkg-config' package with 'pkgconf'. Change-Id: I9ee895cb2ca3186c4aefbdab1fd71778bf981009 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82167 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-26util/docker/coreboot-sdk: Remove libcurl4 from the package listMichał Żygowski
When installing the packages, apt-get returns an error about holding broken packages. It occurs the diffutils depends on libcurl4t64 which breaks the libcurl4. As a solution, remove the libcurl4 from the list, and let the package manager resolve the dependencies. TEST=Build coreboot-sdk Change-Id: Iabc4f74619d4462317d8adb4068e50135d89d80e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-25util/ifdtool: Add support for checking GPR0 statusTyler Wang
This patch adds support for the new command-line option `-c` to the ifdtool, which is able to check GPR0 (Global Protected Range) status. This patch also add helper function get_enabled_gprd() to get enabled GPR0 settings. It used in enable_gpr0() and is_gpr0_protected(). Developers can use ifdtool with '-c' option to check whether GPR0 is set to enabled or disabled in the binary file. BUG=none TEST=(1) > ifdtool -p mtl -E image-unlocked.bin -O image-lock.bin ... Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff ... GPR0 protection is now enabled (2) > ifdtool -p mtl -c image-unlocked.bin GPR0 status: Disabled Value at GPRD offset (64) is 0x00000000 --------- GPR0 Protected Range -------------- Start address = 0x00000000 End address = 0x00000fff (3) > ifdtool -p mtl -c image-lock.bin GPR0 status: Enabled Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff Change-Id: I6b3af973be784200b965a68e5f6b7737cba03ed7 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2024-04-20util/lint: Add lint rule to watch for Makefile.incMartin Roth
This should keep new makefiles from being named Makefile.inc. Change-Id: I4a47998e1c997b82b8a15319eae96cdc0de64e77 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81857 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-17util/crossgcc/buildgcc: Use Intel mirror for ACPICAFelix Singer
The binary hashes from GitHub releases are not stable. Use the Intel mirror. Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80721 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-16buildgcc: Match the string of downloading percentage more preciselyZheng Bao
The command "wget" prints some hyperlink with "%", which will be filtered in by previous regular expression. So we need to change to match the string with exactly 3 digits and a percent symbol. TEST: echo 45% | grep -o "\<[0-9]\{1,3\}%" 45% echo 1245% | grep -o "\<[0-9]\{1,3\}%" <empty> echo aa% | grep -o "\<[0-9]\{1,3\}%" <empty> Change-Id: I6ef9e7c87fd4ee6cc707346954d91e6e3af3b939 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-04util/intelp2m: Add support for TigerLake-H SoCAlicja Michalska
Add support for TigerLake Halo SoC, based on CNL profile. Test: Convert GPIO dump from inteltool into coreboot macros for out-of-tree TGL board. Change-Id: I26eff225c2045edfe5836283be7b4c63f6b405e8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-04-03util/kconfig: Uprev to Linux 6.8's kconfigPatrick Georgi
Linux kconfig has its own implementation of KCONFIG_WERROR now, so use that. This reduces our patch count by 2. Change-Id: I4f5f1f552e96f8ef7a4c5c0ab2ab7e2b6d798ceb Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81223 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-02util/kconfig: Put our SPDX fix in the patch queuePatrick Georgi
With this, `quilt pop -a` leads to an original Linux kconfig tree, making it easier to apply kconfig updates. Change-Id: I771bbd0f8244cae38317bd5b1f809b74771b176f Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-30util/crossgcc: Also build LLVM LDArthur Heymans
When doing LTO the clang linker frontend needs to use LLD or gold. Build LLD as that is the configuration that is best tested. Change-Id: I3242585f8b5c3426fc6568d3dc47300164d56e3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-30util/xcompile: Use a more complete clang targetArthur Heymans
When the compiler is used as a linker frontend clang tries to match the target string with what it supports internally. If it's not sufficiently complete it will forward linking to GCC which is not desirable. This is necessary when doing LTO with clang. Change-Id: Ie9356a2bc0f5b77e934cc16482d6ccb1961195dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80730 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-27cbfstool: Add printing of legacy stage typeVladimir Serbinenko
This is useful for listing older images. Change-Id: I588028d4327f59538f7c9920b671458fc631cb4c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-26util/xcompile: Add target architecture to CPPFLAGSArthur Heymans
In order to preprocess linker scripts the target architecture needs to be specified. With clang this needs to be set via a cli argument. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-23amdfwtool: Use macro to get the table relative addressZheng Bao
TEST=Identical binary test on all AMD SOC platform Change-Id: Iece4ba65e0476543a8d472168d93801714330dde Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78281 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23util/lint: Fix license header regexNicholas Chin
A trailing "|" at the end of the regex added a zero length alternative match, causing all files to match and be filtered out. This was causing `make lint-stable` to ignore all missing license headers, preventing the pre-commit git hook and Jenkins from detecting these. Also, a missing "|" separator between cmos.default and .apcb would cause those files to be unintentionally scanned. Change-Id: I70cc3a5adf7edee059883cd3cbe02029776b02ef Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-22amdfwtool: Only update count in header in only one functionZheng Bao
Other function calls don't have to worry about the fletcher error. TEST=Binary identical test on all AMD SOC platform Change-Id: I7c9d653100b476b52d6d1d80c41d0c3d765f7be3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-21amdfwtool: Move linking BHD2 to PSP2 from main to link funcionZheng Bao
Move the complexity from main to function, so the main flow is easy to understand. TEST=Identical test on all AMD SOC platform Change-Id: Ia549a0d08c2a60b8858440543ac8d8b5259017dd Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-21util/smmstoretool/fv.c: fix 3 formatting issuesSergii Dmytruk
Change-Id: If27218df40e58f249769b3d84c0cd4c299e2282b Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-21util/docker/: Drop recommonmark pip moduleNicholas Chin
The documentation is now built using MyST Parser, so Recommonmark can be dropped. Change-Id: I7f6810c9429573c0c51d3d72b36e9fc2ae2185f5 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80313 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21util/docker: Update Dockerfiles for building documentationNicholas Chin
Update all pip packages related to coreboot's documentation to their latest available version, and update the doc.coreboot.org base image to Alpine 3.19.1. Add myst-parser in preparation to switch from Recommonmark to MyST Parser. TEST: The documentation builds and renders properly when built using the updated container. Change-Id: I8df4aadabc49c0201a836333745fe138184595ac Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80312 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21docker/doc.coreboot.org: Install pip modules into virtual envNicholas Chin
Currently, pip modules are installed system-wide, which may cause conflicts with modules installed using the package manager. Newer versions of the Alpine base image also mark its system wide Python installation as an externally managed environment, which will cause pip to return an error as per recent Python recommendations [1]. TEST: - `make -C util/docker doc.coreboot.org` builds the container successfully - `make -C util/docker docker-build-docs` builds the documentation successfully [1] https://peps.python.org/pep-0668/ Change-Id: Idd9cc5e6fb28b42ef8e4fa5db01eb9ef192ba0ec Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-20amdfwtool: Check sanity before filling the data arrayZheng Bao
Change-Id: I8284c35a0124ba4588d199024e28d3445c681896 Signed-off-by: Zheng Bao <fishbaozi@gmail.com>wq Reviewed-on: https://review.coreboot.org/c/coreboot/+/78763 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20amdfwtool: Set the cookie when the table header is createdZheng Bao
When the table is created, the cookie is known. When the packing going on, the cookie in header can be checked to see where we are. TEST=Identical test on all AMD SOC platform Change-Id: I300e30292c68a14b44c637b26a13b308dc9c0388 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81254 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20amdfwtool: Move the header creation into integration functionZheng Bao
Before every integration there is a header creation. We can put them together. And the parameters for PSP/BIOS tables are useless. TEST=Identical test on all AMD SOC platform Change-Id: Ia9d78bb8145855203048208fcd67f8b9cd9d3199 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-20amdfwtool: Add functions to link all the tablesZheng Bao
The purpose of integration function is to pack the FWs into table. We need to remove other process. Create a dedicate function to link all the tables together. And this linking function is only called when both the level 1 and level 2 directory are created. This simplifies the main function and logic. TEST=Identical test on all AMD SOC platform Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-20amdfwtool: Move the address of tables to the contextZheng Bao
Instead of being local variables. This can be easier to find all the tables anywhere. TEST=Identical test on all AMD SOC platform Change-Id: I98b7d01e32c75b4f13e23d496cd3de3da900678d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-18amdfwtool: Compact the parameter transferingZheng Bao
Remove redundant parameter "debug" from open_process_config(). Change-Id: Ib91a505838d7be4980d6b4f1e95fb8601fbbfd16 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81201 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18amdfwtool: Remove the dissociated combo BIOS table for recovery A/BZheng Bao
For recovery A/B mode, the BIOS tables level 2 are traced by PSP table instead of ROMSIG. There should not be a dedicated BIOS table, nor a combo BIOS table. Change-Id: I8735bd91b32bc9a0e4fc70d293e8d836d5e9c36b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17genbuild_h: Fix and harden major/minor version parsingNico Huber
Our major version is suddenly two digits long to represent the year. This can't be parsed with the current sed scripts. To make sure that no unparsed data ends up in our major/minor versions, we'll run sed with `-n' and only print the extracted numbers if anything. Also, to allow us to use the version numbers in C code, we strip leading zeros (a leading 0 identifies octal numbers, so for instance 08 for August is not a valid number). This can result in empty major/minor version strings, so we move the default `0' to the final variable expansion. As a bonus, this makes an explicit check if the numbers can be parsed unnecessary. Change-Id: Ie39381a8ef4b971556168b6996efeefe6adf2b14 Reported-by: Christoph Zechner <christophz@vrvis.at> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81290 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17util/intelmetool: Print the address in `map_physical` errors in hexMate Kukri
Previously the incorrect 'd' format specifier was used despite the '0x' prefix implying hex to the user. Change-Id: Ib97bd86ee0e0c8fe8c3785e22a4d9f6def3cae61 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-17amdfwtool: Set the level based on cookieZheng Bao
It was complicated and weird to check both the cookie and whether one table is a null pointer. Just checking the cookie is enough. TEST=Identical test on all AMD SOC platform Change-Id: Icab74714990f74e11fd5e899661e4e2d41230541 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17amdfwtool: Set the table size only for FWsZheng Bao
The entry in the table has two categaries, file and pointer. For the pointer, it does not take table space. The ISH, PSP level 2, BIOS table are all the pointer type. So integration function only packs FWs located in folder amd_blobs. And only FWs increase the table size. So the table size is only set once. Later calls only update the count and fletcher. The table has a header at least, so the size can not be 0. The fill_dir_header can take the parameter count as 0, such PSP level 1 only with ISH-A and ISH-B. It doesn't have any file type entries. This actually reverts https://review.coreboot.org/c/coreboot/+/78274 and adds other changes. TEST=Identical test on all AMD SOC platform Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81255 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17util/lint/lint: Fix shellcheck errors in getopt support for darwinMartin Roth
Posix shell doesn't support '==' Change-Id: Icbdc4204f4c07d806e721fa39f96694c4df00e8d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81285 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14util/nixshell: Add a dev shell for i386 archCrabtux
Add a Nix shell file to provide a simple environment for coreboot development of i386 architecture. Currently, this environment is capable of completing Tutorial Part 1 in https://doc.coreboot.org. The Nix shell can be used by running the following command: $ nix-shell --pure util/nixshell/devshell-i386.nix The `--pure` parameter is optional. In Nixpkgs, there is a package called 'coreboot-toolchain'. It fetches the source code of coreboot, build crossgcc, and export it as output. With the binary cache mechanism of Nix, crossgcc can be directly downloaded and used without compiling on user's machine. This Nix shell has been tested on a NixOS laptop and a Debian 12 server, and they both work fine. Change-Id: Idcfe10be214e9bca590a62b8a207267493a4861f Signed-off-by: Crabtux <crabtux@mail.ustc.edu.cn> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-13cbfs: Remove broken remnants of PAYLOAD_INFO featureJulius Werner
PAYLOAD_INFO is a very old feature that can add a key/value information section to a payload file. It seems to have only ever been generated by coreinfo and never really read by anything. Since CB:1721 in 2012, the feature has been inadvertently broken in practice since the `.note.pinfo` sections that contain the information get discarded from the payload before cbfstool gets to see them. Since CB:28647 in 2018, support for the section in the SELF loader was (inadvertently?) dropped, so if someone actually fed cbfstool a payload ELF that did have a `.note.pinfo` section, modern coreboot would refuse to boot the payload entirely (which is probably not a good state to leave things in). This patch removes the code to generate PAYLOAD_INFO entries entirely, but leaves the support to parse and extract those sections from old payloads in place in cbfstool. Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-13util/inteltool: Add support for Alder Lake-NBrandon Weeks
Reference: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2 (#759603) Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562 Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-03-09util/docker/Makefile: Create Documentation/_build for docker-build-docsNicholas Chin
If the host directory of a bind mount does not exist, Docker will create it. However, the newly created directory will be owned by root due to the Docker service running within a root context. The docker command in the recipe for docker-build-docs binds Documentation/_build to /data-out within the container, so if it doesn't already exist, the documentation builder will be unable to copy the HTML output into /data-out since it runs with the same UID and GID as the host user. By creating, if necessary, the _build directory before the `docker run` command, there should always be an existing directory owned by the host user for docker to bind /data-out to (ignoring the case of an existing _build directory the current user does not have permission to write to), avoiding the issue where it cannot write the output. TEST: make -C util/docker docker-build-docs completes without issues with and without an existing Documentation/_build directory Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81127 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-09util/smmstoretool: support processing ROMsSergii Dmytruk
Input file is parsed for FMAP and SMMSTORE region which is used if found. Otherwise, the whole file is assumed to be the region. Passing an image with FMAP that lacks SMMSTORER is an error. Change-Id: Ieab555d7bbcfa4dadf6a5070d1297acd737440fb Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09util: add smmstoretool for editing SMMSTORESergii Dmytruk
Offline SMMSTORE variable modification tool. Can be used to pre-configure ROM image or debug EFI state stored in a dump. Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-08drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 supportJeremy Compostella
Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-06amdfwtool: Change&Record the current table in integration functionZheng Bao
Align with the function integrating PSP FWs. And it is the integration function's responsibility. TEST=Identical test on all AMD platforms Change-Id: I1a98614f3a5756a462b01085e9565b52cf9a9343 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06amdfwtool: Move code related to getting options to a new fileZheng Bao
Cleanup the messy code. The code left in main is all about filling tables. To help to do this, 1. Some local variables are put into global struct. 2. Add some functions. Set some functions to global. TEST=Identical test on all AMD platforms Change-Id: Ia25c3fd5de7ae48054359f0f6551d91d7a4f6828 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06amdfwtool: Set the table size for L1 separatelyZheng Bao
The space defined by size of the L1 table can not overlap with ISH header. For other cases, the size defines the directory and its content. The PSP spec does not say it quite clearly. This change is partly based on guess and can make extraction tool work so far. Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-05mb/emulation/qemu-riscv: Change to -bios optionMaximilian Brune
This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-04amdfwtool: Move the functions to handle_file.cZheng Bao
Change-Id: I4cfec13cbc2a86dc352758541cce915a838e0d0f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78305 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04amdfwtool: Remove the function's dependency to ctxZheng Bao
This is for next CL to move the write_body to another source, handle_file.c. https://review.coreboot.org/c/coreboot/+/78305 Removing amdfwtool_cleanup in write_body will not change the result. Write_body returns to main and amdfwtool_cleanup still ends up getting called. Change-Id: I639828498fa45911f430500735e90ddc198b6af5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78304 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-02lint: Make lint work on DarwinStefan Reinauer
Darwin's getopt does not support the same parameters as the util-linux version and so it is not possible to commit any changes because lint fails. Change-Id: Ife26083d2de080af9ed3d509945720051ca14bd7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80436 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29amdfwtool: Use Makefile.mk for Makefile settingsMartin Roth
When updating the Makefiles, to keep from having to update two files at the same time, import Makefile.mk into the external Makefile. This allows the bulk of the settings to be in a single location. While I'm here, I adjusted the print statements to match the rest of coreboot. Change-Id: Id5b869f49b34b22e6a02fc086e7b42975141a87e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-26docker/coreboot-sdk: Add mesonArthur Heymans
This is needed to build opensil. With meson and ninja added to the coreboot-sdk image there is no need have them in the jenkins node image. Change-Id: I36188ae895f2a770f1dc4528f332c09bf386db73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-26util/amdfwtool: build amdfwtool only for all tools or AMD CPUsMartin Roth
When we're building non-AMD processors, don't bother building amdfwtool unless we're specifically building all of the tools like for abuild. Change-Id: I9021674a06d65a79e24020790d317ab947c505fe Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80714 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-24crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3Elyes Haouas
Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-22riscv/mb/qemu: fix qemu invocation commentPhilipp Hug
Change-Id: I773fb39801f180fead584942dfb385fcde9d2680 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80262 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-02-20util/crossgcc: Update LLVM from 16.0.6 to 17.0.6Felix Singer
Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20crossgcc: Upgrade binutils from 2.41 to 2.42Elyes Haouas
Change-Id: I6e9b2dac6fed702e8e353290971699cb9ee05dfc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19util/liveiso/nixos: Install lm_sensors packageFelix Singer
Change-Id: I6b027ed39d3ee81878e069142c2d7212f3dc0a6f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2024-02-18cbfstool: Support 64bit addresses for flat imagesPatrick Georgi
SELF has the fields wired up for 64bit, but adding flat images cuts the upper half. Change-Id: I3b48b8face921e942fb0e01eace791ad3e1669a0 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80576 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18util/crossgcc/buildgcc: Compile RISC-V GCC with medanyMaximilian Brune
currently the HiFive Unmatched mainboard produces the following error: ``` util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a (_clzsi2.o): in function `__clzdi2': util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in .rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/ rv64imafdc/lp64d/libgcc.a(_clz.o) ``` This is due to the fact that the libgcc.a library is compiled with the medlow code model but the mainboards are compiled with the medany code model. Changing the code model of the GCC libraries to the medany code model fixes the issue. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18util/cbfstool/linux_trampoline: Support more e820 entriesPatrick Rudolph
Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866 "[PATCH] Increase number of e820 entries hard limit from 32 to 128" made in 2005 the number of e820 entries passed from the bootloader is 128. Use the boot protocol version to check for support of 128 entries and use them if necessary. Tested on IBM/SBP1: Fixes booting a Linux payload when more than 32 entries are present in the memory table, which can easily happen on a 4 socket platform. Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18Treewide: Fix incorrect SPDX license stringsMartin Roth
These strings didn't match the license names exactly, so update them to match. Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-15util/ifdtool.c: Fix long_options for platformVojtech Vesely
Platform has argument, but has_arg was mistakenly set to 0. Change-Id: I7d5c31c2b1da544cb73d9e213d463332fcdba7df Signed-off-by: Vojtech Vesely <vojtech.vesely@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80432 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2024-02-14util/showdevicetree: drop unmaintained toolFelix Held
This tool doesn't have a makefile, when trying to compile it manually with the given instructions it even fails to compile after fixing the paths in the given command, and it references the non-existing PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79934 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-12util/intelmetool: Add Intel Union Point supportNicholas Sudsgaard
The device IDs were taken from the 200 series datasheet (page 24). Change-Id: I34b5cb61dd7b561778cc8506858cd436e6f04f9a Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80419 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-12crossgcc: Add buildgcc support for Apple M1/M2 devicesStefan Reinauer
GMP and IASL don't compile with the default compiler and linker flags: - GMP's check for the MacOS architecture hard coded x86_64 but it also needs to know about arm64. - iasl does some trickery on pointer alignment to save space(?), so we need to tell clang about it. Change-Id: If4cca9d3e55051a6121d992e5320bee1df17af9f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80435 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-05util/kconfig: Uprev to Linux 6.7's kconfigPatrick Georgi
Just a memory leak fix in Linux 6.7. Change-Id: I1ff302dafa01e78429a30ff18e21ffe0b45ce46e Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80263 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-02util/cbmem: Use commonlib ipchksum() algorithmJulius Werner
This patch switches the cbmem utility from its own IP checksum implementation to the commonlib version (which is good because the old one had a couple of bugs: doesn't work on odd sizes and may overflow its carry accumulator with input larger than 64K). Change-Id: I0bef2c85c37ddd3438b7ac6389e9daa3e4955b31 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80256 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-02util/ifdtool: Add a new switch -E to protect GPR0Subrata Banik
This patch adds support for the new command-line option `-E` to the ifdtool, which enables users (primarily factory users) to protect GPR0. Additionally, this patch refactors some code while adding support for enabling GPR0 protection. For more information on the scope of GPR0 (General Protection Range 0), please refer to the Intel Meteor Lake-U Type 4 Client Platform SPI Programming Guide, Document Number 768150. BUG=b:270275115 TEST=Able to test GPR0 protection on google/rex and google/yahiko. > ifdtool -p mtl -E image.bin -O image.bin_lock ... Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff ... GPR0 protection is now enabled Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-30crossgcc: Distinguish bootstrap and target compiler optionsPatrick Georgi
GCC_OPTIONS is only used for target specific options right now, so rename to TARGET_GCC_OPTIONS and only use them in the non-bootstrap build. Adapt BINUTILS_OPTIONS for consistency, even though it doesn't have the same problem. Change-Id: I5e4f54b758dd7daf4e69101c19dfa1212fa64cf6 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80229 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-30util/release: Remove makefile.inc references from genrelnotesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id86ebc20cf5af5b65812c3f09235d0cba86d13f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80126 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-29device/device.h: Drop multiple linksArthur Heymans
Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-27util/ifdtool: Refactor GPR0 Unlock ImplemetationSubrata Banik
This patch refactors GPR0 unlock function to add few important logic as below 1. Perform GPR0 unlock if GPR0 is locked. 2. While unlocking dump the GPRD PCH strap details 3. Additionally, print the GPR start and end range if GPR0 protection is enabled. TEST=Able to test GPR0 protection on google/rex and google/yahiko. Exp 1: Trying to unlock GPR0 protection for a locked image > ifdtool -p mtl -g image.bin -O image.bin_unlock File image.bin is 33554432 bytes Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff Writing new image to image.bin_unlock Exp 2: Trying to unlock GPR0 protection for a unlocked image > ifdtool -p mtl -g image.bin_unlock -O image.bin_unlock File image.bin_unlock is 33554432 bytes GPR0 protection is already disabled Change-Id: Id35ebdefe83182ad7a3e735bdd2998baa0ec3ed7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80216 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-26src, util: Clean up makefile.inc in text, help & commentsMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib69236fb5d68272f92405512dc231fa75ecccaa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26src, util: Update toolchain.inc references to .mkMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ieaf7894f49a90f562b164924cc025e3eab5a3f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-26util/autoport: Update Makefile.inc generation to Makefile.mkMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib77cb3a0852092ac414fe0160fe10d6e58fcf660 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80127 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26util/mb: Update variant template Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2a6a4d1eb7e0d0cd32c8690caf3eff340cdb0d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80124 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26util: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I434940ebb46853980596f7ad55d27a62c90280fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/80123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-24util/spd_tools: Update Makefile.inc references to Makefile.mkMartin Roth
Make sure that any new files generated get the Makefile.mk name. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3880d5911ff8de01751befdffc99ba5a961416f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80113 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24*/mem_parts_used.txt: Change Makefile.inc to Makefile.mkMartin Roth
Now that the files are renamed, make sure all references to Makefile.inc are updated as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24payloads: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie7038712de8cc646632d5e7d29550e3260bf2c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80103 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24Makefiles: Rename top-level Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. The rest of the Makefiles will be renamed in following commits. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Idaf69c6871d0bc1ee5e2e53157b8631c55eb3db9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80063 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-18util/superiotool: reformat alternate dump outputMatt DeVillier
Reformat alternate dump output to show default values before read values, and to use brackets to visually indicate which values differ from the defaults. old output: Register dump: idx val def 0x07: 0x0b (0x00) 0x10: 0xff (0xff) 0x11: 0xff (0xff) ... new output: Register dump: idx def val 0x07: 0x00 [0x0b] 0x10: 0xff 0xff 0x11: 0xff 0xff ... TEST=build/dump registers from Erying SRMJ4 w/Nuvoton NCT6796D. Change-Id: Idef2cc136151328b114620eb297ab8fd62b71bcd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80004 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-18util/superiotool: add support for Nuvoton NCT6796DMatt DeVillier
Registers and default values taken from public datasheet: https://www.nuvoton.com/resource-files/NCT6796D_Datasheet_V0_6.pdf TEST=build/dump SIO registers on Erying SRMJ4 mainboard Change-Id: I0ff940a17b0c38a5ca66e90dd4e075a2b04dcfc1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80003 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18util/inteltool: Add support for RPL-H CPUMatt DeVillier
Add PCI IDs and descriptor strings to support the integrated north/south bridges and GPU for the i9-13900H CPU. --- CPU: ID 0xb06a2, Processor Type 0x0, Family 0x6, Model 0xba, Stepping 0x2 Northbridge: 8086:a706 (13th generation (Raptor Lake H family) Core Processor) Southbridge: 8086:519d (Raptor Lake) IGD: 8086:a7a0 (Intel(R) Iris Xe Graphics [RPL-P]) SBREG_BAR = 0xfd000000 (MEM) --- TEST=build/run inteltool on Erying SRMJ4 mainboard, verify PCI IDs not unknown, GPIOs dumped. Change-Id: I4cf3f419f103a1a7d4c6850f2257b7e7d45f3b18 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79962 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-15util/autoport: Improve USB codePatrick Rudolph
Currently autoport fills in USB current '0' if the detected setting isn't one of the known settings. This works as 0 is a valid setting from C point of view, but it's not supported on desktop PCs and on mobile platform results in the lowest possible USB PHY gain. Thus this might cause instabilities as the original firmware had stronger USB drive currents and gain settings. Add more known USB current fields to the map and generate a FIXME as comment when the detected current isn't one of the known entries instead of defaulting to 0. Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78828 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-14tree: Use accessor functions for struct region fieldsNico Huber
Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: Iaae116a1ab2da3b2ea2a5ebcd0c300b238582834 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-12lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONSElyes Haouas
SOUTH_BRIDGE_OPTIONS Kconfig symbol is no longer used. Change-Id: I2380f1ce48afd191755d8b3dcab0b51909f5231f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79913 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-12util/ifdtool: Enable Read Access for SPI device expansion 2 regionSubrata Banik
As per Intel Meteor Lake SPI programming doc, the BIOS region should have a read access enabled for device expansion 2 region (aka region 9). This patch ensures that BIOS region is able to read the device expansion 2 region for Intel Meteor Lake platform as known as SPI padding region. BUG=b:274356894 BRANCH=firmware-rex-15709.B TEST=Able to flash screebo AP FW image using flashrom on DUT. Without this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.67-09255-ge8ae3115f8b0 (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... Transaction error between offset 0x0072f000 and 0x0072f03f (= 0x0072f000 + 63)! read_flash: failed to read (0x72f000..0x7fffff). Read operation failed! FAILED. FAILED With this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.68-09294-g001fdda5287d (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... done. SUCCESS Change-Id: I18c44aa9a0f890f01a889247da118b69a58936e8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-08util/lint: Remove the extra `\` in lint-stable-003-whitespaceRuihai Zhou
A following error occurred when I commit, it seems that the extra `\` after `\.md$` is unnecessary. File Binary file src/mainboard/google/guybrush/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/skyrim/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/zork/data.apcb matches has lines ending with whitespace. test failed Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79782 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-08util/ifdtool: Add support for extended region read/write accessReka Norman
Platforms from CNL onwards support up to 16 flash regions, not 12. The permissions for regions [15:12] are stored in extended region read/write access fields in the FLMSTR registers. Currently ifdtool treats these fields as reserved, so they're not modified when locking or unlocking. Add support for extended regions so that they are locked/unlocked by the --lock/--unlock options. This will make the locked/unlocked descriptors generated by ifdtool match those generated by mFIT. BUG=b:270275115 TEST=Without this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 ff 07 20 00 ff 05 40 00 ff 00 00 00 00 00 00 00 00000090 ff 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 00 ff ff ff 00 ff ff ff 00 ff ff ff 00 00 00 00 00000090 00 ff ff ff With this change: `ifdtool -lr -p adl` on unlocked image: Before: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff After: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 `ifdtool -u -p adl` on locked image: Before: 00000080 00 07 20 00 00 05 40 00 00 00 00 00 00 00 00 00 00000090 00 00 00 00 After: 00000080 ff ff ff ff ff ff ff ff ff ff ff ff 00 00 00 00 00000090 ff ff ff ff Change-Id: Iaa43524d91c399a996ade56f2f613b4110a44aad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-05util/ifdtool: Add support for disabling GPR0Reka Norman
On ChromeOS devices with updateable CSE firmware, the GPR0 (Global Protected Range) register is used to ensure the CSE RO is write protected even when the FLMSTR-based protection is temporarily disabled by coreboot to allow updating the CSE RW. For more details see Documentation/soc/intel/cse_fw_update/cse_fw_update.md Therefore to allow modifying the CSE firmware from the CPU, the descriptor must have both the FLMSTR-based protection disabled (which can be done using ifdtool --unlock), and GPR0 disabled. Add an ifdtool option for disabling GPR0. For now I've added support for all platforms for which I have the SPI programming guide. Support for more platforms can be added in the future if needed. BUG=b:270275115 TEST=Run `ifdtool -p adl -g image.bin -O image-unlocked.bin` on a locked craask image, check the GPR0 field is set to 0. Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79788 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-29util/liveiso: Update to 23.11 releaseFelix Singer
The package 'bluezFull' got superseded by 'bluez'. So just remove the related line since 'bluez' is the default. Change-Id: Ibf72c37205017b27012064b311a9510136351c0f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-29util/docker/fedora: Add Dockerfile.baseFelix Singer
Following commands were used to test if everything builds: * make crossgcc * make clang * make what-jenkins-does Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-20util/{cbfstool,nvramtool}: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I2dd0c2ccc4f4ae7af7dd815723adf757244d2005 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17util/lint: Exclude .apcb files from various checksMatt DeVillier
.apcb files are binary configuration data and not human readable; exclude them from license, newline, and whitespace checks. Change-Id: Idc1ddd5067cb97ef8b5758a0b8bf040d1e421871 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-13lib/jpeg: Replace decoder with Wuffs' implementationPatrick Georgi
To quote its repo[0]: Wuffs is a memory-safe programming language (and a standard library written in that language) for Wrangling Untrusted File Formats Safely. Wrangling includes parsing, decoding and encoding. It compiles its library, written in its own language, to a C/C++ source file that can then be used independently without needing support for the language. That library is now imported to src/vendorcode/wuffs/. This change modifies our linters to ignore that directory because it's supposed to contain the wuffs compiler's result verbatim. Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that implements our JPEG API. I further changed it a bit regarding data placement, dropped stuff from our API that wasn't ever used, or isn't used anymore, and generally made it fit coreboot a bit better. Features are Nigel's, bugs are mine. This commit also adapts our jpeg fuzz test to work with the modified API. After limiting it to deal only with approximately screen sized inputs, it fuzzed for 25 hours CPU time without a single hang or crash. This is a notable improvement over running the test with our old decoder which crashes within a minute. Finally, I tried the new parser with a pretty-much-random JPEG file I got from the internet, and it just showed it (once the resolution matched), which is also a notable improvement over the old decoder which is very particular about the subset of JPEG it supports. In terms of code size, a QEmu build's ramstage increases from 128060 bytes decompressed (64121 bytes after LZMA) to 172304 bytes decompressed (82734 bytes after LZMA). [0] https://github.com/google/wuffs Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Based-on-work-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78271 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12util/abuild: Better identify config string in logMartin Roth
When using the --skip_set and --skip_unset arguments, the config line looked like a statement that the build was being skipped instead of abuild just printing the configuration. This updates those config statements to better show that it's the config and not stating that this particular build is being skipped. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6cc59f9b33dcda51aeb3640d449037a0aa054e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76936 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08util/docker/alma: Add Dockerfile.baseFelix Singer
Following commands were used to test if everything builds: * make crossgcc * make clang * make what-jenkins-does Change-Id: Iab15fe908aa6ca81724ed7557caf70c38817ad25 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>