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2022-08-26util/amdfwtool: Add changes to reserve BIOS SIGRitul Guru
changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-25util/apcb/apcb_v3_edit: Add support for LP5X SDRAMRobert Zieba
This commit adds support for LP5X SDRAM. BUG=b:242765117 TEST=Ran with LP5X SPDs and manually patched APCB Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I2d3cb9c9a1523cb4c5149ede1c96a16c3991a5d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66840 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25util/spd_tools: Add support for LP5X SPDsRobert Zieba
This commit adds support for LP5X SPDs. The SPD format is identical to LP5 except that the memory type is set to 0x15 instead of 0x13. Since they are essentially the same, LP5/5X parts share the same parts JSON file and SPD directory. LP5X parts are distinguished by the optional `lp5x` attribute. This commit also updates two existing LP5X memory parts with the correct attribute. BUG=b:242765117 TEST=Generated SPDs, verified that SPDs generated from LP5X parts match their LP5 counterparts except for memory type byte. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-22lint-000-license-headers: Add src/sbom/TAGS to exception listFelix Singer
Commit 6dac0c54cd0b makes the linter checking for license headers on all files from the src directory. Since this TAGS file doesn't have one, it's causing a linter error and it makes the QA system complain. However, the TAGS file doesn't need a license header and thus add it to the exception list. Usually the build tests detect such issues, but commit 1d7a9debf241, which introduced that file, was merged independently from the other commit, which modifies the linter. Also, the patch that is introducing this file was based on an older commit at which the patch modifying the linter wasn't merged yet and so this issue was hidden. Change-Id: I78da3fa70c39b709478a384da8769fc058ca18ce Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66938 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22util/crossgcc: Remove binutils related MIPS patchFelix Singer
coreboot doesn't support the MIPS architecture anymore. So remove the MIPS patch. Change-Id: I62a2bca141b42ac33b628c48c84422570f4dda10 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-22Add SBOM (Software Bill of Materials) GenerationMaximilian Brune
Firmware is typically delivered as one large binary image that gets flashed. Since this final image consists of binaries and data from a vast number of different people and companies, it's hard to determine what all the small parts included in it are. The goal of the software bill of materials (SBOM) is to take a firmware image and make it easy to find out what it consists of and where those pieces came from. Basically, this answers the question, who supplied the code that's running on my system right now? For example, buyers of a system can use an SBOM to perform an automated vulnerability check or license analysis, both of which can be used to evaluate risk in a product. Furthermore, one can quickly check to see if the firmware is subject to a new vulnerability included in one of the software parts (with the specified version) of the firmware. Further reference: https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/ - Add Makefile.inc to generate and build coswid tags - Add templates for most payloads, coreboot, intel-microcode, amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM, intel ME and compiler (gcc,clang,other) - Add Kconfig entries to optionally supply a path to CoSWID tags instead of using the default CoSWID tags - Add CBFS entry called SBOM to each build via Makefile.inc - Add goswid utility tool to generate SBOM data Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-18util/nixshell/toolchain: Update GNAT to version 12Felix Singer
Change-Id: I308dc7640e16b7cfb7679d81099d8896f3f454fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-17util/lint: Check files of all sizes for licensesMartin Roth
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ib97d009c056b487136f20e5341b31183c65ef761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-17util/lint: Update to check all of src for license headersMartin Roth
This wasn't done previously because not all files in the src directory had the correct headers. Doing this earlier would have broken the build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ia6d7a7a17116e4c8e55354783085355fd45ff87a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66505 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-13util/release: Update genrelnotes with the latest versionMartin Roth
This is the version of genrelnotes that was used to help with the 4.16 release. - Fix shellcheck issues. - Send messages for the user to STDERR. - Add recent platforms - Handle symbolic links to the git repo. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2204793a5d1cc5792d0720d2bbfb172bb6020dd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-08-13payloads/tianocore: Rename TianoCore to edk2Sean Rhodes
coreboot uses TianoCore interchangeably with EDK II, and whilst the meaning is generally clear, it's not the payload it uses. EDK II is commonly written as edk2. coreboot builds edk2 directly from the edk2 repository. Whilst it can build some components from edk2-platforms, the target is still edk2. [1] tianocore.org - "Welcome to TianoCore, the community supporting" [2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform firmware development environment for the UEFI and UEFI Platform Initialization (PI) specifications." Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-12amdfwtool/amdfwtool.h: Allow 16 additional PSP entries to be supportedAltamshali Hirani
Consolidate MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com> Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62911 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12util/spd_tools: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I404fcf59e89b75cd2488bcb51981aee2eb4ff0df Reviewed-on: https://review.coreboot.org/c/coreboot/+/66468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11util/amdfwtool: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I673a9b99d207603b605756fc7d277c54c5d0f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66467 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-11util/lint: Add .gitignore files to list that don't need a licenseMartin Roth
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I568a357b40e8bb69b2b26752d241f06adfbe029e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-10util/lint & LICENSES: Add PDDC as a "license" for corebootMartin Roth
The Creative Commons Public Domain Dedication and Certification is not a license in the common sense in that it's stating that the associated file is already in the public domain (having no copyright), and is not actually putting it in the public domain like the CC-C0 license does. The use for this in coreboot is for unlicensable files - either blank files or files with no creative content. This allows these files to have the SPDX identifier to identify them as having no known copyright for open source license compliance. If CC-PDM-1.0 is ever included in the list of SPDX licenses, that would probably fit better, but because the public domain mark isn't actually a license, and because "public domain" isn't well defined, CC-PDM was rejected as a SPDX identifier. For further information: https://web.archive.org/web/20201018194411/https://github.com/spdx/license-list-XML/issues/988 Change-Id: Ibb300ecd066cde2a016195c2beca76a460c588e3 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66496 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10util/lint & LICENSES: Add GCC-exception-3.1 to license exceptionsMartin Roth
The gcov files in the lib directory are licensed GPL 3.0 with the GCC runtime library exception. Add this as a valid license so that the files can get a correct SPDX identifier. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I1cf9c3125592741923c9b4481038055f24fe6ab1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-09utils: Add initial version of "remove_unused_code" scriptMartin Roth
This script creates a patch to remove all of the coreboot code that a platform doesn't use. This is useful for auditing the codebase for an individual platform or releasing a platform's code. Unlike the script that Sage used that did something similar, this keeps the entire Kconfig tree (Though in a single file), all makefiles that are required to build, and the standard build tools can still be used. This will allow for much easier re-integration back into the coreboot codebase if code is released after running this. This is just the initial version and more features needed to be added to make it fully functional. - It should be able to build multiple configurations to retain the code for all of those configurations. - Flag to remove submodules files as well - Additional variable flags to replace hardcoded values. - The list of makefiles that need to be kept is pretty long, and could be updated so that they aren't needed by the top level makefiles. - Add flag to show changed files - Show number of files before and after script is run Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-09util/amdfwtool: Fix ISH_B directory offsetKarthikeyan Ramasubramanian
On boards which use both PSP recovery A/B layout as well as VBOOT A/B layout, ISH_B directory entry is pointing directly to PSP Level2 directory. This is not correct and either ISH_B should be marked as not present or it should point to the ISH_A directory itself which in turn point to PSP L2 directory. Fix it by choosing the latter option. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-06util/elogtool: Mark redundant boot mode event type as `deprecated`Subrata Banik
This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event logging types as below: * ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason while booting into recovery mode * ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into developer mode. * ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into diagnostic mode. Drop static structure `cros_deprecated_recovery_reasons` as it has been replaced by vb2_get_recovery_reason_string() function. ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those related fw boot info along with ChromeOS boot mode/reason etc. BUG=b:215615970 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I932952ce32337e2d54473667ce17582a90882da8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-03util/cbfstool: Fix truncate command error handling and cbfs_image_from_buffer()Jakub Czapiga
Check return value of cbfs_truncate_space() in cbfs_truncate(). Remove return from cbfs_image_from_buffer() to inform about invalid image region when incorrect offset header was provided. Also change header offset provided to mentioned function in cbfs_expand_to_region() and cbfs_truncate_space() from zero to HEADER_OFFSET_UNKNOWN, as they do not support images with cbfs master header. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ib009212692fb3594a826436df765860f54837154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-02util/cbfstool/elogtool: Support logging FW vboot info in elogSubrata Banik
List of changes: 1. Add support for new elog event type to log vboot info (type 0xB7). 2. Add support string for fw_slot name, boot status and boot mode. 3. Print fw slot information like FW try count, FW current slot, previous FW slot, previous FW boot result and boot mode. BUG=b:215615970 TEST=Able to build and boot google/kano to OS. localhost # elogtool list 0 | 2022-07-01 11:10:27 | Log area cleared | 4088 1 | 2022-07-01 11:10:27 | Memory Cache Update | Normal | Success 2 | 2022-07-01 11:10:42 | System boot | 360 3 | 2022-07-01 11:10:42 | Power Fail 4 | 2022-07-01 11:10:42 | SUS Power Fail 5 | 2022-07-01 11:10:42 | ACPI Wake | S5 6 | 2022-07-01 11:10:42 | Wake Source | Power Button | 0 7 | 2022-07-01 11:10:42 | Chrome OS Developer Mode 8 | 2022-07-01 11:10:42 | Firmware vboot info | boot_mode=Developer | fw_tried=B | fw_try_count=0 | fw_prev_tried=B | fw_prev_result=Unknown 9 | 2022-07-01 11:11:42 | System boot | 361 10 | 2022-07-01 11:11:42 | System Reset 11 | 2022-07-01 11:11:42 | Firmware vboot info | boot_mode=Developer | fw_tried=B | fw_try_count=0 | fw_prev_tried=B | fw_prev_result=Success localhost # crossystem recovery_request=1 localhost # elogtool list 41 | 2022-07-13 12:13:48 | Firmware vboot info | boot_mode=Manual recovery boot | recovery_reason: 0x1/0 (Recovery requested from legacy utility) | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48b5d54723683cef51e416fc6f58da000507fbcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/65562 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01util/spd_tools/spd_gen/lp5: Remove maxSpeed for SabrinaKarthikeyan Ramasubramanian
Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01util/amdfwtool: Support PSP whitelist file on recovery A/B layoutKarthikeyan Ramasubramanian
This is required to enable PSP verstage on SoCs with recovery A/B layout. BUG=b:217414563 TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2 directory. Build and boot to OS in Skyrim with both PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-30crossgcc: Upgrade LLVM from 13.0.1 to 14.0.6Elyes Haouas
Test build for QEMU x86 i440fx/piix4. Change-Id: I97d059947f7049b2491a98985795a4655891c3b3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-07-28util/liveiso/common: Install devmem2 and pcimemFelix Singer
devmem2 and pcimem are useful tools which allow working (reading and writing) with memory mapped IO. Change-Id: Ifda547b44af3c8e11cd4171a1dfbce3713455303 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66171 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-26util/amdfwtool: Update the location of PSP verstage and signing keyKarthikeyan Ramasubramanian
On SoCs which use A/B recovery layout, PSP verstage and signing keys are expected to be present only in PSP L2 directory. Update amdfwtool to include the PSP verstage and signing key only in PSP L2 directory. BUG=b:239519603, b:238938623 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-22util/kconfig: Add README.md documenting the uprev procedurePatrick Georgi
Change-Id: I2e74f1c5cb1657e11d4f7ea101549329274102db Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-19util/spd_tools: Limit memory speed to 5500 Mbps for SabrinaKarthikeyan Ramasubramanian
In Sabrina platform, memory speed is limited to 5500 Mbps. Update the SPD generation tool to limit to that speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-19lint/checkpatch: Add check for used comma where semicolon could beElyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d3a49378008bad61b2a18bd8cb28be952a18006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Add a check for use of self-assignmentsElyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If47a7826ee67a2be25a4caa2a447484e5f11411b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Add a check for existence of a commit logElyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e3b98140d900c5717f4badde71c7be88fd1e23a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'Check patch "separator" and "signoff"'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id3d7375216af5bf75ed7ce61fa8ea2dfebe8ac77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for unwanted Gerrit info'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I856bfa0f0d39fda549671b1029cccdc39f831bab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'uncoalesced string fragments'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I21b2a0d87cbf610fc48e273ed78ab779ad4a6932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'concatenated string without spaces between elements'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I04e58aca4a30e82f3da0cda08403d0daf3b5fb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check indentation of a line with a break'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I79170a45cd8184ebc816b4f16656a3cfdc257f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for logical continuations'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I222e3378ded4cd73d0141cd1e38ac3282d311cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for adding lines without a newline'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bd68e9a6609a3dfa7dc856f24e4b616714d9990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19lint/checkpatch: Update 'check for assignments on the start of a line'Elyes Haouas
This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia7d4b0176bad849e79f037f74c3d99ce9eb061c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-15util/xcompile/xcompile: Define GCOV_${TARCH}Yu-Ping Wu
When payloads analyze the coverage using gcov (or lcov), the gcov version must match the CC version. Otherwise gcov would fail to parse the .gcno files. Therefore, define GCOV_${TARCH} in xcompile, so that payloads don't need to do tedious string manipulations to find the right gcov path. Change-Id: If2fc329810c463a3d2c56deaf4e4a3fc3c0a3ed9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-14commonlib: Substitude macro "__unused" in compiler.hBill XIE
Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14util/spd_tools: Add support for 7500 MT/s lp5 modulesJack Rosenthal
spd_tools does not support LP5x modules yet, and the easiest way to do this is to add support for 7500 MT/s in lp5.go (reference the comments on CB:65063). BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=With follow-on CL, run: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14util/spd_tools: Add Intel Meteor Lake (MTL) platformSubrata Banik
This patch add support for MTL platform to the `spd_tools`. This would be useful to create dynamic SPD for rex variants. BUG=b:224325352 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-14Remove executable flag from source codes and text filesPetr Cvek
Markdown, definition file and sconfig source codes don't need to be executables. This patch fixes that. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: Ic97d684318c689259f7895e3dfbd552434c3882e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-12util: Allow installing to a build rootTim Crawford
Modify util Makefiles to allow installing to a build root specified by DESTDIR. Allows using the `install` target for packaging. Change-Id: I3a31ea0fde9922731e1621dcc8f94b2c1326c93c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60540 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-06util/release/build-release: Use `git log … -1` over `|head -1`Paul Menzel
Avoid piping to `head` to print the top line, and do it in `git log` directly. Change-Id: Id9b99b06c5bdd9c381bd039fc1914a9a2f332aa6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-30util/amdfwtool: Initalize all variables before useFred Reitberger
Not all of the fields of the amd_cb_config structure were properly initialized. Rather than initialize each field individually, initialize the entire structure to 0. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-06-27crossgcc: Upgrade CMake from 3.23.0 to 3.23.2Elyes Haouas
Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63123 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23nvramtool: Fix building on Linux systems with musl libcEvgeny Zinoviev
Current implementation only supports glibc (by looking for __GLIBC__) and fails to build on systems with alternative libc implementations, such as musl; sys/io.h is never included, there are no outb/inb functions which results in undefined references at linking stage. Using __linux__ instead of __GLIBC__ to test whether the system is Linux seems to be a more proper way to detect Linux and it also fixes nvramtool compilation on musl systems. Tested on Gentoo Linux with musl 1.2.2 (builds and works fine) and Void Linux with glibc (still builds and works fine). Change-Id: Idcdc3a033b40f16a6053209813f1e06209ee459a Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48757 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23util/ifdtool: Fix printing or setting PCH strapsArthur Heymans
When printing or setting the PCH straps use the PSL directly instead of multiplying it by 4. Change-Id: Ia91697fdf0c6d80502e8611b259c444f39c6cd57 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-06-22util/lint: Add coreboot specific dictionary fileMartin Roth
This is a wordlist that I've compiled to use in spellcheckers to ignore all of the coreboot specific terms. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I718519000eaf31786380474eb71b99ca442e3bed Reviewed-on: https://review.coreboot.org/c/coreboot/+/64809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-22util/inteltool: Add an additional Device ID for Intel HD 4400 GPUArashk Mahshidfar
Add 0x0A16 as a Device ID for Intel HD 4400 Change-Id: I0129376c0ce005c1bfabaa9dbd8d8dfc6c92e5d3 Signed-off-by: Arashk Mahshidfar <arashkmahshidfar@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-06-19util/cbfstool: Set `USE_FLASHROM=0` to build vbootAngel Pons
cbfstool does not need to build vboot with flashrom support. TEST=./util/abuild/abuild -a --timeless -y -c $(nproc) -Z -t hp/280_g2 no longer fails due to missing libflashrom.h header. Change-Id: I57edcb1b67baa4c458874b11e9ca0238b4419c46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-16util/cbfstool/common.c: Deduplicate buffer_create() logicEdward O'Callaghan
BUG=b:207808292,b:231152447 TEST=builds with vboot_ref uprev. Change-Id: Id7d9b6f5254b08720eebb37151e12ee68ed7f8d7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65145 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-16util/cbfstool: Decouple elogtool from vboot_ref flashrom codeEdward O'Callaghan
Currently elogtool sub-proccesses flashrom as calling libflashrom requires a missing function from the previous flashrom release. Pending a new release of flashrom we must continue to use subprocess. However the current subprocess wrapper implementation lives in vboot_reference which is a git sub-module of coreboot. This causes all sorts of grief keeping a subprocess ABI stable from vboot_reference when the rest of vboot_reference builds of HEAD of the flashrom tree (i.e., using unreleased libflashrom functions). In order to not keep finding ourseleves in a bind between the two separately moving trees with different build environments, decouple elogtool with its own mini copy of flashrom subprocess wrapping logic. Squash in, util/cbfstool/elogtool.c: Convert args into struct in flashrom helper vboot signatures for flashrom r/w helpers changed in the upstream commit bd2971326ee94fc5. Reflect the change here to allow vboot ref and coreboot to realign. BUG=b:207808292,b:231152447 TEST=builds with vboot_ref uprev. Change-Id: I04925e4d9a44b52e4a6fb6f9cec332cab2c7c725 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-14util/mb/google: add support for nissaShou-Chieh Hsu
Add the file template for creating a new variant of Nissa. BUG=b:229550821 Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com> Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-13util/liveiso: Update to NixOS 22.05Felix Singer
Update configs for NixOS 22.05. pulseaudio-modules-bt has been abandoned, and is superseded by pulseaudio's native Bluetooth functionality. Thus, remove it. Change-Id: Ic3b1dbc3c2ab092b576ba2151c93c74d4f298efc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-10crossgcc/gnat.patch: Add additional gnatlib object filesNico Huber
Newer host versions of gnatbind miss these when building the cross gnat1 and gnatbind. Tested with the following host compilers with and without bootstrapping that the resulting coreboot images of three boards stay the same: * GCC 4.9.2 (Debian) * GCC 6.3 (Debian) * GCC 7.4 (Debian) * GCC 8.3 (Debian) * GCC 9.4 (Debian) * GCC 10.2 (Debian) * GCC 12.1 (ArchLinux) Change-Id: I09c6b3cc7b15f1c505acd3ec2c1959b101d6dfb7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65000 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10crossgcc/gnat.patch: Never treat warnings as errorsNico Huber
We used to disable individual warnings that are expected when building our GCC version with a newer one. Not all warnings can be disabled indvidually, though, and it's much easier to simply allow warnings. As a plus, we get the warnings in the log (in case anybody would ever look into it). Partially fixes building with host GCC 12.1. Change-Id: I8fafec4fc49db73b6dba311c775eea2cc92a9b48 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-07util/util_readme: update to give additional informationMartin Roth
Add a note to the top of the util.md document saying not to edit it. The Documentation/util.md file had been updated to contain additional information at the bottom. This copies that information into the file after it's been created. Change-Id: I4b08439420ceb706df62e3949406585ea34c1514 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07util, Documentation: Run util_readme.sh to regen util.mdMartin Roth
Change-Id: Ie14204d0637bb5081e2fae4a9a0e2590bf7abeeb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07cbfstool: Expand CBFS verification validity checkJulius Werner
This patch adds a new line to `cbfstool print -v` output that records the overall CBFS verification health of the image. While this info was already visible from individual fields before, it's nice to have a one-stop location to see "this is a good image" without having to carefully parse a lot of output manually. Also add a few lines to the Makefile that check whether this field is valid for the final image (it always should be, but hopefully this check will allow us to catch regressions like the one fixed by CB:64547 sooner in the future). BUG=b:233263447 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-03inteltool/gpio_names/tigerlake.h: Fix HVMOS pad countMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I344fd2db9d53ad5e82240aaa2b766ac0d8a2045d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64464 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-03util/scripts/cross-repo-cherrypick: Modify output formatPatrick Georgi
As far as I know the Chromium OS team is the only user of this script, so align its output with that of other tools used there: - Replace "Original-Commit-Id" with "GitOrigin-RevId" - Reuse Change-Id instead of moving it to the Original- prefix, which leads to the creation of a new Change ID. Change-Id: I8c39c512901c83a64f00aa48a539e6621f827242 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-03util/release/build-release: Use short git hash for .coreboot-versionMartin Roth
Builds were suddenly failing when the release was done, because the coreboot version was overflowing a 64 character limit. We don't need or use the full hash in other places, so limit the hash to just what's needed to identify the commit. Change-Id: I57c535ca251792cae2c9a9c951e6b44bb61e4e78 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-01cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verificationJulius Werner
The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier among CBFS files because it gets manipulated by a separate utility (ifittool) after cbfstool has already added it to the image. This will break file hashes created for CBFS verification. This is not actually a problem when booting, since coreboot never actually loads the FIT from CBFS -- instead, it's only in the image for use by platform-specific mechanisms that run before coreboot's bootblock. But having an invalid file hash in the CBFS image is confusing when you want to verify that the image is correctly built for verification. This patch adds a new CBFS file type "intel_fit" which is only used for the intel_fit (and intel_fit_ts, if applicable) file containing the FIT. cbfstool will avoid generating and verifying file hashes for this type, like it already does for the "bootblock" and "cbfs header" types. (Note that this means that any attempt to use the CBFS API to actually access this file from coreboot will result in a verification error when CBFS verification is enabled.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOADJulius Werner
There are too many "FIT" in firmware land. In order to reduce possible confusion of CBFS_TYPE_FIT with the Intel Firmware Interface Table, this patch renames it to CBFS_TYPE_FIT_PAYLOAD (including the cbfstool argument, so calling scripts will now need to replace `-t fit` with `-t fit_payload`). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-31util/docker: Update dockerfilesMartin Roth
- Remove deprecated "MAINTAINER" lines - Add Sphinx tools to coreboot-jenkins-node to check documentation. - Add mdl to check markdown - Alphabetize packages in docs Dockerfile - Add jinja2 version 3.0.3 to the docs Dockerfile - The latest version breaks with the error: "exception: cannot import name 'contextfunction' from 'jinja2'" Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia1de62621a6aef4ecd055a1a3afbebad34448002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30util: Update description filesMartin Roth
- Spelling fix - Add languages - Update formatting - Move notes that shouldn't be in the description file to a README Change-Id: I4af37327d5834f8546a3f967585658fb5686f17a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-30util: Fix a few spelling mistakesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib6f0232292c9e289ee1e87998493ea70beea8e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30Documentation: Move intelp2m from description.md to DocumentionMartin Roth
The description.md file for the intelp2m utility wasn't the description that was needed - just a subject, and what language it was written in. It was instead a set of more full documentation, so move it into the Documentation directory and create a new description file. Change-Id: Ia180ae41f91f8b8eb408351a9e44e899edc031d3 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-29util/lint/checkpatch: Add alloc functions to alloc with multiplies checkElyes Haouas
This reduce difference with linux v5.18. Change-Id: Id9412f7b6c0b9f76b39a094142aaded5c2aa1059 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29util/lint/checkpatch: Update 'Check for compiler attributes'Elyes Haouas
This reduce difference with linux v5.18. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I817630321587dec515cd94aa7b73a17819526190 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29util/lint/checkpatch.pl: Use 'allocFunctions'Elyes Haouas
This reduce difference with linux v5.18. Change-Id: I1fc71b9cb6a4e4f8b27fbe6d45f4fa4e2c236157 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28util/inteltool: Add support for Alder Lake chips detection and GPIOsMichał Kopeć
Add PCI IDs for Alder Lake H devices and their GPIO tables. PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362). TEST=dump GPIOs on i5-12600K with Z690 chipset Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-28abuild: Build with clang only when supportedArthur Heymans
This changes the behavior of '-L/--clang' to only buildtest when a target has ARCH_SUPPORTS_CLANG set. Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28util/lint/checkpatch: Warn on period at the end of commit subjectMartin Roth
This gives a warning when there's a period at the end of the commit subject line. Change-Id: If95bef3ba01e0ac13ce18045928081040abef4fd Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-28util/lint: Subtract the patch format string from subject lengthMartin Roth
Checkpatch was looking for a 65 character length, but format-patch adds the text "Subject: [PATCH] " before the actual subject. Checkpatch needs to account for that when looking at the line length. Lines 2863 & 2864 have their indentation fixed as well. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-28util/lint: Add commit message parsing to checkpatch_json scriptMartin Roth
The commit message wasn't being parsed because there's no filename associated with it in the patch output. This change adds the "filename" for the commit message in Gerrit for any errors that have a line number but no filename. calculations is intentionally misspelled as cacluations as a test. Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-25util/intelp2m: Add support for Alder Lake macro generationMichał Kopeć
Add support for Alder Lake as a separate parsing profile, copying the existing 'Cannon' profile and adjusting for differences in reset mapping and GPIO macro generation. TEST=Generate GPIO macros for MSI PRO Z690-A Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-05-24util/lint/checkpatch.pl: Reduce difference with linux v5.18Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16Allow trailing whitespaces in .md filesMaximilian Brune
Two trailing whitesspaces have an actual meaning in Markdown files (a new line). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16util/testing: Remove amdfwread from makefileRobert Zieba
amdfwread was added to the testing makefile but ended up not becoming a separate tool. This commit removes it from the makefile so that `make distclean` works again. Fixes: 29bc79fddb62c30caa33474ac773ae6a6ec1c4f0 ("util/amdfwtool: Add amdfwread utility") TEST=Ran `make distclean` Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I2c8b920bc69d6c20558a28515c52a1e9cecebe27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64348 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16util/inteltool: Add support for Gemini LakeSean Rhodes
Tested on: * StarLite Mk III (N5000) * StarLite Mk IV (N5030) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16util/lint/lint-stable-019: Update grep '\s' to [[:blank:]]Martin Roth
For some reason, the '\s' syntax is causing an error for me under freebsd. It's entirely possible that I'm doing something wrong, but this change should be fine regardless. Freebsd's grep, GNU grep, and git grep all handle posix regex classes, so this change should be transparent. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I489ec13b4ea2e9c17692888e42b8741763b1a2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16util/lint/checkpatch.pl: Fix "uninitialized value" error messageElyes Haouas
Change-Id: I74807f240779060158c6769f63a6e9438a6e5fbe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16util/lint/checkpatch.pl: Fix "Invalid color mode" error messageElyes Haouas
Remove duplicated code: "if ($color =~ /^[01]$/) { $color = !$color; } elsif ($color =~ /^always$/i) { $color = 1; } elsif ($color =~ /^never$/i) { $color = 0; } elsif ($color =~ /^auto$/i) { $color = (-t STDOUT); } else { die "$P: Invalid color mode: $color\n"; }" Change-Id: I5713c364edea806e58df26c3a37b4bba7603ed0a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-13util/amdfwtool: Add amdfwread utilityRobert Zieba
Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-13xcompile,clang: increase the number of bracket-depth for CPPArthur Heymans
Clang has a limit for the number of nested brackets in CPP. For soc/intel/common/block/include/intelblocks this is a problem as it largely exceeds the default limit of 256. Change-Id: I93038f918e07f735394fc495a8ed7371cc5b1569 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-05util/amdfwtool: Add IKEK key for Trusted ApplicationKarthikeyan Ramasubramanian
This binary file is required for use by Trusted Applications that execute in PSP. BUG=b:229947314 TEST=Build and boot to OS in Skyrim. Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-05cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATIONYu-Ping Wu
MediaTek's bootROM expects a SHA256 of the bootblock data at the end of bootblock.bin (see util/mtkheader/gen-bl-img.py). To support CBFS verification (CONFIG_CBFS_VERIFICATION) on MediaTek platforms, we need to re-generate the hash whenever a file is added to or removed from CBFS. BUG=b:229670703 TEST=sudo emerge coreboot-utils TEST=emerge-corsola coreboot chromeos-bootimage TEST=Kingler booted with CONFIG_CBFS_VERIFICATION=y Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63925 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-04util/scripts: Add options to update_submodulesMartin Roth
This extends and adds various options to the update_submodules script. Extensions: - Add help text - Add all options, but specifically allow a single repo to be specified, along with a minimum number of changes instead of being fixed at 10. - Make it a more formal script with main() and functions - Show changes in commit message, unless there are > 65 commits. Options: -c | --changes <#> Specify the minimum number of changes to update a repo -h | --help Print usage and exit -R | --repo <dir> Specify a single repo directory to update -s | --skipsync Assume that repos are already synced -V | --version Print the version and exit This does not fix style issues in the original, which will be fixed in a follow-on commit. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-02utils/cbfstool: Disable Wstrict-prototypes warningManoj Gupta
As recommended on crrev.com/c/3612466 lz4 code is not supposed to be modified. Since both gcc and clang complain about functions without explicit void in argument with Wstrict-prototypes, just disable it instead instead of enabling. BUG=b:230345382 TEST=llvm tot test BRANCH=none Signed-off-by: Manoj Gupta <manojgupta@google.com> Change-Id: I9f3ae01821447f43b4082598dd618d9f8325dca2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63936 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27util/cbmem: fix an unused parameter issue in timestamp_getNick Vaccaro
Fix an unused parameter error when building on devices where __i386__ and __x86_64__ are not defined. BUG=none TEST=none Change-Id: I6c04c8e7b931565c87d358aac1025ebcb7617b13 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63880 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-25amdfwtool: Use command line option use-combo to decide if use comboZheng Bao
The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25amdfwtool: Change the name of macros for 'BHD'Zheng Bao
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-25cpu/x86/64bit: Generate static page tables from an assembly fileArthur Heymans
This removes the need for a tool to generate simple identity pages. Future patches will link this page table directly into the stages on some platforms so having an assembly file makes a lot of sense. This also optimizes the size of the page of each 4K page by placing the PDPE_table below the PDE. Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-24util/lint/checkpatch.pl: Update lines related to CONST_STRUCTElyes Haouas
Update to v5.18-2 version. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0fe2ec6a74a4b8c70452fbf05d534a37e1ea2c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 00:10:34 +0000