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2022-11-21util/testing: Update ABUILD_OPTIONS with long option namesMartin Roth
It's hard to tell what is what with the short option names, so use the long options here. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1371e098bba1077dedfaffa56287a28656197b40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-abuild target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-abuild target, make test-abuild from what-jenkins-does. The test-abuild target had not been updated to use the ABUILD_OPTIONS variable, so update it with the commands from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Call test-lint target from what-jenkins-doesMartin Roth
Instead of having duplicate lines in the what-jenkins-does target and the test-lint target, make test-lint with the --junit argument from what-jenkins-does. Now there's only one place to update when changing the call. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/testing: Unify cleanup in all targetsMartin Roth
Instead of having the what-jenkins-does target clean up before building, have it call the test_cleanup target. Clean the tegra targets. Remove distclean from test_cleanup target - I don't think that's expected, and people might be upset by having their .config deleted. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21util/abuild: check for PASSED_BOARDS before trying to show itMartin Roth
If no boards are tested by abuild, an error is currently shown because no boards failed, but no boards passed either. Account for this possibility. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-20util/kconfig: Add patch to move Kconfig deps to build/configMartin Roth
The change being reverted [1] caused all the Kconfig dependency files to be generated at the top level of coreboot's build directory. This reverts that behavior and puts the dependencies back where we're used to them being. [1] https://web.archive.org/web/20220316120807/https://github.com/torvalds/linux/commit/1b9e740a81f91ae338b29ed70455719804957b80 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic4b48831705c3206e7c2e09f01d072d1cde9c9c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69535 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17util/kconfig: Move Kconfig deps back into build/configMartin Roth
revert commit 1b9e740a8 (kconfig: fix failing to generate auto.conf) [1] The above change caused all of the enabled kconfig options to be written into the top level build directory. We don't want that, so go back to the old behavior for the coreboot tree. [1] https://web.archive.org/web/20220316120807/https://github.com/torvalds/linux/commit/1b9e740a81f91ae338b29ed70455719804957b80 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2904f69a5d85337ad0a6b48590ccd4b4a6e38b70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-16util/testing: Move check of intel-sec-tool to separate targetMartin Roth
Testing for the presence of intel-sec-tools doesn't need to happen inside the what-jenkins-does target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6faa5bd5292ac5cceba9a64fe81939c0e25b9f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-15testing/Makefile.inc: Fix removing clang buildsArthur Heymans
The directory names were wrong. Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69568 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13util/superiotool: Add SMSC MEC5035Nicholas Chin
Also comment out the SMSC FDC37M602 which has a conflicting ID and has never had the LDN/register layout anyway. Tested on a Dell Latitude E6400 Change-Id: I5b1900e6ef599c422a1d6eca7a2ac4691d56d874 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69481 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13util/superiotool: Add Nuvoton NCT6685D/NCT6686DNicholas Chin
There doesn't seem to be a datasheet available for the NCT6685D, but there is one for the NCT6686D. The 85D seems to return the same ID as the 86D, and the registers do seem to be returning valid data other than LDN 0xf which returns all 1s. The LDN and register layout appears to be identical to the NCT6687D-W. Tested on a Lenovo ThinkCentre M900 with a NCT6685D. Change-Id: I4de0e7b86422a14ab9ccb15b7571597611d755d5 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13util/xcompile: Fix building for clang + 64bitArthur Heymans
-malign-abi does not exist on clang (v15.0.0) and the -ccc-gcc-name variable is not needed anymore. TESTED: This also boots on qemu q35 Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12util/testing: Buildtest with clangArthur Heymans
Some platforms correctly build and boot with clang. Add this to our CI. Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12amdfwtool: Add definition of instance for PSP entryZheng Bao
Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12treewide: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarityElyes Haouas
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12util/amdfwtool/amdfwtool: Don't rewrite macrosElyes Haouas
Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-11util/amdfwtool: Add more instances some types in BDTArthur Heymans
Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11util/amdfwtool: Add new typesArthur Heymans
These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-11-10util/inteltool: Add support for Elkhart lakeKacper Stojek
Document: 614109, 601458 Tested on: Protectli vault_ehl (VP2420) Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Change-Id: I54948741082ca1072642046f64539a4c15ddb578 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-10util/scripts: Add script to run abuild on specific SOCsMartin Roth
This finds all the boards using a specified Kconfig option and runs both CrOS and non-CrOS abuilds on them to make sure they're working. Nobody wants to run the full what-jenkins-does build on their host machine. Hopefully this can help get some tests run locally before pushing to coreboot.org. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-09cbfstool: Fix possible memory leakShaik Shahina
Handle the possible memory leak scenario. Foundby=klocwork BUG=NONE TEST=Boot to OS on Nivviks Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e Signed-off-by: Shaik Shahina <shahina.shaik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69220 Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-08util/cbfstool/bpdt_formats: Fix memory leak issuesSolomon Alan-Dei
The functions create_bpdt_hdr and create_cse_layout in bpdt_1_6.c are defined to return pointers but not integers as was previouly implemented. Reported-by: Coverity(CID:1469323) Reported-by: Coverity(CID:1469353) Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com> Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-07util/superiotool/fintek.c: Fix F71808A hardware monitor readoutsRavi Mistry
Fix readouts from the hardware monitor on Fintek F71808A Super I/O. The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61. Referred to util/superiotool/winbond.c and the Linux kernel driver f71882fg. Tested on a HP 500-319na (Memphis-S / IPM87-MP). Signed-off-by: Ravi Mistry <rvstry@protonmail.com> Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07util/scripts: Add script to show platforms, CPU, type, and date addedMartin Roth
This is the script used to generate the list of platforms that were removed from the master branch at each release. Generate a list for the old branch, another for the new, and compare the two. Representative output: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | | amd/bilby | AMD_PICASSO | 2021-02-17 | eval | | amd/birman | AMD_MORGANA | 2022-10-10 | eval | | system76/whl-u | INTEL_WHISKEYLAKE | 2021-04-14 | laptop | | ti/beaglebone | TI_AM335X | 2013-05-26 | sbc | | up/squared | INTEL_APOLLOLAKE | 2019-05-22 | mini | +-------------------------+-------------------+------------+----------+ ``` Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4f7265d95df31f3a74aa2aa164f6a094c1139750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04util/cbmem: Update formatting for cbmem -l commandMartin Roth
Some of the cbmem area names have gotten longer, and were making the output of cbmem -l look bad, so expand the name area to 20 characters. Instead of printing a blank area if the name isn't recognized, call it unknown. Change the method of printing the title to match the way the actual text of the table is printed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04checkpatch: add Co-authored-by to signature listMichael Niewöhner
Co-authored-by is commonly used for changes that have more than one author. Add it to the list to make Jenkins happy. Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-11-03util/docker/coreboot.org-status: Rewrite parserPatrick Georgi
The current tool is a shell script that mixes data collection and HTML generation and is generally a pain to work with. It takes 15 minutes to run. The new tool is written in go, collects all data first, then generates the output HTML from the data and a single template, and finishes in 10 seconds. The goal in this version is to produce output as similar as possible to the output of the shell script. Some difference will remain because the shell script returns some trash data whose reproduction would require more effort than is worth. Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-11-02util/eventlog: Correct the capitalization for diagnostics typesHsuan Ting Chen
Correct the capitalization of ELOG_CROS_DIAG_TYPE_STORAGE_HEALTH from "Storage Health Info" to "Storage health info", which is already widely used in depthcharge diagnostics tools. BUG=b:254405481 TEST=none Change-Id: Ia6c1df9e8d2ee6f8ae11b962e76b52f3c6663c42 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02util/cbfstool: fix memory leak in compress.cSolomon Alan-Dei
free the memory allocated in lz4_compress function before returning from it. Reported-by: Coverity (CID:1469433) Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com> Change-Id: I8698090d519964348e51fc3b6f2023d06d81fcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-02util/release/build-release: Use bash arrays for paramsMartin Roth
Instead of using unquoted strings for the command line parameters, use arrays which naturally split into separate elements inside the quotes. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1c96d5072b98523af4e407cfff8f4d1d28ec3297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-30util/kconfig: Uprev to Linux 6.0's kconfigPatrick Georgi
Only minor changes in kconfig this time that shouldn't affect us. TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: I77cc8517128a973c345c41da2c483b78eeaee89f Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.19's kconfigPatrick Georgi
Only minor changes in kconfig this time that shouldn't affect us. TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: Icc83c929dd1ea2d98e1a789560ce26886ded1f12 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.18's kconfigPatrick Georgi
Only minor changes in kconfig this time that shouldn't affect us. TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: I46f43182ce9ec1b6a5923cb77dcd6e335e44c87a Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.17's kconfigPatrick Georgi
Another upstream refactoring, another local patch gone! TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains the same Change-Id: I0f99dcbd8ecc7256551f0a6e2c83c060cb1999b6 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30util/kconfig: Uprev to Linux 5.16's kconfigPatrick Georgi
Linux 5.16 saw a significant rewrite in the boolean handling which reduces our change set. On the other hand, it's all new code. Comparing the config.build and config.h files generated by `util/abuild/abuild -C`, only a few lines of comment in the header changed. Change-Id: I52984e15a48236ddf228707aec85e90f71aa4382 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-29util/lint: fall back to regular grep in kconfig_lintSolomon Alan-Dei
Automatically fall back to using regular grep if working outside a git repository and the option to use regular grep is not specified Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com> Change-Id: I0cdecf01a0e74c30947c4fe7e7c7d9457a5165a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-29util/chromeos/extract_blobs: try using RW_MAIN_A region firstMatt DeVillier
Since the RW firmware may contain newer/additional blobs than the RO COREBOOT region, try using it first, then fall back to COREBOOT and eventually BOOT_STUB if necessary. TEST=extract blobs from dedede and brya firmware images Change-Id: Ia01b37f8c410685de8a17ea4105ca671931a47c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-28lint/checkpatch: consider leading + in the line length limit checkMichael Niewöhner
The line length limit in coreboot's coding style guidelines applies to the final file, while checkpatch currently checks the patch line length. Since patches´ lines start with a `+` (only added content is checked), the line length being checked is one character longer than the actual content. Increase max_line_length by 1 to take this into account. Change-Id: I8da45bb0d5fbe7d0e12c8b181cf01e5685186bf6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-26util/cbfstool: Check for metadata hash in verstageKarthikeyan Ramasubramanian
Metadata Hash is usually present inside the first segment of BIOS. On board where vboot starts in bootblock, it is present in bootblock. On boards where vboot starts before bootblock, it is present in file containing verstage. Update cbfstool to check for metadata hash in file containing verstage besides bootblock. Add a new CBFS file type for the concerned file and exclude it from CBFS verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 and PSP verstages. Change-Id: Ib4dfba6a9cdbda0ef367b812f671c90e5f90caf8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66942 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool: Add build rules for amdfwreadKarthikeyan Ramasubramanian
Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: List AMDFW RO binary entriesKarthikeyan Ramasubramanian
Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories and list the entries present in them. Accommodate both recovery A/B layout and normal layout. This is required to identify the location and size of each entries in the finally built amdfw.rom. This in turn can be used to perform any platform specific verification on the relevant components. BUG=None TEST=Build and list the contents of AMDFW binary. /usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin Table: FW Offset Size PSPL1: Dir 0x00d97000 +-->PSPL1: 0x48 0x00d98000 0x00001000 +-->PSPL2: Dir 0x00c30000 +-->PSPL2: 0x00 0x00c31000 0x00000440 +-->PSPL2: 0x01 0x00c31500 0x00007580 +-->PSPL2: 0x02 0x00c38b00 0x00019470 +-->PSPL2: 0x08 0x00c52000 0x0001f560 +-->PSPL2: 0x09 0x00c71600 0x00000440 +-->PSPL2: 0x0b 0x430000041(Soft-fuse) +-->PSPL2: 0x0c 0x00c71b00 0x00023100 +-->PSPL2: 0x12 0x00c94c00 0x00015890 +-->PSPL2: 0x13 0x00caa500 0x000021c0 +-->PSPL2: 0x20 0x00cac700 0x00000640 +-->PSPL2: 0x21 0x00cace00 0x00000030 +-->PSPL2: 0x22 0x00cad000 0x00001000 +-->PSPL2: 0x24 0x00cae000 0x00003b60 +-->PSPL2: 0x28 0x00cb1c00 0x00022890 +-->PSPL2: 0x2d 0x00cd4500 0x00003100 +-->PSPL2: 0x30 0x00cd7600 0x0006b550 +-->PSPL2: 0x3a 0x00d42c00 0x000006d0 +-->PSPL2: 0x3c 0x00d43300 0x000018c0 +-->PSPL2: 0x44 0x00d44c00 0x00006610 +-->PSPL2: 0x45 0x00d4b300 0x00001c70 +-->PSPL2: 0x50 0x00d4d000 0x00001a00 +-->PSPL2: 0x51 0x00d4ea00 0x00001020 +-->PSPL2: 0x52 0x00d4fb00 0x00010180 +-->PSPL2: 0x55 0x00d5fd00 0x00000600 +-->PSPL2: 0x5a 0x00d60300 0x00000570 +-->PSPL2: 0x5c 0x00d60900 0x00000b20 +-->PSPL2: 0x71 0x00d61500 0x00024710 +-->PSPL2: 0x73 0x00d85d00 0x00010640 +-->PSPL2: 0x8d 0x00d96400 0x00000030 +-->PSPL2: 0x49 0x00d99000 0x00001000 +-->BIOSL2: Dir 0x00d99000 +-->BIOSL2: 0x60 0x00d9a000 0x00009924 +-->BIOSL2: 0x68 0x00da4000 0x00009924 +-->BIOSL2: 0x61 0x2001000(DRAM-Address) +-->BIOSL2: 0x62 0x00dada00 0x00010000 +-->BIOSL2: 0x63 0x00000000 0x0001e000 +-->BIOSL2: 0x64 0x00db4200 0x00006310 +-->BIOSL2: 0x65 0x00dba600 0x000004e0 +-->BIOSL2: 0x64 0x00dbab00 0x00006180 +-->BIOSL2: 0x65 0x00dc0d00 0x00000250 +-->BIOSL2: 0x6b 0x201f000(DRAM-Address) +-->PSPL1: 0x4a 0x00d98000 0x00001000 Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Handle recovery A/B layoutKarthikeyan Ramasubramanian
Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to handle it. Also add a generic read_header function to read different header types. BUG=None TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to dump the Softfuse entry. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit maskKarthikeyan Ramasubramanian
Optional arguments that involve printing information from the firmware image is mapped to bit fields with bit 31 set. But instead of just setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Update relative_offset functionKarthikeyan Ramasubramanian
* AMD_ADDR_PHYSICAL refers to physical address in the memory map * AMD_ADDR_REL_BIOS is relative to the start of the BIOS image * AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS tables Update the relative_offset implementation accordingly. Though AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify the relative_offset implementation so that it can be used for both PSP and BIOS firmware tables. Hence update the relative_offset function signature as well. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-24util/superiotool/nuvoton.c: fix NCT6687D PP LDN typoMichał Żygowski
Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the patch adding register definitions for NCT6687D Super I/O chip. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-23scripts/update_submodules: Fix "bad revision" errorElyes Haouas
Fix "bad revision" error when we run "update_submodules" with no option. This adds "origin/trunk" branch name for "util/goswid". Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-21util/amdfwutil: Fix adding microcode binariesArthur Heymans
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21util/lint: Fix linting outside of git reposMartin Roth
If the coreboot code is not in a git repository, the linters switch from using `git ls-files` to find. This requires some changes to prevent the linters from looking at the wrong files which are automatically excluded by git. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-14util/elogtool: Add support for parsing CrOS diagnostics logHsuan Ting Chen
Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it. The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains: * An uint8_t of subtype code * Any number of "ChromeOS diagnostics logs" events Each "ChromeOS diagnostics log" represents the result of one ChromeOS diagnostics test run. It is stored within an uint8_t raw[3]: * [23:19] = ELOG_CROS_DIAG_TYPE_* * [18:16] = ELOG_CROS_DIAG_RESULT_* * [15:0] = Running time in seconds Also add support for parsing this event. The parser will first calculate the number of runs it contains, and try to parse the result one by one. BUG=b:226551117 TEST=Build and boot google/tomato to OS, localhost ~ # elogtool list 0 | 2022-09-26 04:25:32 | Log area cleared | 186 1 | 2022-09-26 04:25:50 | System boot | 0 2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery | recovery_reason=0x2/0 (Recovery button pressed) | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery 4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success 5 | 2022-09-26 04:26:06 | System boot | 0 6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs | type=Memory check (quick), result=Aborted, time=0m0s | type=Memory check (full), result=Aborted, time=0m0s | type=Storage self-test (extended), result=Aborted, time=0m1s Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-13util/cbfstool: Wrap logging macros in do - whileFred Reitberger
Wrap the console logging macros with do { ... } while (0) so they act more like functions. Add missing semicolons to calls of these macros. TEST=compile only Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I721a4a93636201fa2394ec62cbe4e743cd3ad9d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-12util/superiotool/nuvoton.c: Add NCT6687D-W register definitionsMichał Żygowski
Based on public NCT6686D hardware datasheet revision 0.5 which should be similar to NCT6687D. TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-11util/amdfwread: Fix cookie error messageArthur Heymans
Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-11util/amdfwutil: Order enum and use hex consistentlyArthur Heymans
This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-10-10util/amdfwtool: Add Mendocino to usageFred Reitberger
Add missing Mendocino soc to usage print. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10util/amdfwtool: Add preliminary code for morgana & glinda SOCsMartin Roth
This allows amdfwtool to recognize the names for the upcoming morgana and glinda SoCs. It does not yet do anything for those SoCs, but this allows the morgana SoC to build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10util/lint/lint-stable-003-whitespace: Fix shell variable nameFred Reitberger
Fix shell variable "LINTDIR" so that helper_functions.sh can be found. TEST=`./util/lint/lint lint-stable --junit` no longer prints "cannot open /helper_functions.sh: No such file" Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-08util/inteltool: Add support for (non-ULT) BroadwellAngel Pons
Add support for traditional (non-ULT) Broadwell. Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08util/inteltool: Add 9 series PCH supportAngel Pons
Add the PCI device IDs for 9 series PCHs. Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-07util/coreboot-configurator: Update the READMESean Rhodes
Update the README with new instructions for Debian 11 and MX Linux. Also add the build dependencies. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-07util/inteltool: Add support for Alderlake P in inteltoolKacper Stojek
TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P Document number: 626817, 630094, 655258 Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Generate hashes for signed AMDFW componentsKangheui Won
Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Add options to separate signed firmwaresKangheui Won
Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Include the header with __packed definitionKarthikeyan Ramasubramanian
Checkpatch script recommends to use __packed instead of __attribute__((packed)). Currently the build rule for amdfwtool does not include the required header file with __packed definition. Update the compiler flag to include the required header file. BUG=None TEST=Build amdfwtool. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/docker/coreboot-sdk: add graphicsmagick-imagemagick-compatTom Hiller
edkII requires ImageMagick's `convert` to compile. The `graphicsmagick-imagemagick-compat` package provides `convert` without the full ImageMagick library. Change-Id: I8fc01526842eb408b0015c0652043c20f826a015 Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-09-30util/lint: Update tools that use git to use a libraryMartin Roth
Each of the tools that used git had similar functionality. This combines all of that into a single script that gets sourced by each. This makes maintenance much easier. By doing this and updating each of the scripts to do the correct thing if the script isn't being run in a git repository, it makes them work much better for the releases, which are just released as a tarball, without any attached git repository. Change-Id: I61ba1cc4f7205e0d4baf993588bbc774120405cb Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30util/lint: Update spelling.txt, add makefile to sort itMartin Roth
- Update spelling.txt with Lintian changes - Remove words that are going to mess up code - Add comments to the header about what words should be removed, along with where the files - Add Makefile to sort the list Note that this undoes some of the sorting that Patrick introduced in commit CB:38632 - ID: 805b291830 I just cannot reproduce his sort order, even using the script he put into the commit message. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic131d5b08409f43eb700dcc8f125af00cff53d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64893 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30util/amdfwtool/data_parse: fix PMU subprogram/instance ID handlingFelix Held
The parsing of the PMU binary subprogram and instance numbers only worked correctly for the cases where the ID in the name in the fw.cfg file was between 0 and 9, but returned wrong results if it was between a and f. Switch to using strtol with a base of 16 instead of subtracting the char '0' from the char in the filename in find_register_fw_filename_bios_dir to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-29util/spd_tools: Change Mendocino to use 0x13 for LP5x memory typeRobert Zieba
Mendocino supports LP5x but currently doesn't support SPDs that use the LP5x memory type, 0x15. This commit updates set 1 SPDs, which are currently only used for mendocino, to use 0x13 for their memory type. BUG=b:245509394 TEST=Generated SPDs, verified that only set 1 have changed to 0x13 Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-28intelmetool: Add PCI ID for Bay TrailDenis 'GNUtoo' Carikli
Tested on a Dell Venue 8 Pro tablet Change-Id: Ic8f162ea82b910082af4b4e05fa1408fd24f2c88 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-22util/amdfwtool: Add support for PSP NVRAM base addr and sizeRitul Guru
Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22util/coreboot-configurator: Update legacy_8254_timer descriptionSean Rhodes
The help text and label for legacy_8254_timer is inverted, so update this so that it is correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I866a15886d1cfd2b77094742787dee7a36a54e85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65348 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22util/coreboot-configurator: Add RPM spec fileSean Rhodes
Add RPM spec to allow building RPMs, for both coreboot-configurator and nvramtool, for Fedora. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I80a77d0f2246409c06e22abb229d63c4611a9fb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65346 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22util/coreboot-configurator: Update Debian dependanciesSean Rhodes
Change the control file to allow either libyaml-cpp0.6 or libyaml-cpp0.7. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I754d3e2018ab78fcb657d313c8662313738b190a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-21tests: Add support for tests build failures detectionJakub Czapiga
This patch introduces new target: junit.xml-unit-tests, which builds and runs unit-tests. It also creates build log containing build logs. This feature allows for one to see build failures in Jenkins dashboard. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67372 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0Elyes Haouas
Test build for QEMU x86 i440fx/piix4. Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18crossgcc: Upgrade cmake from 3.23.2 to 3.24.2Elyes Haouas
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-18cbmem: use aligned_memcpy for reading lb_cbmem_entry informationYidi Lin
The lbtable contains the memory entries that have fields unnaturally aligned in memory. Therefore, we need to perform an aligned_memcpy() to fix the issues with platforms that don't allow unaligned accesses. BUG=b:246887035 TEST=cbmem -l; cbmem -r ${CBMEM ID} Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-17riscv: Enable the newfangled way of selecting instruction setsPatrick Georgi
gcc12+ will require riscv architecture selection to come not only with featurei suffixd charactersa, it also comes with feature_ful suffix_ed words_mith. Much creative, very appreciate. To accommodate for this madness, enable the already existing (but off by default) support for that in our gcc11 build, support using by detecting the compiler's behavior in xcompile and pass that knowledge along to our build system. Then cross our fingers and hope for the best! Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-16util/kconfig/regex.c: Remove leftoverElyes Haouas
coreboot doesn't support the MIPS architecture anymore. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I404d034949a7786d7971117081537baf27ff2e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-16crossgcc [binutils]: Remove 'enable-plugins' optionElyes Haouas
unneeded 'enable-plugins' option sneaked in..., so remove it. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16crossgcc [binutils]: Remove invalid enable-interwork optionElyes Haouas
'enable-interwork' is not a binutils configure option. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-15sconfig: Allow to specify device operationsNico Huber
Currently we only have runtime mechanisms to assign device operations to a node in our devicetree (with one exception: the root device). The most common method is to map PCI IDs to the device operations with a `struct pci_driver`. Another accustomed way is to let a chip driver assign them. For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI ID lists grew very large and are incredibly error-prone. Often, IDs are missing and sometimes IDs are added almost mechanically without checking the code for compatibility. Maintaining these lists in a central place also reduces flexibility. Now, for onboard devices it is actually unnecessary to assign the device operations at runtime. We already know exactly what operations should be assigned. And since we are using chipset devicetrees, we have a perfect place to put that information. This patch adds a simple mechanism to `sconfig`. It allows us to speci- fy operations per device, e.g. device pci 00.0 alias system_agent on ops system_agent_ops end The operations are given as a C identifier. In this example, we simply assume that a global `struct device_operations system_agent_ops` exists. Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15util/ifittool: Error out if microcodes do not fit the FIT tableJeremy Compostella
parse_microcode_blob() returns success when it reaches max_fit_entries microcode. It makes the FIT table size verification in fit_add_microcode_file() useless. This patch makes parse_microcode_blob() error out if max_fit_entries is reached. Note that this size verification is critical as a FIT table only partially listing the microcode patches can lead to boot failures as recently observed on Raptor Lake-P. BRANCH=firmware-brya-14505.B BUG=b:245380705 TEST=compilation errors out when trying to stitch more than CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
2022-09-14util/lint: Add a check for touchpads using the "probed" flagMatt DeVillier
As of commit 2cf52d80a6ec ("mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flag") all touchpads in the tree have been switched from using the 'probed' flag to 'detect.' Add a lint check to ensure no touchpads are added with the probed flag. TEST=manually change one touchpad to use 'probed' flag and ensure lint check catches it. Change-Id: Ie0aee2e3778fc56c6c21c97995738a147a1fa0d4 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67486 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14crossgcc: binutils: Remove invalid enable-multilibs optionElyes Haouas
Looks like somewhere after the original implementation it was renamed to --enable-multilib without the s. 'enable-multilibs' is not a valid option for binutils. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I105cc9fa489aed24905dedb785c70bc69ed18970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65608 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-12intelp2m: Add Go Managing Dependencies System supportMaxim Polyakov
Add go.mod containing the full name of the project according to the docs [1]: review.coreboot.org/coreboot.git/util/intelp2m, and also, based on this, rename the internal packages to point to the absolute path. This will allow Go Managing Dependencies System to integrate packages from intelp2m to third-party Go written on the Go language [1]. This also requires fixing the Golang compiler version in go.mod: use go1.18 [2], the latest up-to-date version. [1] https://web.archive.org/web/20220910100342/https://go.dev/doc/modules/managing-dependencies [2] https://web.archive.org/web/20220910100206/https://tip.golang.org/doc/go1.18 [ TEST ] 1) Import the coreboot project into some go project: $cd path/to/go-project $go get review.coreboot.org/coreboot.git go: downloading review.coreboot.org/coreboot.git v0.0.0-20220903004133 -39914a50ae16 go: added review.coreboot.org/coreboot.git v0.0.0-20220903004133 -39914a50ae16 Thus, 'go get' correctly downloaded the contents of the repository. 2) Import intelp2m: $cd path/to/go-project $go get review.coreboot.org/coreboot.git/util/intelp2m review.coreboot.org/coreboot.git/util/intelp2m imports ./config: "./config" is relative, but relative import paths are not supported in module mode review.coreboot.org/coreboot.git/util/intelp2m imports ./parser: "./parser" is relative, but relative import paths are not supported in module mode Thus, the problem is in the package names, but after this patch, the import should be without errors. 3) Import a repository with an incorrect url: $cd path/to/go-project $go get review.coreboot.org/coreboot/test go: unrecognized import path "review.coreboot.org/coreboot/test": reading https://review.coreboot.org/coreboot/test?go-get=1: 404 Not Found This has not happened in previous cases. Change-Id: I12efae31227129b8c884af10fb233f398c4094e7 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-09-12util/ifittool: Fix buffer overflow with padded microcode patchesJeremy Compostella
Some microcode patches are padded with zeros, which make parse_microcode_blob() read beyond the end of the buffer. BRANCH=firmware-brya-14505.B BUG=b:245380705 TEST=No segmentation fault with a padded microcode patch Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67460 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-07util/lint/lint: Add -I option to invert test resultsMartin Roth
To test the linters, we want to invert the results so that any test that passes shows up as a failure. This will allow us to verify that all of the linters are working correctly. This will be tested nightly as well as on changes to the lint tools. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-07util/spd_tools: Update LP5X support for ADL/RPL/MTLCaveh Jalali
This updates the SPD utility and generated SPDs for LP5X to use memory type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on Intel Tech Advisory Doc ID #616599 dated May 2022, page 15. SPDs were regenerated with: "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5" This only affects the SPDs for 2 memory parts for Intel SoCs and the only board referencing these is rex. BUG=b:242765117 TEST=inspected SPD hex dump Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-06lint/checkpatch: Fix incorrect camelcase detection on numeric constantElyes Haouas
This reduce the difference with linux v6.0-rc3. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I15e1a935665c38b8a2109d412b1d16f935cbb402 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-06util/lint/lint-stable-019-header-files: add testMartin Roth
Add a test to make sure that the linter fails correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06util/lint: Add rules.h & compiler.h to 019-header-files linterMartin Roth
The rules.h & compiler.h includes were removed in previous commits, so add the checks to keep them out to the linter. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-05util/lint: ignore util/goswid, a new submoduleMartin Roth
git submodules should be ignored when parsing the coreboot tree for lint errors. Those should be handled in their own commit checks. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-04util/amdfwtool/amdfwread: Fix incorrect option indexKarthikeyan Ramasubramanian
index I/O argument to getopt_long is not the index to argv. Instead it is an index into the optlong array corresponding to the parsed option. Also getopt() uses a global variable optind to track the index of the next argument to be processed. Use the optindex variable as an index to extract the filename from argv. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04util/spd_tools: Rebuild utils when source changesCaveh Jalali
This adds source file dependencies to utilities so that they are rebuilt when the source is changed. Previously, binaries were only built if they did not already exist and never rebuilt to reflect source file changes. BUG=none TEST=verified binaries are rebuilt when source files are touched. Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-04util/lint: Add lint tests to make sure they fail correctlyMartin Roth
Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-03util/lint/lint: Reformat usageMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I684d374bd02a42e178383c26936e137e173f8f7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-03util/lint/lint: Add command line parsingMartin Roth
The lint script just did very basic argument parsing and required the sub-command and --junit argument to be in specific locations. I'm adding additional commands, so the first step is to add true command line parsing. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7118c29e6c5d785b35a7ae12cf5984c43ebc3ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67191 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02cbfs/vboot: Adapt to new vb2_digest APIJulius Werner
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02util/docker/coreboot-jenkins-node: Install cmockaFelix Singer
flashrom uses cmocka for unit testing. Install it so that the CI can use it. Change-Id: I5c168e480d6f4cbfbbd175ecb035c88bfcbac00b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67272 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>