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2023-08-04coreboot-jenkins-node/Dockerfile: Upgrade lua5 from lua5.3 to lua5.4Elyes Haouas
Change-Id: Ic1450f0fa8eb69273aa907dea2eba8f7e7131ef1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04util/docker/coreboot-sdk: add mrc extraction packagesTom Hiller
Add packages required to extract the `mrc.bin` from a ChromeOS firmware image as per the instructions provided in https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html Change-Id: I81ed4ef55f0ba745a8a0a0cc85c2b00360f59297 Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67160 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04util/docker: refactor out and fix docker cache dir testMartin Roth
The test for the docker cache directory was used by two different targets, so turn it into its own target. Add missing $ for whoami commands. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic5e1d28110097eb502959e81bafe77faa0fc7fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/76707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04util/docker: Update coreboot-sdk-test to coreboot-jenkins-testMartin Roth
The coreboot-jenkins-test docker image takes the coreboot-jenkins-node docker image and runs a series of tests to verify that things build properly. This was original created to test the coreboot-sdk, but build functions like the documentation have been moved from the sdk image into the jenkins node, so the test needs to be renamed. Add the makefile target to the help and phony target list at the same time. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0e6282bbb163064f177c8e68e7180ba2bdc101f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04util/amdfwtool: Introduce support for Hash Table v2Karthikeyan Ramasubramanian
Some stages in bootflow prefer to use 16 bytes UUID instead of traditional 2 bytes FWID to identify the firmware components they verify/validate. Hence add version 2 of hash table which identifies firmware components using UUID. Other than UUID and a reserved field for alignment reasons, the format of the hash table is very similar to hash table v1. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP Verstage enabled. Ensure that the hash table v2 is built and installed into BIOS image for the components that are configured in amdfw.cfg file. Ensure that the validation by PSP is successful for all the relevant components during the boot flow. Change-Id: I2899154086cf8e90c3327178157b07ead034b16e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76586 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04util/amdfwtool: Support multiple firmware identifier typesKarthikeyan Ramasubramanian
Currently this tool generates a hash table to verify signed binaries, with a 2 byte FWID as the only kind of identifier. Going forward some binaries are going to adopt 16 byte UUID identifiers and more binaries will follow in the future SoCs. Hence add support for handling multiple firmware identifier types. While at this remove the unused fwid from the PSP FW table. BUG=b:277292697 TEST=Build BIOS image and boot to OS in Myst & Skyrim. Change-Id: I5180dc0fe812b174b1d40fea9f00a85d6ef00f2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03docker/coreboot-sdk/Dockerfile: Remove old workaroundElyes Haouas
Remove old workaround for automake and aclocal. Change-Id: Ifc00a479fd08d9ee4d97df6da8762bae2d097827 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03util/docker: Remove manual symlink python3 to pythonElyes Haouas
Debian sid symlinks already python3 to python. Change-Id: Ibc3b2b047df7e1066624d4dd8aa9664ab1869222 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03linux_trampoline: Handle 64-bit framebuffer addressesNico Huber
To support full 64-bit addresses, there is a new field `ext_lfb_base` since Linux 4.1. It is unclear, however, how a loader is supposed to know if the kernel is compatible with this. Filling these previously reserved bits doesn't hurt, but an old kernel would probably ignore them and not know that it's handling a clipped, invalid address. So we play safe, and only allow 64-bit addresses for kernels after the 2.15 version bump of the boot protocol. Change-Id: Ib20184cf207f092062a91ac3e6aa819b956efd33 Signed-off-by: Nico Huber <nico.h@gmx.de> Co-authored-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76479 Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03util/abuild: Add per-build statistics tarfileKyösti Mälkki
Change-Id: Icb9a5bdf94013fe493dc8ec634cf3094bcff2838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75803 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-01Revert "util/amdfwtool: Add some PSP entries to both levels"Matt DeVillier
This reverts commit 91f5da477677cc6a7a7d5cdc50f5d2bf71981e44. Commit breaks booting on MDN (and likely others). Boot hangs on: [NOTE ]  MRC: no data in 'RW_MRC_CACHE' Change-Id: Id8042690af2764d6e46fe01287be598091b1a239 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76718 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-01linux_trampoline: Handle coreboot framebufferNico Huber
Translate the coreboot framebuffer info from coreboot tables to the Linux zero page. Tested in QEMU/Q35 with a kernel w/ efifb enabled. Change-Id: I2447b2366df8dd8ffe741c943de544d8b4d02dff Signed-off-by: Nico Huber <nico.h@gmx.de> Co-authored-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76431 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
2023-08-01util: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I6b87680ec9f501945ae266ae4e4927efd2399d56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76815 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31util/sconfig: rework help text printingFelix Held
Drop the program name and split the printf call with multiple lines of text into separate printk calls. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I43df1fd02ce0fdbb6b22e1d4eda45017811c48d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76774 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31util/sconfig: Don't hardcode PCI device domainArthur Heymans
Use the domain number in static references to pci device so that device domain 0x20 on device pci 00.0 on end end results in DEVTREE_CONST struct device *const __pci_32_00_0 = &dev_#something; in static.c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7a98b2325ee08feb1a3d1d4b333f3f4e53934b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-31util/amdfwtool: Add some PSP entries to both levelsArthur Heymans
Some SoC like Genoa require this. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I01ff792e8016b16f34bc69722469b63cae5a42ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/76468 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-07-24amdfwtool: Add early vga BIOS ID to enumArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ife8c166350030cb89d794ac42834d79ec933f278 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-23util/docker: Update libncurses5-dev to libncurses-dev packageMartin Roth
The libncurses5-dev package no longer seems to be available in debian sid. It's been marked as a transitional package, pointing to libncurses-dev (ncurses 6) for since 2018, so this patch updates the package to the new name. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I81e1a174ab25f573a7d7711eeeb26ef22fd3854b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-18spd_tools: bring README up to dateNick Vaccaro
bug=b:260128250 TEST=none Change-Id: I412044a13f636e87db1d2266b33c9134e746e1a2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76543 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18Makefile,genbuild: Provide length for abbreviated commit hashesNico Huber
The original default, minimum abbreviated hash length was 7. It dif- fers on newer systems, however. This breaks reproducibility, so set an explicit length. 12 hex digits should be good enough. Note: This sets only a minimum. With a high enough number of commit objects in the repository, Git could still decide to use a longer hash, again breaking reproducibility. 12 digits will hopefully pro- vide enough margin. Change-Id: Ia86e9cc41e27a0a57d498dcb13aec954c4ea0f04 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-17Center bootsplash on bigger framebuffersNico Huber
In the JPEG decoder, use `bytes_per_line` instead of `width` for address calculations, to allow for bigger framebuffers. When calling jpeg_decode(), add an offset to the framebuffer address so the picture gets centered. Change-Id: I0174bdccfaad425e708a5fa50bcb28a1b98a23f7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17util/xcompile: Add NASM to xcompileArthur Heymans
Reason: opensil uses nasm code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib8d89354bfd21113f77927186e418e2ec3eab44c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76465 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17crossgcc: Enable rv32iafc-ilp32 configurationPatrick Georgi
rv32iafc-ilp32 is compatible with rv32iac-ilp32 for library implementation, so add a reuse rule allowing the default configuration to support rv32iafc. -IAFC is an unusual configuration (much less common than -IMAFC), but multilib reuse has essentially no cost: this change is useful to users of platforms that support hardware floating-point but cannot use hardware multiply/divide for any reason. To avoid generating a new set of libraries this is limited to the soft-float ABI. Tested by verifying that `gcc -march=rv32iafc -mabi=ilp32 --print-search-dirs` refers to the rv32iac/ilp32 library directory as expected, rather than just the root library directory as occurs when an unsupported target is selected (for instance, rv32id). Change-Id: Ie056ba6488a138fe0876eebf7cbc59477b3c3518 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-15util/intelmetool: Remove useless break after a breakElyes Haouas
Change-Id: Ifb76d8fa09585ad6da9bfb1488a15bf853c4da99 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-14util/crossgcc: Update GCC version from 11.3 to 11.4Felix Singer
Change-Id: Ia9063af4495735a0e47f4cab1179441185d888b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-14util/lint/checkpatch_json.py: Make output message verbatimYu-Ping Wu
Some of the error messages of checkpatch.pl contain "*". Since now Gerrit supports markdown, messages with "*" will be rendered incorrectly. For example, foo* bar should be foo *bar will be shown as foo bar should be foo bar with "bar should be foo" being in italics. Fix the problem by surrounding the output message with "`" to make it verbatim. Change-Id: I02d0e894adf7f94a9e154f99321f51d4097963a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76392 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-07-11util/crossgcc: Fix broken link by Intel to acpica tarballFelix Singer
All requests to acpica.org are redirected to an intel.com site now, which breaks our buildgcc script as it's unable to download the source tarball. Use GitHub again as it's a more reliable source. *rant* Change-Id: Ie4570539d6c8abe59295e5a29b323b091e939f90 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76399 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06util/apcb: Add apcb edit tool for phoenixRob Barnes
Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into an APCB for phoenix platform. The tool makes several assumptions: * Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero. * Each block is 64 bytes. * Dimm and socket are always 0 * Unused SPD entries are zero'd BUG=b:281983434 BRANCH=None TEST=build, flash, boot myst Change-Id: Ifb50287de77138170714a702ab87d56427aacfef Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-04util/cbmem: add parsing of TPM logs per specsSergii Dmytruk
CBMEM can contain log in different forms (at most one is present): - coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as LB_TAG_TPM_CB_LOG) - TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG) - TPM2 format (CBMEM_ID_TPM2_TCG_LOG) The last two follow specifications by Trusted Computing Group, but until now cbmem couldn't print them. These formats were added not so long ago in: - commit 4191dbf0c9a5 ("security/tpm: add TPM log format as per 1.2 spec") - commit 53db677586e3 ("security/tpm: add TPM log format as per 2.0 spec") These changes make cbmem utility check for existence of TPM1.2/TPM2 logs in CBMEM and add code necessary for parsing and printing of their entries. TEST=`cbmem -L` for CONFIG_TPM1=y case TCPA log: Specification: 1.21 Platform class: PC Client TCPA log entry 1: PCR: 2 Event type: Action Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e Event data: FMAP: FMAP TEST=`cbmem -L` for CONFIG_TPM2=y case TPM2 log: Specification: 2.00 Platform class: PC Client TPM2 log entry 1: PCR: 2 Event type: Action Digests: SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c Event data: FMAP: FMAP Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c Ticket: https://ticket.coreboot.org/issues/425 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68749 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03util/sconfig: Improve usage and long optionsJakub Czapiga
Move usage function closer to main(), remove excessive printf() calls, use descriptive argument flags. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If5252de63692c5e43bfbde4d7d93e1d7a84e8dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/70524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-02util/docker/coreboot-sdk: Drop legacy libftdi packageFelix Singer
flashrom does not support libftdi 0.20 anymore and it's not used by anything else. Its build systems (Makefile and Meson) only reference libftdi1 and it still compiles fine without the legacy package. Thus, drop it from the package list. Change-Id: If1b575bc9abfd192e93811a83d8615bed61eba0c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-07-02util/docker/coreboot-sdk: Drop legacy libusb packageFelix Singer
flashrom does not support libusb 0.1 anymore and it's not used by anything else. Its build systems (Makefile and Meson) only reference libusb1 and it still compiles fine without the legacy package. Thus, drop it from the package list. Change-Id: Ib9b7530e5b707e12fbf3f8058999456dc1f8dff4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-02crossgcc: Upgrade IASL from 20230331 to 20230628Elyes Haouas
Changes: https://acpica.org/node/204 Change-Id: I4a1be7ffa6cb363d3fe0cddc59f0f4283fcc5257 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-27util/docker/coreboot-sdk: Install GNAT meta package instead gnat-12Felix Singer
The versions of both GCC and GNAT need to be in sync and the meta package for GCC is already used. So use the meta package for GNAT as well. Change-Id: Ifcd6960731bc02c70a510e520b385ca300caf88f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-26util/docker/coreboot-sdk: Drop subversion packageFelix Singer
Subversion is not used anywhere (anymore?). Thus, drop it from the package list. Change-Id: Ibf8073c7878c130ff688102e850bbdcd66e3becc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-24util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6Felix Singer
Change-Id: I68f776c676b1c3c5562e9209c68c7a840198e36f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flashMichał Żygowski
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 root ports functioning even if CSME/HECI is not functional. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23util/qemu: Add config for AArch64Nico Huber
Most arguments taken from the Kconfig help. RAM needs to be >= 531M, as coreboot is linked to reside between 512M..531M. Tested `make qemu` with QEMU 7.2.0. Change-Id: Id7f23918a786bc126188d5caf285e9f532dbb0ed Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-14util/abuild: Improve elapsed time measurementKyösti Mälkki
Time elapsed for a single board build with ccache typically measures well below 10 seconds. Improve the measurements to milliseconds resolution using bash EPOCHREALTIME (pseudo) environment variable. Change-Id: Iaedc470bb45cf9bb6f14ff8b37cd6f7ae3818a08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-14util/docker: Add Alpine DockerfileFelix Singer
Add a Dockerfile for Alpine to build-test with musl-libc. Change-Id: If90412146acc94f01a89cd681539aad48e92dd2e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-12Update goswid submodule to upstream masterStefan Reinauer
Updating from commit id bdd55e4: 2022-08-11 13:59:07 +0200 - (Add json minify to remove comments in JSON files) to commit id 567a1c9: 2023-01-18 20:38:13 +0100 - (Fix README.md uSWID table) This brings in 5 new commits: 567a1c9 Fix README.md uSWID table f5fd52f Add PlantUML Documentation cd56b5b Add uSWID Documentation 1a294af Add more comprehensive example in README b0e66ae Add plantuml output Change-Id: Ib399578a20c5c64978edf4b6198439bf6983ea44 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-12Update cbootimage submodule to upstream masterStefan Reinauer
Updating from commit id 65a6d94: 2019-07-17 17:47:14 -0600 - (Free image buffer on read error) to commit id 80c499e: 2019-09-19 12:41:46 -0600 - (Correct spelling mistakes) This brings in 1 new commits: 80c499e Correct spelling mistakes Change-Id: I0557e7116052e98266ee1d078a078d698232bb2c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75798 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-10board_status: Point to documentation in headerDavid Hendricks
This adds a pointer to the README and to the wiki in the header of board_status.sh. Change-Id: I5877a3bf3544f175ac74a5e5a8e1ef1cab366ab8 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/21569 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-10util/inteltool: Fix building with musl libcEvgeny Zinoviev
1. Make sure __always_inline is defined. 2. To test if we're on Linux, check presence of __linux__ instead of __GLIBC__. Change-Id: I2ccfc4d2ef4c60877e24508f9926b533cffec0ed Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2023-06-10util/inteltool: suggest booting with iomem=relaxedPeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: Ib80efd7d1ba516cb0ae4bdb86f95877855195ce0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63999 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04util/qemu: Revise q35 configsNico Huber
Add an NVMe drive and be more conservative with hotplug-capable PCIe ports. QEMU treats everything as hotpluggable by default, so devices can be added at runtime. However, this leads to unrealistic resource allocations with PCIEXP_HOTPLUG enabled. Tested recent allocator changes with QEMU/Q35 config and: $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg Change-Id: I23746b642329356c6767b04ec177cd9411e3adb9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67026 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-04crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5Elyes Haouas
Change-Id: I1f227bf55bac51e6226ca5d13156e54220e33629 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75635 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4Elyes Haouas
Change-Id: Id6dca6be8f7a82eadcbc18b4736219faf51b843c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02util/amdfwtool: Add ability to split hash tableKarthikeyan Ramasubramanian
Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-02util/docker: Split coreboot-sdk test into its own docker imageMartin Roth
This allows the coreboot-sdk docker image to build properly even if the testing fails, and keeps the added overhead out of the coreboot-sdk image. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6488799256f57ad64e14c93e7317b7ad2a71781c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenixFred Reitberger
BUG=285390041 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74971 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02amdfwtool: Add --output-manifest optionGrzegorz Bernacki
Passing this option tells amdfwtool to create a text file, containing the versions of the blobs below: - PSP bootloader (type 0x01), - SMU firmware (type 0x08), - AGESA bootloader 0 (type 0x30), - PSP bootloader AB (type 0x73). Created file can be embedded into CBFS which allows to read the version of blobs at runtime. This way version of blobs used to build the coreboot image can be verified at runtime and also from the binary file. Format of manifest file is following: $ cat build/amdfw_manifest type: 0x01 ver:00.35.00.13 type: 0x08 ver:00.5a.23.a6 type: 0x30 ver:2a.14.b0.10 type: 0x73 ver:00.35.00.13 BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-29util/crossgcc: Update nasm from 2.15.05 to 2.16.01Elyes Haouas
Timeless build for QEMU (i440fx/piix4) does not modify the binary. New patch is add to fix the build in a separate directory from the source. Change-Id: Ib69437be8ee69ad62fb1dfbbafabc2c4c885b7b2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-27util/ifdtool: Add support for Intel 800 series chipsetSubrata Banik
This commit adds support for Intel 800 series chipset. The new chipset can be uniquely identified by its SPI speed, eSPI speed, and chipset name. This commit message is clear and concise, and it accurately describes the changes that were made to the code. It also includes the following information: - Specify the correct chipset name. "PCH Revision: 800 series Meteor Lake" - Show the valid eSPI/EC frequency. "Read eSPI/EC Bus Frequency: 20MHz" Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I70619d9e3ed2bcad86f84a0527e3a0ad13acd706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-27libpayload;arch,cpu/x86: drop USE_MARCH_586 Kconfig optionFelix Held
Only the Intel Quark SoC selected this option and that SoC was dropped in commit 531023285ea4 ("soc/intel/quark: Drop support"), so drop this Kconfig option too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4f1c7530cd8ac7a1945b1493a2d53a7904daa06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75473 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26commit-msg: Match the Signed-off-by line with name and mail addressZheng Bao
The previous regular expression only matches the line starting with "Signed-off-by:". If the name and mail address are missing, it can not find out. The following words should be "name <mail@xxx.com>". Change-Id: I42cc399e79b65928a6aef87c51e5476c7158d166 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-26util/crossgcc: Update binutils-2.40 import set_entry_point patchElyes Haouas
Import set_entry_point patch from https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3539414584be0094b0a4fe56dfd64ea79d802edc to fix issue in binutils 2.40 with LTO when applied to PE/PE+ binaries (i.e. UEFI). Change-Id: I3844b53c8761239932ce91c2ff19ed0402321d1a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-25crossgcc: Upgrade IASL from 20221020 to 20230331Elyes Haouas
Changes: https://acpica.org/node/202 Change-Id: I43fc180bd51ff7cb06a67619c8350d28b086bc90 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-24util/crossgcc: Add empty directory for tarballsFelix Singer
A directory for tarballs is needed in any case but it's created at build time. However, in reproducible build environments the sources are downloaded before the buildgcc scripts runs and the directory needs to be created. Thus, to simplify that, add an empty tarballs directory. Change-Id: Id3b4bf918c93f10c145f580684e916a4f8bae3b1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-24amdfwtool: Set the minimum size of entry PSPL2 A/BZheng Bao
This is a PSP FW requirement. This is only for recovery A/B without ISH header. That means only Cezanne. Change-Id: I62616d5a866f66fc71e6c0b31a23c62dc11cf3c6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-23crossgcc: Upgrade LLVM version 15.0.7 to 16.0.4Elyes Haouas
Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22util: Use common ARRAY_SIZE defineKonrad Adamczyk
Remove duplicated definitions of ARRAY_SIZE macro across util/ dir. Instead of duplicates, use the one from commonlib/bsd/helpers.h file. BUG=b:231765496 TEST=make -C util/cbfstool; make -C util/cbmem; make -C util/intelmetool; make -C util/superiotool Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74474 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Grzegorz Bernacki Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22util/kconfig: Fix default value getter for integer optionsKrystian Hebel
CB:37152 was supposed to be uprev to Linux's kconfig, but it got this one case wrong, Linux never returned "0" [1]. As a result, when an option has default value different than 0, and it was changed to 0, savedefconfig skips saving it. However, during the build from such defconfig the option is assigned default value. TEST=Set SEABIOS_DEBUG_LEVEL to 0 and see that savedefconfig writes it to defconfig file. [1] https://github.com/torvalds/linux/commit/7cf3d73b4360e91b14326632ab1aeda4cb26308d Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I821e45dcec99904fab85f136298cbd0315237ff6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72650 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-05-17util/docker: Add Dockerfile for Arch LinuxFelix Singer
Add a minimal Dockerfile that pre-installs necessary software which is needed to work with coreboot. Change-Id: I85f3dc7b28b77989f0f1400d1282ed4b17082f65 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-05-16util/chromeos: Add EC header update utilityCaveh Jalali
This adds a new utility for copying ec_commands.h and ec_cmd_api.h from the chrome EC repo with the appropriate copyright header adjustment. It is invoked as: util/chromeos/update_ec_headers.sh [EC-repo] where EC-repo is the top of the EC repo from which header files are to be obtained. The corresponding files in src/ec/google/chromeec are updated but not committed. Also, a commit message is suggested with the original git versions for reference. BUG=b:258126464 Change-Id: Ib43c75d807dd925b2c4bff425c07a36b4b4582c4 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-11util/scripts/show_platforms.sh: Fix reStructuredText table outputNicholas Chin
reStructuredText grid tables require row separators otherwise the rows get concatenated into a single cell for each column. Representative output of previous behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Representative output of corrected behavior: ```eval_rst +-------------------------+-------------------+------------+----------+ | Vendor/Board | Processor | Date added | Brd type | +=========================+===================+============+==========+ | 51nb/x210 | INTEL_KABYLAKE | 2020-03-16 | laptop | +-------------------------+-------------------+------------+----------+ | acer/aspire_vn7_572g | INTEL_SKYLAKE | 2022-01-28 | laptop | +-------------------------+-------------------+------------+----------+ | acer/g43t-am3 | INTEL_X4X | 2020-09-28 | desktop | +-------------------------+-------------------+------------+----------+ ``` Change-Id: I83be58dd2c34c65ae2c65cf2bd98330936fb6f6a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-11util/inteltool: Add ADL-S device identificationsMaximilian Brune
R680E, Q670E, H610E are the ADL-S IoT variants see also: commit a0bc90e4abfe ("Add missing ADL-S device identification") Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1dbfa0464bc22f9bcf91d9e9fa9eb79132600175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-08util/amdfwtool: Consolidate entry line regex patternKarthikeyan Ramasubramanian
There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-04-28amdfwtool: Increase MAX_PSP_ENTRIESFred Reitberger
The MAX_PSP_ENTRIES constant reserves space for the psp directory table entries. This table is aligned to 4K and the next binary is also aligned to 4K. The number of psp directory entries on Birman exceeds the previous limit, so increase it to the maximum that will fit in a 4K block. TEST=timeless builds for Birman unchanged Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I297edc9cccffde0ad1ce7461b375542f9f2f7c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-27util/ifdtool/ifdtool.c: Fix default FMAP generationMaximilian Brune
According to SPI programming guide, a region limit of 0 as well as region base of 7FFFh indicates an unused/reserved region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I790d7f5631ecef3043b2c17c41430dc4fd854f72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-27util/cbmem: Add REG_NEWLINE flag to fix matching patternKonrad Adamczyk
Match-any-character operators (eg. ".*") shall not match newline characters for BANNER_REGEX, since given regular expression matches newline explicitly. Add REG_NEWLINE flag to `regcomp` call. BUG=b:278718871 TEST=Boot firmware on skyrim, reboot. Run `cbmem -2`. `cbmem -2` returns second-to-last boot log. Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-04-25util/docker/jenkins-node: Drop Zephyr SDKFelix Singer
The version of the Zephyr SDK that is used is quite old and Zephyr hasn't been really used. Thus, drop it and also its dependencies from u-boot. Change-Id: Ie498d687e1566133adf650166117d8f68fcfdaf6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-04-25util/docker/jenkins-node: Allow pip to install packages system-wideFelix Singer
Call pip3 with `--break-system-packages` allowing it to install packages system-wide. This fixes building the Docker container. Change-Id: Id093f2c69fec43556c434fbca7b36095a7e6bd97 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-25util/docker/jenkins-node: Merge package installations into first stepFelix Singer
It's not necessary to have multiple steps for installing packages and requirements. Just merge the two install steps to one. Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74245 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-22lib/version: Move board identification stringsKyösti Mälkki
These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21util/inteltool: Add support for Jasper LakeKarol Zmyslowski
Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor) Based on Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 revision 001 (DOC# 634545) Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-04-17crossgcc: Upgrade CMake from version 3.26.2 to 3.26.3Elyes Haouas
Change-Id: Iab8d67632f97c596baa9b430228d4aae6fa48126 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-16util/cbfstool: Qualify struct e820entry as packedBill XIE
In order to accord with grub (see include/grub/i386/linux.h) and comments for offsets of members of struct linux_params, struct e820entry should be defined as __packed, otherwise, sizeof(struct linux_params) will become 4224 (0x1080). Fortunately, the affected area is usually not occupied. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I09955c90e4eec337adca383e628a8821075381d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-04-13mb/google/rex: add variant gpio tables for variant creationYH Lin
BUG=b:276818954 TEST=new_variant_fulltest.sh rex0 BRANCH=None Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iebc098f8d480ac3e1835b00861fd844d97f281a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-13cbfstool: Add comment to define stability rules for cbfstool print -kJulius Werner
In CB:41119, I sort of made up a mechanism on the fly for how to make the machine-parseable cbfstool print output extensible without breaking backwards compatibility for older scripts. But I only explained it in the commit message which is not very visible. This patch adds a comment to the function that generates that output so that people who want to change it can understand the intent. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0d18d59e7fe407eb34710d6a583cfae667723eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-11util/sconfig: Remove unused ioapic and irq keywordsArthur Heymans
Ioapic information in the devicetree was only used to set up mptables but this generic driver was removed (ca5a793 drivers/generic/ioapic: Drop poor implementation). This removes the unused remainders from mainboard devicetrees. Remove ioapic setup from sconfig. Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-08ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .backlight_enable = 0x01, ^~~~ /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .dock_event_enable = 0x01, ^~~~ Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-07Revert "cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOS"Arthur Heymans
This reverts commit 89b4f69746ac215e4a7c5f204d1ea807b4ea08b5. SI_BIOS is mostly used to indicate the BIOS region in Intel IFD. Not all platforms are Intel platforms with an IFD, so revert this change. Also tooling often depends on names not changing so renaming things should not be done lightly. The default region should also be in sync with non-x86 and made systematic across the tree. Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74290 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-04-06tree: Replace `egrep` with `grep -E`Felix Singer
For compatibility reasons, egrep is just a wrapper around grep today. Thus, replace it with `grep -E`. Change-Id: Ief08a22e4cd7211a3fee278492c95d37f9e058fa Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-06util/lint/stable-017: Update full config pattern matchingArthur Heymans
CONFIG_ARCH gives false positives for CONFIG_ARCH_X86_64_PGTBL_LOC so use a different string: 'CONFIG_MAINBOARD_DIR'. Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74220 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-05util/spd_tools: Add support for Phoenix platformKarthikeyan Ramasubramanian
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform so that SPD can be generated for the memory parts used in that platform. SPD requirements for Phoenix and Mendocino platforms are identical. BUG=b:273383819 TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms share the platform manifest for LP5 memory parts. Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-03util/crossgcc/buildgcc: Allow bootstrapping CMake with multiple threadsFelix Singer
The main build process already runs multi-threaded, when requested. Apply the same setting to the bootstrap / configure step. Change-Id: I89d6728a0985946b702f83770bedf767afb12690 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74156 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02crossgcc: Upgrade CMake from version 3.25.2 to 3.26.2Elyes Haouas
Change-Id: I62078257fd84a64c699a7f930bc306e38d2f4058 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73791 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-01util/crossgcc: Update binutils from 2.37 to 2.40Felix Singer
Change-Id: I34a20a999f7ea624c1add4750fcd116166953dd8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-04-01util/docker/coreboot-sdk: Remove Python 2 packageFelix Singer
Debian removed Python 2 from their Sid repository and so it needs to be removed from the Dockerfile as well. Built and tested the Dockerfile with Python 2 removed. Still works. Change-Id: If4e298dc275c1dfaf57cd4c3f8e5f89410318ec0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-03-28util/cbfstool: Add usage information about verbose outputMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ica512d21d1cef8ccffbc093016c7a3bfcf901b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73488 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-28cbfstool/default-x86.fmd: Rename BIOS -> SI_BIOSMaximilian Brune
Currently ifdtool --validate will not correctly validate the FMAP against the IFD regions, since it will compare the IFD bios region with an FMAP region called SI_BIOS. It's probably a good idea to define default name for the BIOS FMAP region like we have for 'COREBOOT' or 'FMAP' FMAP region. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I55eddfb5641b3011d4525893604ccf87fa05a1e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28util/ifdtool: Add option to create FMAP templateMaximilian Brune
On systems that do not provide their own *.fmd (Flashmap) file, we fall back to a default flashmap file. That file however does not contain the blobs (ME, GBE ...), that are usually placed below the BIOS Flashmap. It can therefore easily happen that the placement of the blobs collides with the placement of the BIOS region (e.g. if CBFS_SIZE is big enough). The fmaptool can't catch that, since it does not know of the blobs placement. This patch basically maps the regions described in the IFD (Intel Firmware Descriptor) to the default Flashmap. Test: Build and see that build/fmap.fmd contains all blobs now (on intel systems that are supported by the ifdtool) Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I82cb252fff456773af69943e188480a4998736fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24amdfwtool: Clean up table buffers before combo loopZheng Bao
Keep clean copies of PSP and BIOS table. Refresh the working tables before they are filled with file names and other information at each iteration. Change-Id: Ie8339a4d66c38e02180cbf99e13914bfff66dc0f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Add missing help information for --combo-config1Zheng Bao
Change-Id: I6b69965991daadaf8b4148b06d0715b087021c9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Call wrapper funtion to write fileZheng Bao
Don't call system call directly. Change-Id: I6da31723bc2bfc1197fc31962053671c84ccc397 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Move some funtions to other categorized source filesZheng Bao
To reduce the size of amdfwtool.c which is already too big. Change-Id: Ib80eeb42f59a3dda04402b2feaadc1d178ed989e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-21util/amdfwtool: remove unused union from embedded_firmware structFelix Held
Since commit 2f6b7d557d97 ("amdfwtool: Move the filling of table headers into functions"), the combo_psp_directory union element in the embedded_firmware is unused and the new_psp_directory element is used in all places, so replace the union of new_psp_directory and combo_psp_directory with just the new_psp_directory struct element. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35d339b3084ec8f93210095c233f5e68296d0013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-17util/liveiso: Move NixOS configs to subdirectoryFelix Singer
Move the NixOS configuration into a subdirectory so that configurations for other distros can be added as well. Change-Id: I0462c1a6541878c973be4302c5c5e9e9bfaed2a6 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 01:56:30 +0000