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2024-06-25util/autoport: Move SPDX header before defines in dsdt.aslNicholas Chin
Macros were being printed before the SPDX header in dsdt.asl, so fix this. Previous output: #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB /* SPDX-License-Identifier: GPL-2.0-only */ Change-Id: Idebdcf816911af9d262a114c86461e6fa5bfd1f8 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83187 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24util/autoport: Remove extra blank lines from generated filesNicholas Chin
The generated dsdt.asl and early_init.c files contained 2 consecutive blank lines, so remove one of them. Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83186 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-23util/autoport: Remove bd82x6x/pch.h from generated mainboard.cNicholas Chin
The southbridge/intel/bd82x6x/pch.h header was previously used to configure a few registers in SPIBAR, but these have since been moved to PCH code and the devicetree, making it unnecessary in mainboard.c Change-Id: I904c95394b4fea73b4990342e647595b5f10335f Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82601 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21coreboot-sdk/Dockerfile: Remove explicit install of 'm4'Elyes Haouas
Remove m4 as an explicity installed package as it will be installed automatically by flex and bison. Change-Id: Ic4f1c5e6f3324429914bf593047d802dfcc0cb30 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82512 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21util/intelp2m: Remove blank line after '{'Maxim Polyakov
The generator inserts into the gpio.h an unnecessary blank line in front of the list of macros in the table. Let's remove this from the template to make the code cleaner. These changes have no effect on the configuration of macros. Change-Id: I1141ca630cb6d9a46be5bce2b434762ef8e6fdd0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83003 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21util/intelp2m/platforms: Fix DW register number before clear itMaxim Polyakov
This error does not affect the generated files as the tests are running [1, 2, 3]. However, this once again confirms the need to work on updating the utility. [1] CB:67132 [2] CB:67133 [3] CB:67134 Change-Id: I91e74d65977bd5e10589530258d1709ea33f1af5 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83002 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21util: Move remainings from ipqheader to qualcomm directoryElyes Haouas
With commit 101098c41a ("sdm845: Combine BB with QC-Sec for ROM boot"), most files from ipqheader were moved to the qualcomm directory. Change-Id: I4e5136bd5ec4fd47bbd93cea2e4614fa63a3bd4e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-21util/ifdtool: Add Panther Lake platform support under IFDv2Subrata Banik
BUG=b:347669091 TEST=Able to build ifdtool. Change-Id: Id261898932f11f4c9066453bce18fd889996e171 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-20cbfstool: Read XIP stage alignment requirements from ELFArthur Heymans
On x86_64 romstage can contain page tables and a page table pointer which have an larger alignment requirement of 4096. Instead of hardcoding it, read if from the ELF phdrs. Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82102 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-19util: Break up spdx identifier text in scripts & makefilesMartin Roth
The SPDX parsers can find the SPDX identifiers in the scripts and makefiles if they aren't broken up. This unnecessarily confuses things when we're doing license parsing. Change-Id: I215ed047397f342c912f1a969315fa184a124f6a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-06-17util/intelp2m: Add support for Emmitsburg macro generationFabian Meyer
Test: Generated GPIO for ASRock Rack SPC741D8-2L2T/BCM. Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797 Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-06-17util/autoport: Factor out yes/no prompt handlingAngel Pons
In preparation for introducing other yes/no prompts, factor out the logic into a common function. Change-Id: Iff1f0c6c665a5352013122fb791121a116c434f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-14util/inteltool: Add more Westmere/Ironlake device IDsAngel Pons
The host bridge PCI device ID can be changed by the firmware. There is no documentation about it, though. There's 'official' IDs, which appear in spec updates and Windows drivers, and 'mysterious' IDs, which Intel doesn't want OSes to know about and thus are not listed. For the sake of completeness, add the PCI device IDs for Clarkdale. Though coreboot only supports Arrandale, both of them are Ironlake. It is possible that the Management Engine handles changing the PCI device ID, which would not happen when using a broken ME firmware. Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-14util/smmstoretool: add uint64 data typeSergii Dmytruk
It's in particular useful for working with variables that contain 64-bit pointers, like CapsuleUpdateData* global variables defined by UEFI specification. Change-Id: I4b46b41cdc5f69d4ca189659bef1e44f64c0d554 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-06-14util/smmstoretool: fix uint{16,32} not being listed by helpSergii Dmytruk
These data types were added during review of CB:79080 but they weren't added to the help message. Change-Id: I6e79d65c80c292c3f5d2a2611e602db5cc6cf374 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82610 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
2024-06-12util/autoport: Update for recent USB developmentsKeith Hui
Update autoport for: 1. Commit ee126348726b ("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree") 2. Commit 94625d2aae76 ("sb/intel/bd82x6x: Allow actual USBIRx values for native USB config") As a side effect of #2 above, no more (broken anyway) FIXME comment will be written for usb_port_config. Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-10util/autoport: Assign SPD addresses in devicetreeAngel Pons
Commit 45e4ab4a660c (mb/*: Update SPD mapping for sandybridge boards) changed the way in which SPD addresses are set up for SNB/IVB boards, but autoport was not updated to reflect these changes. Result is: register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" # FIXME: Put proper SPD map here" The stray quote at the end is irritating, but is hard to get rid of without substantial refactoring of autoport's guts. But, given that this is a FIXME comment, anyone using autoport should just drop the comment after verifying the SPD map, so it's not a big deal. In addition, update the corresponding section of the README, which was horrendously out-of-date. Change-Id: I6ad38f53afc4fafb45be7f086723cc0782a965ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82405 Reviewed-by: Keith Hui <buurin@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-09util/superiotool: Add support for dumping ITE IT8659E configurationMichał Żygowski
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2 (For H Version)". TEST=Dump IT8659E configuration on the new Protectli platform Change-Id: Ic036f8b99d5bd0107be7850fc4509da1bf020fe5 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-07sb/intel/bd82x6x/early_usb.c: Align native current map with MRCKeith Hui
Replace 3 unused values in the map with those found during a Ghidra examination of MRC binary, and on hardwares running vendor firmware (asus/p8z77-m and HP Z210 CMT Workstation). The outgoing values were introduced in commit 216ad2170ca8 ("sb/intel/bd82x6x: Add new USB currents") in anticipation for Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually abandoned. Since commit xxxxxxxxxxxx, such values can be placed directly in the port config, so there should be no hurdle should that effort be resurrected. Add a few #defines in pch.h to place some inline documentation on MRC values, but more will be documented in the future when this mapping is introduced MRC-side. Finally, update autoport to match. Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-06-07util/smmstoretool: explain what happens when no store is foundMaciej Pijanowski
We are going to expose ths tool to end users, and want to take care that the presented information can be consumed by them. The current code simply prints below warnings if we use release binary available for end-user to download: No firmware volume header present No valid firmware volume was found It will be concerning and not clear to end users, they might not understant why it happens, what are the implications, and whether it is something that they should worry about. This commit tries to explain what actually happens here. Change-Id: Iaa2678f5ae7c243811484c0567ced97ae0b3fc0a Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-06-04util/xcompile: Use new GCC's warning options only if supportedElyes Haouas
Wflex-array-member-not-at-end & Wcalloc-transposed-args are not supported when using GCC older than GCC-14. Use them only when supported. Change-Id: I11c1e729569c8130bd254a10454c5066a72974d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82785 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-03util/cbfstool: Fix linux_trampoline.c generationShuo Liu
linux_trampoline.c generation is broken with latest crossgcc-i386 toolchain. Fix the issue to enable the building. ../cbfstool/linux_trampoline.S: Assembler messages: ../cbfstool/linux_trampoline.S:100: Error: no instruction mnemonic suffix given and no register operands; can't size instruction <builtin>: recipe for target '../cbfstool/linux_trampoline.o' failed TEST=Build and boot on intel/archercity CRB cd util/cbfstool/ rm linux_trampoline.c make linux_trampoline.c Change-Id: I7faca296f946bb4e9fd510661357925e5dcf9a6b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82704 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29util/nvidia: Use c11 dialectElyes Haouas
Change-Id: I75909ce85eed549d9094ba6f62d93656621d9f0d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82679 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29util/superiotool: Use c11 dialectElyes Haouas
Change-Id: Ic03d9ac883a92d52467d563f048446871b928712 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-27lint-stable-003-whitespace: Exclude DTB filesMaximilian Brune
This excludes Devicetree blob files from the list of files to check for superfluous whitespaces. A DTB file has recently been added in commit 33079b8174 ("lib/device_tree: Add some FDT helper functions"). Change-Id: Ic25ee5361163446370c530cccefa3bf085895d15 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82638 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21lib/device_tree: Add some FDT helper functionsMaximilian Brune
This adds some helper functions for FDT, since more and more mainboards seem to need FDT nowadays. For example our QEMU boards need it in order to know how much RAM is available. Also all RISC-V boards in our tree need FDT. This also adds some tests in order to test said functions. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81081 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-20crossgcc: Update LLVM from 18.1.5 to 18.1.6Elyes Haouas
Change-Id: Ie087f43e6f60df7b97d7d7b402d3540c3a0a2461 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-20util/docker: Change Debian suite from Sid to stableMartin Roth
Debian sid is too unstable at this point, and frequently ends up having issues that cause the coreboot-sdk docker image to fail to build. Using stable also better reflects what users will typically be running. Also remove the parameters to quiet the apt-get install command so that if something does break, we can see what happened more easily. Fixes bug 536 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I41b6464b024df89c114db2cdb9367c0526eb0297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82411 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-15util/crossgcc: Update GCC from 13.2 to 14.1.0Felix Singer
Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81683 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-05-15util/crossgcc: Update LLVM from 17.0.6 to 18.1.5Lennart Eichhorn
Change-Id: I03a44e0c23a925396f614f282882405dc886ba58 Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-05-15crossgcc: upgrade nasm from 2.16.01 to 2.16.03Elyes Haouas
Remove the patch since it was picked from master before and thus it's included in the new release. Change-Id: I70408b189b974f8abaadc66f0c809a1dbe10504b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81900 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14util/crossgcc: Update ACPICA from 20230628 to 20240321Felix Singer
Change-Id: I41f56ba58af51b1ec1d7554fb35a49ccf9e778f6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-14util/crossgcc: Update CMake from 3.28.3 to 3.29.3Felix Singer
Change-Id: Iaf2d4f579d987fbfd4187ae41c1be5cec55e0e8e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-14util/autoport: Remove incorrect commentAngel Pons
Yes, the DSDT revision is the OEM revision. But most certainly not that of the board being ported. Because no one seems to care about the value (newer boards inexplicably use lower values even though this represents a date in 0xYYYYMMDD format), simply drop the incorrect comment. Should save a bit of effort when reviewing mainboard ports: no longer will one have to ask authors to drop the comment. Change-Id: I9c425573e4fcb0f670a780e7821e815eadc8a2aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-14util/autoport/.gitignore: Ignore `logs` folderAngel Pons
The README suggests using `logs` as the folder name where autoport puts the generated logs. Thus, add this folder to .gitignore for the sake of convenience. Yes, people can use other folder names, but `logs` is most commonly used. Change-Id: I37906b43ba3e132de616184e4a5082ce00f4b230 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82398 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-05-13util/inteltool: Fix Emmitsburg GPIO Group J pad namesFabian Meyer
Pad names now matching soc/intel/xeon_sp/ebg/soc_gpio.c. Test: Generated pad names for ASRock Rack SPC741D8 now compile. Change-Id: Ied53b654f905add86a05bce8c2e366dea9ccf4d3 Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82205 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-12util/intelp2m: add Meteor Lake supportFilip Lewiński
Enables parsing Meteor Lake inteltool output into gpio.h pad macros. Change-Id: Iaebd51d587507e68c6f263b92dc61cb6c0411bf8 Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81916 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-05-12util/inteltool: add Meteor Lake supportFilip Lewiński
Based on: Intel Core Ultra Processor External Design Specification Meteor Lake SOC IO Registers Meteor Lake-U/H/U Type4 and Arrow Lake-U/H GPIO Implementation Summary Change-Id: I7473119fa97c57cd2a1303f08f964abd0ca96270 Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-05-08util/chromeos/crosfirmware: ensure $BOARD is lowercaseMatt DeVillier
If $BOARD is not all lowercase, then certain subfunctions of the script will fail due to case-sensitive comparisons therein. To avoid this, since all matched strings are fully lowercase, set $BOARD to lowercase. TEST: './crosfirmware.sh {akemi/Akemi/AKEMI}' all succeed. Change-Id: I8ecb613a8d9384e2cccaff5183470e2e9956d0a2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-06util/util_readme: Update post_util.md for MyST ParserNicholas Chin
This file is appended to Documentation/util.md by the util_readme.sh script, and contains toctree entries for utilities with more in-depth documentation than the description automatically pulled from the description.md files throughout the util directory. As of commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser), the syntax for creating a toctree has changed, so update this post_util.md accordingly. Change-Id: Ia7ae3c513781e53512763578fd97db7e2f75e65c Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-05-04docker/coreboot-sdk: Replace 'pkg-config' with 'pkgconf'Elyes Haouas
Replace transitional 'pkg-config' package with 'pkgconf'. Change-Id: I9ee895cb2ca3186c4aefbdab1fd71778bf981009 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82167 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-26util/docker/coreboot-sdk: Remove libcurl4 from the package listMichał Żygowski
When installing the packages, apt-get returns an error about holding broken packages. It occurs the diffutils depends on libcurl4t64 which breaks the libcurl4. As a solution, remove the libcurl4 from the list, and let the package manager resolve the dependencies. TEST=Build coreboot-sdk Change-Id: Iabc4f74619d4462317d8adb4068e50135d89d80e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-25util/ifdtool: Add support for checking GPR0 statusTyler Wang
This patch adds support for the new command-line option `-c` to the ifdtool, which is able to check GPR0 (Global Protected Range) status. This patch also add helper function get_enabled_gprd() to get enabled GPR0 settings. It used in enable_gpr0() and is_gpr0_protected(). Developers can use ifdtool with '-c' option to check whether GPR0 is set to enabled or disabled in the binary file. BUG=none TEST=(1) > ifdtool -p mtl -E image-unlocked.bin -O image-lock.bin ... Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff ... GPR0 protection is now enabled (2) > ifdtool -p mtl -c image-unlocked.bin GPR0 status: Disabled Value at GPRD offset (64) is 0x00000000 --------- GPR0 Protected Range -------------- Start address = 0x00000000 End address = 0x00000fff (3) > ifdtool -p mtl -c image-lock.bin GPR0 status: Enabled Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff Change-Id: I6b3af973be784200b965a68e5f6b7737cba03ed7 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2024-04-20util/lint: Add lint rule to watch for Makefile.incMartin Roth
This should keep new makefiles from being named Makefile.inc. Change-Id: I4a47998e1c997b82b8a15319eae96cdc0de64e77 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81857 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-04-17util/crossgcc/buildgcc: Use Intel mirror for ACPICAFelix Singer
The binary hashes from GitHub releases are not stable. Use the Intel mirror. Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80721 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-16buildgcc: Match the string of downloading percentage more preciselyZheng Bao
The command "wget" prints some hyperlink with "%", which will be filtered in by previous regular expression. So we need to change to match the string with exactly 3 digits and a percent symbol. TEST: echo 45% | grep -o "\<[0-9]\{1,3\}%" 45% echo 1245% | grep -o "\<[0-9]\{1,3\}%" <empty> echo aa% | grep -o "\<[0-9]\{1,3\}%" <empty> Change-Id: I6ef9e7c87fd4ee6cc707346954d91e6e3af3b939 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-04util/intelp2m: Add support for TigerLake-H SoCAlicja Michalska
Add support for TigerLake Halo SoC, based on CNL profile. Test: Convert GPIO dump from inteltool into coreboot macros for out-of-tree TGL board. Change-Id: I26eff225c2045edfe5836283be7b4c63f6b405e8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-04-03util/kconfig: Uprev to Linux 6.8's kconfigPatrick Georgi
Linux kconfig has its own implementation of KCONFIG_WERROR now, so use that. This reduces our patch count by 2. Change-Id: I4f5f1f552e96f8ef7a4c5c0ab2ab7e2b6d798ceb Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81223 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-02util/kconfig: Put our SPDX fix in the patch queuePatrick Georgi
With this, `quilt pop -a` leads to an original Linux kconfig tree, making it easier to apply kconfig updates. Change-Id: I771bbd0f8244cae38317bd5b1f809b74771b176f Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-30util/crossgcc: Also build LLVM LDArthur Heymans
When doing LTO the clang linker frontend needs to use LLD or gold. Build LLD as that is the configuration that is best tested. Change-Id: I3242585f8b5c3426fc6568d3dc47300164d56e3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-30util/xcompile: Use a more complete clang targetArthur Heymans
When the compiler is used as a linker frontend clang tries to match the target string with what it supports internally. If it's not sufficiently complete it will forward linking to GCC which is not desirable. This is necessary when doing LTO with clang. Change-Id: Ie9356a2bc0f5b77e934cc16482d6ccb1961195dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80730 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-27cbfstool: Add printing of legacy stage typeVladimir Serbinenko
This is useful for listing older images. Change-Id: I588028d4327f59538f7c9920b671458fc631cb4c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-26util/xcompile: Add target architecture to CPPFLAGSArthur Heymans
In order to preprocess linker scripts the target architecture needs to be specified. With clang this needs to be set via a cli argument. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-23amdfwtool: Use macro to get the table relative addressZheng Bao
TEST=Identical binary test on all AMD SOC platform Change-Id: Iece4ba65e0476543a8d472168d93801714330dde Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78281 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23util/lint: Fix license header regexNicholas Chin
A trailing "|" at the end of the regex added a zero length alternative match, causing all files to match and be filtered out. This was causing `make lint-stable` to ignore all missing license headers, preventing the pre-commit git hook and Jenkins from detecting these. Also, a missing "|" separator between cmos.default and .apcb would cause those files to be unintentionally scanned. Change-Id: I70cc3a5adf7edee059883cd3cbe02029776b02ef Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-22amdfwtool: Only update count in header in only one functionZheng Bao
Other function calls don't have to worry about the fletcher error. TEST=Binary identical test on all AMD SOC platform Change-Id: I7c9d653100b476b52d6d1d80c41d0c3d765f7be3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-21amdfwtool: Move linking BHD2 to PSP2 from main to link funcionZheng Bao
Move the complexity from main to function, so the main flow is easy to understand. TEST=Identical test on all AMD SOC platform Change-Id: Ia549a0d08c2a60b8858440543ac8d8b5259017dd Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-21util/smmstoretool/fv.c: fix 3 formatting issuesSergii Dmytruk
Change-Id: If27218df40e58f249769b3d84c0cd4c299e2282b Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-21util/docker/: Drop recommonmark pip moduleNicholas Chin
The documentation is now built using MyST Parser, so Recommonmark can be dropped. Change-Id: I7f6810c9429573c0c51d3d72b36e9fc2ae2185f5 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80313 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21util/docker: Update Dockerfiles for building documentationNicholas Chin
Update all pip packages related to coreboot's documentation to their latest available version, and update the doc.coreboot.org base image to Alpine 3.19.1. Add myst-parser in preparation to switch from Recommonmark to MyST Parser. TEST: The documentation builds and renders properly when built using the updated container. Change-Id: I8df4aadabc49c0201a836333745fe138184595ac Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80312 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21docker/doc.coreboot.org: Install pip modules into virtual envNicholas Chin
Currently, pip modules are installed system-wide, which may cause conflicts with modules installed using the package manager. Newer versions of the Alpine base image also mark its system wide Python installation as an externally managed environment, which will cause pip to return an error as per recent Python recommendations [1]. TEST: - `make -C util/docker doc.coreboot.org` builds the container successfully - `make -C util/docker docker-build-docs` builds the documentation successfully [1] https://peps.python.org/pep-0668/ Change-Id: Idd9cc5e6fb28b42ef8e4fa5db01eb9ef192ba0ec Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-03-20amdfwtool: Check sanity before filling the data arrayZheng Bao
Change-Id: I8284c35a0124ba4588d199024e28d3445c681896 Signed-off-by: Zheng Bao <fishbaozi@gmail.com>wq Reviewed-on: https://review.coreboot.org/c/coreboot/+/78763 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20amdfwtool: Set the cookie when the table header is createdZheng Bao
When the table is created, the cookie is known. When the packing going on, the cookie in header can be checked to see where we are. TEST=Identical test on all AMD SOC platform Change-Id: I300e30292c68a14b44c637b26a13b308dc9c0388 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81254 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20amdfwtool: Move the header creation into integration functionZheng Bao
Before every integration there is a header creation. We can put them together. And the parameters for PSP/BIOS tables are useless. TEST=Identical test on all AMD SOC platform Change-Id: Ia9d78bb8145855203048208fcd67f8b9cd9d3199 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-20amdfwtool: Add functions to link all the tablesZheng Bao
The purpose of integration function is to pack the FWs into table. We need to remove other process. Create a dedicate function to link all the tables together. And this linking function is only called when both the level 1 and level 2 directory are created. This simplifies the main function and logic. TEST=Identical test on all AMD SOC platform Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-20amdfwtool: Move the address of tables to the contextZheng Bao
Instead of being local variables. This can be easier to find all the tables anywhere. TEST=Identical test on all AMD SOC platform Change-Id: I98b7d01e32c75b4f13e23d496cd3de3da900678d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-18amdfwtool: Compact the parameter transferingZheng Bao
Remove redundant parameter "debug" from open_process_config(). Change-Id: Ib91a505838d7be4980d6b4f1e95fb8601fbbfd16 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81201 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-18amdfwtool: Remove the dissociated combo BIOS table for recovery A/BZheng Bao
For recovery A/B mode, the BIOS tables level 2 are traced by PSP table instead of ROMSIG. There should not be a dedicated BIOS table, nor a combo BIOS table. Change-Id: I8735bd91b32bc9a0e4fc70d293e8d836d5e9c36b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17genbuild_h: Fix and harden major/minor version parsingNico Huber
Our major version is suddenly two digits long to represent the year. This can't be parsed with the current sed scripts. To make sure that no unparsed data ends up in our major/minor versions, we'll run sed with `-n' and only print the extracted numbers if anything. Also, to allow us to use the version numbers in C code, we strip leading zeros (a leading 0 identifies octal numbers, so for instance 08 for August is not a valid number). This can result in empty major/minor version strings, so we move the default `0' to the final variable expansion. As a bonus, this makes an explicit check if the numbers can be parsed unnecessary. Change-Id: Ie39381a8ef4b971556168b6996efeefe6adf2b14 Reported-by: Christoph Zechner <christophz@vrvis.at> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81290 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17util/intelmetool: Print the address in `map_physical` errors in hexMate Kukri
Previously the incorrect 'd' format specifier was used despite the '0x' prefix implying hex to the user. Change-Id: Ib97bd86ee0e0c8fe8c3785e22a4d9f6def3cae61 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-17amdfwtool: Set the level based on cookieZheng Bao
It was complicated and weird to check both the cookie and whether one table is a null pointer. Just checking the cookie is enough. TEST=Identical test on all AMD SOC platform Change-Id: Icab74714990f74e11fd5e899661e4e2d41230541 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81208 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17amdfwtool: Set the table size only for FWsZheng Bao
The entry in the table has two categaries, file and pointer. For the pointer, it does not take table space. The ISH, PSP level 2, BIOS table are all the pointer type. So integration function only packs FWs located in folder amd_blobs. And only FWs increase the table size. So the table size is only set once. Later calls only update the count and fletcher. The table has a header at least, so the size can not be 0. The fill_dir_header can take the parameter count as 0, such PSP level 1 only with ISH-A and ISH-B. It doesn't have any file type entries. This actually reverts https://review.coreboot.org/c/coreboot/+/78274 and adds other changes. TEST=Identical test on all AMD SOC platform Change-Id: I5dfbbb55912c8e37243c351427a8df89c12e5da8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81255 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-17util/lint/lint: Fix shellcheck errors in getopt support for darwinMartin Roth
Posix shell doesn't support '==' Change-Id: Icbdc4204f4c07d806e721fa39f96694c4df00e8d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81285 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-14util/nixshell: Add a dev shell for i386 archCrabtux
Add a Nix shell file to provide a simple environment for coreboot development of i386 architecture. Currently, this environment is capable of completing Tutorial Part 1 in https://doc.coreboot.org. The Nix shell can be used by running the following command: $ nix-shell --pure util/nixshell/devshell-i386.nix The `--pure` parameter is optional. In Nixpkgs, there is a package called 'coreboot-toolchain'. It fetches the source code of coreboot, build crossgcc, and export it as output. With the binary cache mechanism of Nix, crossgcc can be directly downloaded and used without compiling on user's machine. This Nix shell has been tested on a NixOS laptop and a Debian 12 server, and they both work fine. Change-Id: Idcfe10be214e9bca590a62b8a207267493a4861f Signed-off-by: Crabtux <crabtux@mail.ustc.edu.cn> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-13cbfs: Remove broken remnants of PAYLOAD_INFO featureJulius Werner
PAYLOAD_INFO is a very old feature that can add a key/value information section to a payload file. It seems to have only ever been generated by coreinfo and never really read by anything. Since CB:1721 in 2012, the feature has been inadvertently broken in practice since the `.note.pinfo` sections that contain the information get discarded from the payload before cbfstool gets to see them. Since CB:28647 in 2018, support for the section in the SELF loader was (inadvertently?) dropped, so if someone actually fed cbfstool a payload ELF that did have a `.note.pinfo` section, modern coreboot would refuse to boot the payload entirely (which is probably not a good state to leave things in). This patch removes the code to generate PAYLOAD_INFO entries entirely, but leaves the support to parse and extract those sections from old payloads in place in cbfstool. Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-13util/inteltool: Add support for Alder Lake-NBrandon Weeks
Reference: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2 (#759603) Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562 Signed-off-by: Brandon Weeks <me@brandonweeks.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-03-09util/docker/Makefile: Create Documentation/_build for docker-build-docsNicholas Chin
If the host directory of a bind mount does not exist, Docker will create it. However, the newly created directory will be owned by root due to the Docker service running within a root context. The docker command in the recipe for docker-build-docs binds Documentation/_build to /data-out within the container, so if it doesn't already exist, the documentation builder will be unable to copy the HTML output into /data-out since it runs with the same UID and GID as the host user. By creating, if necessary, the _build directory before the `docker run` command, there should always be an existing directory owned by the host user for docker to bind /data-out to (ignoring the case of an existing _build directory the current user does not have permission to write to), avoiding the issue where it cannot write the output. TEST: make -C util/docker docker-build-docs completes without issues with and without an existing Documentation/_build directory Change-Id: I6be9bc1fdca48f4d924f5c07cc261189ab6862fd Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81127 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-03-09util/smmstoretool: support processing ROMsSergii Dmytruk
Input file is parsed for FMAP and SMMSTORE region which is used if found. Otherwise, the whole file is assumed to be the region. Passing an image with FMAP that lacks SMMSTORER is an error. Change-Id: Ieab555d7bbcfa4dadf6a5070d1297acd737440fb Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09util: add smmstoretool for editing SMMSTORESergii Dmytruk
Offline SMMSTORE variable modification tool. Can be used to pre-configure ROM image or debug EFI state stored in a dump. Change-Id: I6c1c06f1d0c39c13b5be76a3070f09b715aca6e0 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-08drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 supportJeremy Compostella
Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-06amdfwtool: Change&Record the current table in integration functionZheng Bao
Align with the function integrating PSP FWs. And it is the integration function's responsibility. TEST=Identical test on all AMD platforms Change-Id: I1a98614f3a5756a462b01085e9565b52cf9a9343 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06amdfwtool: Move code related to getting options to a new fileZheng Bao
Cleanup the messy code. The code left in main is all about filling tables. To help to do this, 1. Some local variables are put into global struct. 2. Add some functions. Set some functions to global. TEST=Identical test on all AMD platforms Change-Id: Ia25c3fd5de7ae48054359f0f6551d91d7a4f6828 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-06amdfwtool: Set the table size for L1 separatelyZheng Bao
The space defined by size of the L1 table can not overlap with ISH header. For other cases, the size defines the directory and its content. The PSP spec does not say it quite clearly. This change is partly based on guess and can make extraction tool work so far. Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-03-05mb/emulation/qemu-riscv: Change to -bios optionMaximilian Brune
This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-04amdfwtool: Move the functions to handle_file.cZheng Bao
Change-Id: I4cfec13cbc2a86dc352758541cce915a838e0d0f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78305 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04amdfwtool: Remove the function's dependency to ctxZheng Bao
This is for next CL to move the write_body to another source, handle_file.c. https://review.coreboot.org/c/coreboot/+/78305 Removing amdfwtool_cleanup in write_body will not change the result. Write_body returns to main and amdfwtool_cleanup still ends up getting called. Change-Id: I639828498fa45911f430500735e90ddc198b6af5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78304 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-02lint: Make lint work on DarwinStefan Reinauer
Darwin's getopt does not support the same parameters as the util-linux version and so it is not possible to commit any changes because lint fails. Change-Id: Ife26083d2de080af9ed3d509945720051ca14bd7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80436 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29amdfwtool: Use Makefile.mk for Makefile settingsMartin Roth
When updating the Makefiles, to keep from having to update two files at the same time, import Makefile.mk into the external Makefile. This allows the bulk of the settings to be in a single location. While I'm here, I adjusted the print statements to match the rest of coreboot. Change-Id: Id5b869f49b34b22e6a02fc086e7b42975141a87e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-26docker/coreboot-sdk: Add mesonArthur Heymans
This is needed to build opensil. With meson and ninja added to the coreboot-sdk image there is no need have them in the jenkins node image. Change-Id: I36188ae895f2a770f1dc4528f332c09bf386db73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-26util/amdfwtool: build amdfwtool only for all tools or AMD CPUsMartin Roth
When we're building non-AMD processors, don't bother building amdfwtool unless we're specifically building all of the tools like for abuild. Change-Id: I9021674a06d65a79e24020790d317ab947c505fe Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80714 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-24crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3Elyes Haouas
Change-Id: I17758e23da25d610a0b462dfd388c53b89315242 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-22riscv/mb/qemu: fix qemu invocation commentPhilipp Hug
Change-Id: I773fb39801f180fead584942dfb385fcde9d2680 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80262 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-02-20util/crossgcc: Update LLVM from 16.0.6 to 17.0.6Felix Singer
Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20crossgcc: Upgrade binutils from 2.41 to 2.42Elyes Haouas
Change-Id: I6e9b2dac6fed702e8e353290971699cb9ee05dfc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-19util/liveiso/nixos: Install lm_sensors packageFelix Singer
Change-Id: I6b027ed39d3ee81878e069142c2d7212f3dc0a6f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
2024-02-18cbfstool: Support 64bit addresses for flat imagesPatrick Georgi
SELF has the fields wired up for 64bit, but adding flat images cuts the upper half. Change-Id: I3b48b8face921e942fb0e01eace791ad3e1669a0 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80576 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18util/crossgcc/buildgcc: Compile RISC-V GCC with medanyMaximilian Brune
currently the HiFive Unmatched mainboard produces the following error: ``` util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a (_clzsi2.o): in function `__clzdi2': util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in .rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/ rv64imafdc/lp64d/libgcc.a(_clz.o) ``` This is due to the fact that the libgcc.a library is compiled with the medlow code model but the mainboards are compiled with the medany code model. Changing the code model of the GCC libraries to the medany code model fixes the issue. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18util/cbfstool/linux_trampoline: Support more e820 entriesPatrick Rudolph
Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866 "[PATCH] Increase number of e820 entries hard limit from 32 to 128" made in 2005 the number of e820 entries passed from the bootloader is 128. Use the boot protocol version to check for support of 128 entries and use them if necessary. Tested on IBM/SBP1: Fixes booting a Linux payload when more than 32 entries are present in the memory table, which can easily happen on a 4 socket platform. Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>