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2019-11-14lib/fmap: Add optional pre-RAM cacheJulius Werner
This patch adds an optional pre-RAM cache for the FMAP which most platforms should be able to use, complementing the recently added post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP about half a dozen times from flash in verstage, which will all be coalesced into a single read with this patch. It will also help future vboot improvements since when FMAP reads become "free" vboot doesn't need to keep track of so much information separately. In order to make sure we have a single, well-defined point where the new cache is first initialized, eliminate the build-time hardcoding of the CBFS section offsets, so that all CBFS accesses explicitly read the FMAP. Add FMAP_CACHEs to all platforms that can afford it (other than the RISC-V things where I have no idea how they work), trying to take the space from things that look like they were oversized anyway (pre-RAM consoles and CBFS caches). Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-12util/autoport: Stop generate empty h8_mainboard_init_dock().Bill XIE
CB:36385 makes dock init in ramstage fully mainboard-specific, so keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes unnecessary and problematic. Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-06util/lint/kconfig_lint: Handle glob prefix and suffixArthur Heymans
Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-04cpu/qemu-x86: Add x86_64 bootblock supportPatrick Rudolph
Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-31util/ifdtool: Add Tigerlake platform support under IFDv2Ravi Sarawadi
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I3f9672053dcf0a4462ef6ab718af4f18fcfa7e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-10-30automation: add GPIOs and version number, change branch namePaul Fagerburg
* Add defines for GPIO_MEM_CONFIG_0:3 in the template file, so that code that relies on these defines can compile. Because they are preprocessor symbols, there is no way to define them as __weak in the baseboard header and allow the variant to override as needed, so they need to be defined here and changed if needed. * Add a version number for the script and an "auto-generated by" line in the git commit message. * Change the branch name so that it's not the same as the ones that the other scripts will create, so that repo upload on those CLs won't affect this one. BUG=b:140261109 BRANCH=None TEST=Create and build the "sushi" variant: $ util/mainboard/google/hatch/create_coreboot_variant.sh sushi $ util/abuild/abuild -p none -t google/hatch -x -a Prior to this CL, you would get an error message that SPD_SOURCES is not set. If you fixed that, then you would get failures for GPIO_MEM_CONFIG_0, _1, _2, and _3 not defined, and/or gpio_table[] and early_gpio_table[] not defined. After the CL, the build proceeds. Change-Id: I0f48d6bb9544cad6d419d3a6fbb17f57200938b2 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36408 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28inteltool: Add method 'print_system_info'Felix Singer
To get a better idea what this code does, this patch adds a new method called 'print_system_info'. Change-Id: I16f1c9cdc402b1a816fac65d1490432e39c07baf Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36315 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27buildgcc: ACPICA: build more utilities and in parallelStefan Reinauer
- honor $JOBS in build_IASL - Build the following utilities in addition to iasl for easier debugging of ACPI issues: * acpibin * acpidump * acpiexec * acpihelp * acpinames * acpisrc * acpixtract Change-Id: I84476da8f9a5ba4860ba4ad0220ec3efb229cc03 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36337 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26util/crossgcc/patches: facilitate successful build of ipxeHimanshu Sahdev
New changes in the latest binutils 2.32 lead to assembler errors causes ipxe build failure. IPXE uses the divide test which requires /dev/null as input as well as the output file name. This patch facilitates the /dev/null as an exception to the current changes in binutils package while building crossgcc for coreboot leads to successful build of ipxe and further tests to pass based on /dev/null and applies automatically during the crossgcc rebuild. Also, this can be reverted once binutils/ipxe provides an updated release in this respect. Fixes: https://ticket.coreboot.org/issues/204 Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35098 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22util/inteltool: Add server 5065x CPU model supportMaxim Polyakov
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky Lake, Cascade Lake, Cooper Lake). The cores number for these processors exceeds the limit of 8 cores (it is hardcoded in cpu.c). For this reason, the patch also adds code that determines the number of processor cores at run time. These changes are in accordance with the documentation: [*] pages: 2-265 ... 2-286, 2-297 ... 2-308. Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2019-10-22util/chromeos: Don't hide error outputNico Huber
Change-Id: Idf29275575ca7965a0df98dbc8f2b27ab9c5ec4d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-10-20util/amdfwtool: Add holding locations for more APCBsMarshall Dawson
Increase the number of potential APCB images to 5 by adding to the amd_bios_table. New instance IDs are from 0 to 4. The backup APCB block (type 0x68) still supports only instance ID 0. Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-19util/ifdtool: Add support for setting flash density on IFD V2Arthur Heymans
Change-Id: Ibc3e4c197f99f99007cb208cf6cc4ae6f56be70c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-18util/cbfstool: Add optional argument ibbPhilipp Deppenwiese
* Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17util/abuild: Have abuild generate the .xcompile if it doesn't existRaul E Rangel
Previously if .xcompile was missing, abuild would silently ignore the error. With https://review.coreboot.org/c/coreboot/+/34241 we now check the return code so abuild started failing. We should generate the .xcompile if it doesn't exist. The Makefile will handle that so we include it as the first Makefile. We then need to override the default target so we don't use the one from the Makefile. BUG=b:112267918 TEST=ran abuild and made sure it generated a .xcompile in the root. Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-16util/ifdtool: Fix argument parsing for layout/validateSamuel Holland
When `mode_validate` was added, a second copy of `mode_layout` was accidentally added to the multiple-mode-argument check instead. This prevents `-f` from working. Fix the check to reference the correct variable. Change-Id: Ibac6f090550ff63ec9158355b0450da204a300a7 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-16util/amdfwtool: Grow the Embedded Firmware StructureMarshall Dawson
Ensure adequate space exists for all Embedded Firmware Structure fields. Field definitions are NDA only. See PID #55758 "AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors". BUG=b:141790457 TEST=run on Mandolin Change-Id: I098ffc7c05d27387a877e6b7c8628d98939bd9af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35667 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-12util/inteltool: remove unsupported MSRs for 06_9EHMaxim Polyakov
Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12util/inteltool: fix 6d0H-6dfH MSR names for 06_9EHMaxim Polyakov
Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addrMaxim Polyakov
According to the documentation [1], IA32_PLATFORM_ID MSR register address should be 17H. [1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s Manual. Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12util/inteltool: remove duplicate MSR for 06_9EHMaxim Polyakov
Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-05util/sconfig: Issue header for exposed PCI and PNP namesNico Huber
Let `sconfig` output a C header file with the symbol names that we generate since 5e2a2cd5e7 (util/sconfig: Expose usable PCI and PNP device names). We add another command line argument for the path to the header file. As the file is similar in nature to our `config.h` we simply put it in $(obj)/ too. Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-03ifdtool: Add validate option to ifdtoolMathew King
Add an option to ifdtool which validates that the flash regions defined in the descriptor match the coresponding areas in the FMAP. BUG=chromium:992215 TEST=Ran 'ifdtool -t' with a good bios image and verify no issues run 'ifdtool -t' with a bad bios image and verify expected issues Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03util/release: add gerrit stats scriptMartin Roth
This tool downloads, caches and analyzes commits pushed to gerrit for a specified range of commits. Currently it only works over SSH. Data that is printed about the range of commits: CSV Data about each individual commit: - Commit ID - Commit Date - Author - Commiter - Submitter - Lines added - Lines removed - Title - Reviewers It then prints the analysis it did on the data: - Total Commits - Total lines added - Total lines removed - Total difference - Authors - Number of commits - Total Authors - Authors - Lines added - Authors - Lines removed - Reviewers - Number of patches reviewed - Submitters - Number of patches submitted The script relies on a number of perl modules which must be installed separately. Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/14225 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03buildgcc: Run aclocal before configureStefan Reinauer
Ubuntu 19.04 will fail looking for aclocal-1.15 if the scripts are not regenerated because 19.04 ships with 1.16. There are not enough eyes to roll when working with GNU autotools. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03util/crossgcc: Add patch for __alloca missing on ubuntu 18.04Martin Roth
Bring this over from the HEADS repo. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-09-30util/mb/google/hatch: update CRC calculation for correctnessPaul Fagerburg
The CRC result is treated as a signed value, and so in certain situations, the calculated value for the last four digits will not be correct. Ensure that the CRC is treated as an unsigned 32-bit value prior to converting the last 4 decimal digits to a string. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I92f9ce1ceb7450f90b89c94e0ace6f79a9419b42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35604 Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30util/mb/google/hatch: script can take optional bug parameterPaul Fagerburg
When creating a new variant, adding a bug parameter after the name of the variant will populate the BUG= field in the commit message. If the parameter is not present, then BUG=None. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I3e08df5d80a5684c9f3675e3c0a8346240171cd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-30util/mb/google/hatch: fix style issues in shell scriptPaul Fagerburg
* Use all caps for variables. * Use a single exit code for failures. * No need to popd before exiting the script. * Do ${var,,} and ${var^^} into variables instead of using it everywhere. * Add more punctuation in comments. * Specify LC_ALL=C so that upper/lower case show the desired behavior. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I63aa0aa633f36b9543e809fc42fac955da5960a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-30vboot: create board-specific test-only GBB HWID if not setHung-Te Lin
The HWID in vboot GBB is an identifier for machine model. On Chrome OS, that should be provisioned in manufacturing process (by collecting real hardware information), and will be checked in system startup. For bring up developers, they usually prefer to generate a test-only string for HWID. However that format was not well documented and cause problems. Further more, most Chromebooks are using HWID v3+ today while the test-only HWID is usually v2. Non-Chrome OS developers may also prefer their own format. To simplify development process, the GBB_CONFIG now defaults to empty string, and will be replaced by a board-specific test-only v2 HWID automatically. Developers can still override that in mainboard Kconfig if they prefer v3 or other arbitrary format. BUG=b:140067412 TEST=Built 'kukui' successfully. Removed kukui GBB config and built again, still seeing correct test HWID. Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30util/chromeos: revise description for more utility scripts in futureHung-Te Lin
The description.md and README.md was explicitly made for downloading or extracting some resources, but we need to add more Chrome OS related scripts soon; so the description should be revised. Also changed README.md for better markdown style, for example - Use #, ## to replace the old '-' headers - Use code format for file names - Use code block for example of shell execution Change-Id: Icc3677fa318b03f4aee1b0f5fb13b2095f2afe64 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-28superiotool: add basic support for SCH5545Alexander Couzens
Based on the SCH5627 datasheet which is similiar SCH5545 id 0xc4, SCH5627 id 0xc6. Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25util/mainboard/google: Fix hatch variant scriptEdward O'Callaghan
The script had a couple of bugs: * It didn't create the required directory under variants/ * It was treating the wildcard as literal and so couldn't find variant files to copy. V.2: Drop verbose cp && fixup wild card usage. Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7 Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-09-25util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMETLAKEFurquan Shaikh
Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig, utility to create a new variant does not need to do that anymore in Kconfig.name Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-19util/lint: make clang-format non-fatalAngel Pons
The current clang-format configuration is completely broken. It forces one to change the code style of patches before pushing them, only to find out that checkpatch now complains about it. This means newcomers get scared away, and developers only get angered and frustrated about it, and end up working around clang-format's requirements anyway. For now, make clang-format's complaints non-fatal, reducing them to text noise. However, since clang-format is currently unusable, reverting it out would be preferred. Change-Id: Iffa8934efa1c27c04e10545f66d8f9976e74c367 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-19hatch: automate creating a new variant in corebootPaul Fagerburg
To create a new variant of the hatch baseboard, we need to add the variant's GBB_HWID and other information to Kconfig and Kconfig.name, and set up a skeletal build based on the hatch baseboard. BUG=b:140261109 BRANCH=none TEST=``./create_coreboot_variant.sh sushi && git show`` Kconfig will have three new lines for the SUSHI variant, and Kconfig.name will have an entirely new section. New files created are: variants/sushi/Makefile.inc variants/sushi/overridetree.cb variants/sushi/include/ec.h variants/sushi/include/gpio.h variants/sushi/include/variant/acpi/dptf.asl Also run the script with an existing board name to verify that you can't create a variant that already exists. Change-Id: I1a5b9c8735faafebb2e4e384cb3346867d64c556 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-15util/inteltool: Add Intel HD 4400 (Haswell IGD)Sellerie
Add the 8086:041e integrated graphics controller. Adding the definition makes the Intel HD 4400 graphics recognized by inteltool. It is found on the ark page of e.g. the Intel i3-4130 CPU. Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588 Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11futility: Use HOSTPKGCONFIG for host PKG_CONFIGManoj Gupta
futility is built for the host. However, when cross-compiling, the target's pkg-config is called to get the library paths which can add paths from the cross-compilation tree instead of host. e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config . /build/elm/usr/bin/pkg-config adds the paths specific to the cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib. This causes linker to complain that files in library paths do not match the architecture. BFD produces a warning while LLD errors out. Fix this by passing PKG_CONFIG from host when building futility. BUG=chromium:999217 TEST=coreboot builds BRANCH=None Cq-Depend: chromium:1778519 Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35316 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10crossgcc: Upgrade CMake to 3.15.3Elyes HAOUAS
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html Change-Id: Id3283b4a091a5a8afd76235059636bba1c238f0f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-06util/sconfig: Expose usable PCI and PNP device namesKyösti Mälkki
These devices can be accessed directly by symbolname, without a search and walk through the tree, as they have static paths. Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31933 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-05inteltool: Add Skylake Xeon E DMI3 Host bridge IdMaxim Polyakov
Tested on Intel S2600WF and SUPERMICRO MBD-X11DPL-I-O Change-Id: I4b429536fc2db16d770120487e4c383da437593a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05inteltool: add Lewisburg C62x GPIOs supportMaxim Polyakov
These changes are in accordance with the documentation: [*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-04inteltool: add Lewisburg family C62x chipset PCI IDsMaxim Polyakov
These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30Kconfig: Write tmp files into same directory as target filesRaul E Rangel
This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the original files will be replaced with the tmp file, the parent directory already needs to be writable. Before this change, the tmp files would be created in the CWD (src) if COREBOOT_BUILD_DIR was not specified. BUG=b:112267918 TEST=emerge-grunt coreboot and verified no tmp files were created in the src directory. Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34244 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30kconfig: Use config's full path when generating tmp fileRaul E Rangel
If KCONFIG_CONFIG is set to a full path, we should generate the tmp file in the same directory instead of the current working directory. BUG=b:112267918 TEST=emerge-grunt coreboot and verified with print statements that the correct path was used. Change-Id: Ia21e930a9b0a693f851c34bcde26b34886cbe902 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28Makefile: Pass .xcompile into genbuild_hRaul E Rangel
I'm moving the .xcompile file into the $(obj) directory so we can leave the source pristine. We need to pass the location of .xcompile into genbuild_h.sh. BUG=b:112267918 TEST=Ran genbuild_h with and without an .xcompile and verified it was passed. Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28what-jenkins-does: Use abuild's -Z optionPatrick Georgi
This reduces disk usage during builds by removing all object files and other intermediate files directly after a build instead of waiting for the entire build to pass. Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35112 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28abuild: Add -Z / --clean-somewhat optionPatrick Georgi
This option removes everything in the build tree but coreboot.rom, config.build, config.h and make.log - a useful subset of the tree for further testing. Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35136 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26what-jenkins-does: keep essential artifacts aroundsPatrick Georgi
Keep for every board: coreboot.rom, config.h, config.build That way these can be used in follow-up jobs. Change-Id: I5ca5cb84ab1bcffbc92a972980cd0769ebf02462 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-20mb,autoport: Fix GCC 9 Port_List build errorJacob Garber
Port_List is an array of 8 elements, and GCC 9 is warning that there are no 'others' when all 8 elements are explicitly initialized, which is causing the build to fail. Remove the 'others => Disabled' clause to silence this. Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20util/nvidia/cbootimage: Update to upstream masterJacob Garber
This brings in 4 new commits from the upstream repository. 65a6d94 Free image buffer on read error 9de64c7 Fix various abort(), crashes, and memory errors 7c9db58 Bump to version 1.8 3b3c3cc Use C99 uintXX_t instead of implementation-specific u_intXX_t types Change-Id: If949309a7481537de6529c205fe745d5509906a9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20util/cbfstool: Remove unused assignmentJacob Garber
This variable is overwritten on one branch of the next if statement, and the other branch returns, so this assignment does nothing. Change-Id: I63737929d47c882bbcf637182bc8bf73c19daa9f Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-19util/superiotool: add IT8987 detection and register supportMatt Parnell
Signed-off-by: Matt Parnell <mparnell@gmail.com> Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/34888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-08-08util/abuild: Clean up the missing_arches checkRaul E Rangel
This change adds the following improvements: * Easier to read. * Checks to see if .xcompile is complete. * Checks the make return code. This will catch if .xcompile is missing. BUG=b:112267918 TEST=Modified my .xcompile and ran abuild and verified that missing_arches got set correctly. Also deleted .xcompile and verified there was a failure. Change-Id: I7604d431f398fc0c80a857a0c7c21e164004cc99 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-05util/arm_boot_tools/mksunxiboot: Remove toolArthur Heymans
Support for allwinner sunxi was dropped. Change-Id: I0d4cbcac3e96e381185338455a773bcccc3401ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34688 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03util/nvidia: Change ENODATA to ENOATTR for FreeBSDMartin Roth
FreeBSD doesn't have ENODATA defined, so the cbootimage utility wouldn't build. It looks like the BSDs use ENOATTR in the same fashion, so update the error to use that. Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-08-03util/abuild: Use realpath for FAILED_BOARDS/PASSED_BOARDSRaul E Rangel
The abuild script will `cd` into the build directory. FAILED_BOARDS defaults to a relative path, so it ends up trying to echo into a directory that doesn't exist. If we set the realpath to the file then we can correctly update the failed/passed boards file. BUG=none TEST=make what-jenkins-does and verified there was a failed_boards and passed_boards in coreboot-builds. Change-Id: Ib3af003b090668380a9425583a9f4367023820a6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-31inteltool: Add GPIO support for Skylake-H chipsetsFelix Singer
PCH IDs: - H170, Z170, Q170, Q150, C232, QM170, HM170 Used documents: - Intel 332690-005EN Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31util/release/genrelnotes: Emit more markdown-ish outputPatrick Georgi
It's better to format lists with bullet points. Change-Id: I503ef2dea9146d67c220236b8a5b64c2ba2d794f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34504 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31util/release: Make sure intel-microcode ends up in the blobs tarballPatrick Georgi
Change-Id: Ib41c196cf543070e237d240cf31e019c9b2bf339 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34503 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29util/inteltool: Add H110 GPIO supportPavel Sayekat
Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29util/amdfwtool: Correct fletcher32 algorithmMarshall Dawson
Change the fletcher32 checksum calculation to match PSP and AGESA implementations. The symptom of the failure has only been noted in Picasso's BIOS Directory Table, when a BIOS binary image of different sizes were passed to amdfwtool. The PSP halts the boot process with the bad BDT checksum, and if allowed to continue, AGESA asserts later due to a failed BDT verification. This version has been verified to produce the same result as found at https://en.wikipedia.org/wiki/Fletcher%27s_checksum. TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom is unchanged. Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-28util/abuild: Add asserts flag to getoptsMartin Roth
We recently added the --asserts option to set asserts as fatal in abuild but didn't add the flag to getopts, so it gets rejected as an invalid argument. Change-Id: Ic70e9a2bec039955cf62c175875598773ade2d3d Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-26util/testing: Allow adding abuild options to what-jenkins-doesPatrick Georgi
JENKINS_ABUILD_OPT is passed in abuild's command line Change-Id: I5e7fbb77a3c6592a4414a6c1e3f7556c7e3a824c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26util/abuild: Add --asserts flagPatrick Georgi
This enables fatal asserts, which can be useful to get better diagnostics by the build tools (both compilers and static analysis.) Change-Id: I1e1653f465fe1f545878d6eec83b8645dc17d9cb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26util/testing: Factor out abuild options in what-jenkins-doesPatrick Georgi
The abuild command line can vary a lot depending on options and the line became unwieldy (plus, it's on two lines because we run abuild twice), so factor it out into a variable. Change-Id: I102756fb95c93f542d534610bf9737a13ac1ad62 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-25xcompile: Store XGCCPATHNico Huber
It can be useful to pass along to external projects, e.g. payloads. Change-Id: I61c7bb162e2737a562cbef08b32ebbafd9cf1cb0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25crossgcc: Add nasm to toolchainMartin Roth
Tianocore payload uses nasm. Supply it in the coreboot toolchain instead of relying on system version. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33024 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade CMake to 3.15.0Elyes HAOUAS
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33053 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade acpica to version 20190703Elyes HAOUAS
Changes: https://acpica.org/node/171 Change-Id: I3883718623e4a23a901a446f738a9e8c988d8433 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25crossgcc: Upgrade Expat to version 2.2.7Elyes HAOUAS
Change-Id: If3611494228a9228b0b323038ba1e884a1bde10f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33825 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade Python to version 3.7.4Elyes HAOUAS
Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32077 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25crossgcc: Upgrade GDB to version 8.3Elyes HAOUAS
Change-Id: I7a85ad171fa259e0dcb0019941d735ef41511737 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32754 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23util/*/Makefile: Rename -W to -WextraJacob Garber
-W is the old name for -Wextra, so let's rename it to be consistent with the rest of the utility Makefiles. Change-Id: I0e50f13d2617b785d343707fc895516574164562 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-21util/cbfstool/flashmap: Fix memory leaks on failureJacob Garber
Fix several memory leaks on failed printing or tests. These don't matter much, but it keeps Coverity happy. Change-Id: Ie750acb50ae1590c3aea533338a8827c03459c1a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 130245{1,2,3} Reviewed-on: https://review.coreboot.org/c/coreboot/+/34412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-17device: Move pci_irqs outside DEVTREE_EARLYKyösti Mälkki
Only needed in ramstage, and only for MP tables. Change-Id: Ia7c1e153b948aeefa4c3bea4920b02a91a417096 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33922 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16util/inteltool: Shrink buffer sizeJacob Garber
512 bytes is much too big for this buffer, which only needs to hold a path that will have a length of at most 20. The large buffer size also triggers a -Wformat-truncation warning with GCC since it is later printed into the smaller temp_string array, so shrink it down to something reasonable. Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-15util/amdfwtool: Add option to build verstage binary into the PSPMartin Roth
For AMD's Family17h processors, verstage needs to be run in the PSP, before memory is initialized. This adds that binary into the PSP directory. See the Family17h documentation in the coreboot documentation directory for more information. BUG=b:137338769 TEST=Build, add test binary to mandolin board, boot Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15util/amdfwtool: Do misc cleanupMartin Roth
- Correct command line argument for microcode patches from -u to -O - Add #if PSP_COMBO around new_combo_dir() as it's only called when that's enabled. - Remove unused variable in integrate_bios_firmwares() - Correct enum type from amd_fw_type to amd_bios_type in register_fw_addr() Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-13util/testing: Ensure coreboot-gerrit fails if libpayload build failsKeith Short
The JUnit output from the libpayload builds was getting deleted by the coreinfo build. Move the libpayload to later in the coreboot-gerrit job. Also add messages to stdout indicating the various libpayload configs that are built and a message indicating when all libpayload builds are complete. BUG=b:137380189 TEST=Upload test commit that includes a libpayload compile error and verify buildbot fails. Change-Id: I43b55f402216582dcf81be34171437be345572ab Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12util/superiotool/aspeed: fix SUART numberMaxim Polyakov
Change-Id: I20c4436d414bc6b9a3ff5138d6fd59ead8fd4a47 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-12util/sconfig: Fix compile error with older glibc-headersWerner Zeh
In patch e29a6ac16a9f478fc00ce7cb83f3779954e3168d (util/sconfig: Add commonlib/helpers.h) helpers.h has been added to the include-list. In headers.h we have a definition for __unused: On a host system environment where glibc-headers-2.12-1.212 is installed, a file included by <sys/stat.h> called bits/stat.h have the following content on line 105 and onwards: long int __unused[3]; where the mentioned part is part of the structure called struct stat. If we include commonlib/helpers.h _before_ <sys/stat.h>, the symbol for __unused will be defined by the preprocessor to be '__attribute__((unused))', therefore the above mentioned structure member will be expanded by the preprocessor to be 'long int __attribute__((unused))[3];', which is not a valid C syntax and therefore produces a compile error for sconfig tool. To handle this case we need to make sure commonlib/helpers.h is included _after_ <sys/stat.h>. As the needed part of stat.h (which is struct stat) is only used in main.c it is safe to move the include from sconfig.h directly into main.c while taking care of the order. Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10util/amdfwtool: Close file descriptor on errorJacob Garber
Prevents a resource leak. Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10util/romcc: Correct format specifiersJacob Garber
The right specifier for printing ptrdiff_t is %td. Change-Id: I7bae4d47f15cfe85ca870f687c6f702339f680bb Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 14021{64,68,76} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10util/cbfstool: Close file on errorJacob Garber
Prevents a resource leak. Change-Id: I032227228c8e37e989960ad6292ded39b81835a9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1383919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10util/sconfig: Add commonlib/helpers.hKyösti Mälkki
Followup work injects ARRAY_SIZE() in static.c Change-Id: Ifbcaa1b613aef312d3876e8b536499a9f01a8d19 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-10util/sconfig: Declare the repeated devicetree storageKyösti Mälkki
With DEVTREE_EARLY we could create incomplete device objects with topology links removed to reduce footprint for bootblock. Declare everything with 'static __unused DEVTREE_CONST' to avoid compiler errors and to not expose unusable device object names to global scope. Change-Id: Ie4cb9e75f179f44edf4f8256ad8320bc2d4ae71a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-09crossgcc: Fix runtime initialization of a constantNico Huber
GNAT had a constant initialized at runtime which led to trouble with compilers that decided to place it into an actual constant section (e.g. GCC 9). Usually, this would be handled gracefully if the Ada compiler knew about the runtime initialization. How- ever, as the initialization was done by taking the address of the variable, the compiler had no clue. Change-Id: I73ce4cadc612c814ed2e22b44f429af2ad3db288 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34147 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08util/superiotool: Add AST2400Patrick Rudolph
Add support for AST2400 Super I/O. The device doesn't have an ID register, so probe for scratch register not to read as 0xff. Tested on platform which has an AST2400. Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-07util/cbfstool: Prevent overflow of 16 bit multiplicationsJacob Garber
Considering the following integer multiplication: u64 = u16 * u16 What on earth, one might wonder, is the problem with this? Well, due to C's unfortunately abstruse integer semantics, both u16's are implicitly converted to int before the multiplication, which cannot hold all possible values of a u16 * u16. Even worse, after overflow the intermediate result will be a negative number, which during the conversion to a u64 will be sign-extended to a huge integer. Not good. The solution is to manually cast one of the u16 to a u32 or u64, which are large enough to not have any overflow and will prevent the implicit conversion. The type of the u64 is preferred, though a u32 is used instead of size_t, since that can change depending on the platform. Change-Id: I5391221d46d620d0e5bd629e2f9680be7a53342e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 12297{03,04,05,06,07,08,09,10} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07util/nvramtool: Mark out_of_memory() as noreturnJacob Garber
This silences several false positives from scan-build. Change-Id: I327a967c75d6aeec0b3aba16ee696dbae8cf997d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07util/nvramtool: Enable -Wmissing-prototypesJacob Garber
Change-Id: Id751250b07a495dc25293ff703602bfefa9011bd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07util/nvramtool: Make internal function staticJacob Garber
This function is only used in this file, so it can be made static. Change-Id: I90e673da91eb926424d1730c268860da7fa1627b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07util/nvramtool: Include missing headerJacob Garber
The prototype for is_ident() is in this header, so include it. Change-Id: I45e0d58d1b891b18b3eb7741897ab691188a2bd9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07util/inteltool: Enable -Wmissing-prototypesJacob Garber
Change-Id: I6bf041d089498780ea2b7c52402d7452d44d3f87 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33946 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07util/inteltool: Make internal functions staticJacob Garber
None of these functions are used outside of the files they are defined in, so they can all be static. Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-03util/cbfstool: Add AMD BIOS compression tool for PSPMarshall Dawson
Add a utility to generate a compressed BIOS image for AMD Family 17h. If the input is an elf file, the utility extracts the program portion for compression. Otherwise the file is compressed as-is. In modern AMD systems, the PSP brings up DRAM then uncompresses the BIOS image into memory prior to x86 beginning execution. The PSP supports a zlib engine, and interprets the first 256 bytes as a header, where offset 0x14 containing the uncompressed size. For further details, see AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:127766506 TEST=Use with WIP Picasso Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-07-02cbfstool: show "preserved" flag in cbfstool layout outputPatrick Georgi
The flag is useful for updaters to determine which areas to leave alone, such as VPD (vital product data) regions that are set in factory and might contain unique (MAC addresses) or hard to obtain (calibration output) data. It's also useful to see which regions are marked as such. Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02util/cbmem: Enable -Wmissing-prototypesJacob Garber
Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 08:04:52 +0000