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2018-05-18util/cbmem: Fix compare function for qsortFurquan Shaikh
compare_timestamp_entries will fail for entries that are different by at least 2^32 since entry_stamp is 64-bit and the return for compare is 32-bit. This change fixes compare_timestamps by actually comparing the entries to return 1, -1 or 0 instead of doing math on them. TEST=Verified that "cbmem -t" sorts entries correctly on previously failing entries. Change-Id: I67c3c4d1761715ecbf259935fabb22ce37c3966e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-18cbfstool: Drop `-t` parsing for `add-payload` commandNico Huber
It seems this was never used and the usage doesn't mention it either. Change-Id: I9240c0ed5453beff6ae46fae3748c68a0da30477 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26324 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-17util/abuild: Disable unspecified payload optionsMartin Roth
We have two payload options in abuild: "None" or a pointer to an elf file. This disables all other options in abuild, and makes disabling the other options common to both valid options. Change-Id: Icbd6fde4343ac1cff05778131f9e54370baf4224 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-16Revert "cbfs/payload type: Fix build warning and whitespace in name"Ronald G. Minnich
This reverts commit 717ba748366cda19b7532897a5b8d59fc2cd25d9. This breaks seabios and a few other payloads. This is not ready for use. Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/26310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-15cbfs/payload type: Fix build warning and whitespace in namePaul Menzel
Currently, adding a payload to CBFS using the build system, the warning below is shown. W: Unknown type 'payload' ignored Update payload type from "simple elf" to "simple_elf" and rename the word "payload" to "simple_elf" in all Makefiles. Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF) Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26240 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15msrtool: add VIA C7Lubomir Rintel
Change-Id: I67c4f579f898a709dde3fab6bab1474a721da770 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18258 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15util/msrtool: Check for VENDOR_AMD for K8 probeKyösti Mälkki
Change-Id: Icc3973dfc7217ca649fb4151ccdea5461a550bb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-15util/msrtool: Fix swapped IA32_MC3_x and IA32_MC4_xKyösti Mälkki
Registers IA32_MCi_xx are defined as architectural MSRs since "P6 Family Processors" and should have model-agnostic indexing. Note that in IA32 architecture manual, names of these MSRs are similarly swapped in the table of Intel Core Microarchitecture. I take this is an error in the documentation only, and it got copy-pasted across different CPU family files in the utility. Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26269 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15util/msrtool: Fix names from IA32_MCO_xx to IA32_MC0_xxKyösti Mälkki
Change-Id: I46cd986f4914b214156da49db37ecfa749386ce8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-15msrtool: use a bit more clever cpuid vendor matchLubomir Rintel
Not everything non-intel is AMD. Change-Id: I06d6fbaa0b4f2c9e61d9b3b4aeeb349a91aa090e Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18255 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-13cbmem: Sort timestamp entriesRaul E Rangel
If the timestamp entries are added out of order, the duration calculation will be wrong. AGESA collects timestamp data through all the stages. Then in AmdInitPost it asks for a buffer to write TP_Perf_STRUCT into. agesawrapper will then take the data and call timestamp_add on each entry. This results in the entries being out of order. TEST=Built firmware for grunt that manually added entries and then ran cbmem -t/-T to verify the entries were in the correct order. Change-Id: I6946a844b71d714141b3372e4c43807cfe3528ad Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26168 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-13msrtool: add support for printing string valuesLubomir Rintel
The VIA CPUs allow setting the CPUID vendor, which is best read as a character string. Change-Id: I67f77ca75f7d77e47b3ba09bad904df5805e373a Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-13mstrool: only use intel targets for actual intel CPUsLubomir Rintel
VIA c3 & C7 use the the family of 0x6 and model 10, but are not quite Pentium III. Change-Id: I85e9853b42cfd20db46db0bd244620d6813bc826 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18256 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11devicetree: Add USB device typeDuncan Laurie
This commit adds support for describing USB ports in devicetree.cb. It allows a USB port location to be described in the tree with configuration information, and ACPI code to be generated that provides this information to the OS. A new scan_usb_bus() is added that will scan bridges for devices so a tree of ports and hubs can be created. The device address is computed with a 'port type' and a 'port id' which is flexible for SOC to handle depending on their specific USB setup and allows USB2 and USB3 ports to be described separately. For example a board may have devices on two ports, one with a USB2 device and one with a USB3 device, both of which are connected to an xHCI controller with a root hub: xHCI | RootHub | | USB2[0] USB3[2] device pci 14.0 on chip drivers/usb/acpi register "name" = ""Root Hub"" device usb 0.0 on chip drivers/usb/acpi register "name" = ""USB 2.0 Port 0"" device usb 2.0 on end end chip drivers/usb/acpi register "name" = ""USB 3.0 Port 2"" device usb 3.2 on end end end end end Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09util/lint: Ignore whitespace, newlines, and licenses in vbt filesMartin Roth
Change-Id: I84f612db058d83936ddd5a6baa32c993e5b0f594 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09util/xcompile: prefer riscv64 over riscvPatrick Georgi
gcc 8.1 insists. Change-Id: I8cb00fafdfff7679e38f357c6e8968da656c351d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25995 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-05util/release/genrelnotes: Add "sifive" search patternJonathan Neuschäfer
Make sure that SiFive-related code is counted under RISC-V in the release notes. Change-Id: I3a74bb25ea66c98bc194adafd8267afeb42d7993 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25987 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELFPatrick Rudolph
In preparation of having FIT payloads, which aren't converted to simple ELF, rename the CBFS type payload to actually show the format the payload is encoded in. Another type CBFS_TYPE_FIT will be added to have two different payload formats. For now this is only a cosmetic change. Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-04ifdtool: Add a list of known platforms that support IFD_VERSION_2Furquan Shaikh
ifdtool has relied on one of the fields within FCBA(read_freq) to determine whether a platform supports IFD_VERSION_1 or IFD_VERSION_2. However, newer platforms like GLK and CNL do not have read_freq field in FCBA and so the value of these bits cannot be used as an indicator to distinguish IFD versions. In the long run, we need to re-write ifdtool to have a better mapping of SoC to IFD fields. But until that is done, this change adds a list of platforms that we know do not support read_freq field but still use IFD_VERSION_2. This change also updates GLK and CNL to pass in platform parameter to ifdtool. BUG=b:79109029, b:69270831 Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-03board_status: Remove sudo when checking for cbmem with commandMatthias Gazzari
I get the error below when using the following command in combination with sudo: sudo command -v $SOME_COMMAND sudo: command: command not found Detection of the cbmem path is working fine without sudo. Change-Id: I8788c190ffebde117e2abd3df924c48d8f6fd05d Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/25989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-30cbfstool: Add region offset information to layout commandWerner Zeh
The layout command prints all FMAP regions in the final image among with the region size. Extend this command to show the offset of each region in the image. Change-Id: I5f945ba046bd2f1cb50a93e90eb887f60c6fde8a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-29util/autoport: Improve `readme.me`Paul Menzel
Correct spelling mistakes and punctuation, and improve some wording. Change-Id: I2c976bd62d8fa508373747b3fb3cf31490d5f631 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-28util/intelmetool: Be explicit about *kernel* cmdline argumentsJonathan Neuschäfer
Reduce the potential for confusion. Change-Id: I1d5df9acb30948f786f4ced895bbaeed80153fdb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-28buildgcc: Add missing '\'Vivia Nikolaidou
That caused the CFLAGS, CXXFLAGS, and '|| touch .failed' to not be taken into account when building binutils. Change-Id: I94521eb73cefdc5ed01fbf10122966a54cc28166 Signed-off-by: Vivia Nikolaidou <vivia.nikolaidou@puri.sm> Reviewed-on: https://review.coreboot.org/25901 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27util/docker: Add docker container that builds the sphinx documentationPatrick Georgi
It's what we use on coreboot.org to update www.coreboot.org/Documentation Change-Id: I6e5457d2e39a10f14fabd68bbb231a05e2f66f1d Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/25869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27util/qualcomm: Add T32 debug scriptsT Michael Turney
T32 scripts that allow debug of any coreboot stage on sdm845 Change-Id: Ia1bcbe687ca7bba10dc04cb6689640b13a8453f5 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-27util/x86/x86_page_tables: add command line to generated filesAaron Durbin
In order to help the reader understand where things are generated from add a comment string that is composed of the command line used to generate the files. BUG=b:72728953 Change-Id: I1b93923f8b08192448ab19226fd27661cc09e853 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-26util/hugo: Drop support for hugo based documentationPatrick Georgi
We shouldn't have two of everything Change-Id: I9879b40e26ba5a98626bc14c3d273fb525c070f7 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/25870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-26src/sifive: Add the SiFive Freedom Unleashed 540 SoCJonathan Neuschäfer
The FU540 is the first RISC-V SoC with the necessary resources to run Linux (an external memory interface, MMU, etc). More information is available on SiFive's website: https://www.sifive.com/products/hifive-unleashed/ Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-25util/riscvtools: Rename to util/riscv/Jonathan Neuschäfer
There's no good reason to use the more complicated name. Change-Id: I515e2df3b87580ddd31d18fe63451a98e92ead61 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25700 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-23util/x86/x86_page_tables: add license header to generated codeAaron Durbin
If one wants to check in generated page tables in C then coreboot complains about there not being a license. Therefore, add the BSD license to the generated page tables. BUG=b:72728953 Change-Id: I980d7a7c0c14c1ed5aa8ce37a1484943a6a100f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23util/x86/x86_page_tables: update PAT mapping to match linuxAaron Durbin
The linux kernel uses the following mapping for PAT entries: PTE encoding: PAT |PCD ||PWT PAT ||| slot 000 0 WB : _PAGE_CACHE_MODE_WB 001 1 WC : _PAGE_CACHE_MODE_WC 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS 011 3 UC : _PAGE_CACHE_MODE_UC 100 4 WB : Reserved 101 5 WP : _PAGE_CACHE_MODE_WP 110 6 UC-: Reserved 111 7 WT : _PAGE_CACHE_MODE_WT Update the page table generator to match what the linux kernel is using. This just makes things consistent with linux. BUG=b:72728953 Change-Id: Ie5ddab5c86d4e03688d7e808fcae34ce954b64f9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-19ectool: Add an option to get and use EC ports from /proc/ioportsIru Cai
There are boards that don't use ports 0x62 and 0x66 for EC, e.g. Dell Latitude E6230 uses 0x930 and 0x934. Change-Id: Ie3005f5cd6e37206ef187267b0542efdeb26b3af Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-17Use git HTTP URLs without `/p` in itPaul Menzel
Change-Id: I9972b138c6dd2a289880c4ec8b3fe64fc3baa66b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25545 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16util/intelmetool: Add additional helpful error messagesPatrick Rudolph
Add more verbose error message for common problems on modern operating systems, like Secure Boot and CONFIG_STRICT_DEVMEM. Change-Id: Ie3361910d48271bcc2cd3b4b74937fbc5df0a176 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16util/intelmetool: Fix bootguard dumpPatrick Rudolph
* Fix broken bootguard report on Intel ME 9.5+ * Fix broken debug statement * Add additional rehide_me() * Move last rehide_me() Tested on Lenovo T470p. It shows correct BootGuard state: Verified & Measured Boot. Tested on Lenovo T430. It shows correct BootGuard state: Disabled. Change-Id: Ib6c49ee39dd9962a4981e7de19b1c98c753f2944 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16util/intelmetool: Add support for platforms without RCBAPatrick Rudolph
Only try to unhide MEI if the PCI device wasn't found and probe for RCBA before trying to use it. Allows to run the utility on Skylake and newer hardware that do not have RCBA any more. TODO: Use sideband interface to unhide MEI. Change-Id: I7926aa80b132d5be9fece0724516701d74dd4d3d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16util/intelmetool: Fix crash on strict devmem kernelsPatrick Rudolph
Don't crash if mapping MEI PCI memory fails. This can happen if CONFIG_STRICT_DEVMEM is enabled. Change-Id: I33c75a7cccb4cefaa26f70aed4bdc4bd620cdad0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16util/scripts: Add script to alphabetize MAINTAINERS filePaul Menzel
Copy script from Linux added in commit 7683e9e5 (Properly alphabetize MAINTAINERS file) by Linus Torvalds. > This adds a perl script to actually parse the MAINTAINERS file, clean > up some whitespace in it, warn about errors in it, and then properly > sort the end result. > > My perl-fu is atrocious, so the script has basically been created by > randomly putting various characters in a pile, mixing them around, and > then looking it the end result does anything interesting when used as > a perl script. Change-Id: I2eb4e3f9863d0fe242fb690f1121842c80d72d6a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/20742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16util/lint: Fix execution on OpenBSDPiotr Kubaj
util/lint/lint creates a file using mktemp. mktemp on OpenBSD requires at least 6 X's, while only 5 are in the template. Change-Id: I0b80214dd83d21e12e16a5002c68127a7ca2e41b Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> Reviewed-on: https://review.coreboot.org/19745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16nvramtool: Fix build with OpenBSDPiotr Kubaj
OpenBSD needs the same includes as NetBSD. It also doesn't have x86_64_iopl function, but amd64_iopl. Change-Id: I28273d4d87a3a77cf35412a0695325c0535e42e5 Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl> Reviewed-on: https://review.coreboot.org/19741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16autoport: add missing PCI IDsDan Elkouby
As seen on ASUS P8Z77-V Pro Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-11util/cbfstool: Print all supported architecturesJonathan Neuschäfer
The list of supported architectures in the usage output of cbfstool is currently hardcoded and outdated. Use the arch_names array in common.c to provide and up-to-date list. Change-Id: I3e7ed67c3bfd928b304c314fcc8e1bea35561662 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-11util/cbfstool: Print types on stdoutJonathan Neuschäfer
Currently, "cbfstool -h | less" doesn't show any file types under "TYPEs:". That's because the file types are printed with print_supported_filetypes, which uses LOG, which prints to stderr. Use printf print_supported_filetypes, and thus print to stdout, to make the usage output more normal. Change-Id: I800c9205c59383b63a640bc0798a1bd9117b0f99 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10util/board_status/to-wiki: Remove link to xivo's git treeJonathan Neuschäfer
coreboot doesn't support any Xivo boards, and their tree has been only available as a tarball for a while. Let's remove this link from the Supported Motherboards page's preamble. It's still listed on https://www.coreboot.org/Supported_Motherboards/old. Change-Id: I50e7bec02e803b62563f21384d857f1b37904dd1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10util/board_status/to-wiki: s/corebootv4/coreboot/Jonathan Neuschäfer
corebootv4 vs. just coreboot has lost its significance. Version 4.0 has been released in February 2010. Change-Id: Ic2a35739e53fea411efc8691f1ba7db85ba0c764 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-09crossgcc/Makefile: don't allow to call buildgcc in parallelAlexander Couzens
Change-Id: If296414f8cb3bc87862cdc20f3d3acc1a3f78556 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/21229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09util/lint: Generate json output from checkpatch outputNaresh G Solanki
checkpatch_json.py processes the output of checkpatch.pl & generates json format output of comments. This json format output can be used to post comment on particular CL using gerrit. BUG=None BRANCH=None TEST= Run following commands: 1. Capture output of checkpatch.pl to file say checkpatch.txt nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl --no-signoff -q - | tee checkpatch.txt 2. Generate json format file for the output. util/lint/checkpatch_json.py checkpatch.txt comment.json 3. Post the comment.json using gerrit ssh coreboot.org gerrit review -j "<CL number>,<patchset number>" < comment.json Change-Id: I2471792796ab8e7d9855a6559fc731345ebd1525 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/23429 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06docker/coreboot-sdk: Add device-tree-compilerPatrick Rudolph
Add dtc to Dockerimage for Jenkins. Change-Id: Ifa3608f0a83431e75fbd402385863cce06e249fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25525 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06util/me_cleaner: Update to v1.2Nicola Corna
Changelog: * Add support for the HAP/AltMeDisable bit * Add support for selective partition removal * Fix the ME permission removal on gen. 3 * Add public key match * Print the compressed size of the Huffman modules on gen. 2 * Wipe the ME6 Ignition firmware images * Fix the removal of the last partition on ME6 * Various region size fixes * Add manpage * Add setup.py * Print the value of the HAP/AltMeDisable bit The output image should be identical, except for the platforms affected by bugs (ME 6.x, but it's not supported by coreboot and ME 11.x with the -d option, but it's not being used in our build process). Overall, nothing should change when it's used with the CONFIG_USE_ME_CLEANER option. Tested on a Lenovo X220 and Sapphire Pure Platinum H61. Change-Id: I3d5e0d9af0a36cc7476a964cf753914c2f3df9d2 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-05intelmetool: Include <sys/io.h> for musl-libcIvan J
This allows compiling the program using musl-libc, since otherwise iopl(2) is undeclared. Change-Id: Ia27203cf47b9be3f7bf1ad422c8f490caeae8f56 Signed-off-by: Ivan J. <parazyd@dyne.org> Reviewed-on: https://review.coreboot.org/23834 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-27inteltool: Add some Skylake desktop idsNico Huber
Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/25144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-03-22util/ifdtool: Fix region access control for SKL/KBLFurquan Shaikh
The default values used by ifdtool for setting region access control do not match the expected values for SKL/KBL as per the SPI programming guide. This change adds platform "sklkbl" that sets region access control bits differently for SKL/KBL images. BUG=b:76098647 BRANCH=poppy TEST=Verified that the access control bits on KBL images is set correctly. Change-Id: I1328d8006c25be282b3223268d8f1fd0a64e2ed3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-15util/inteltool: Add missing #include <string.h>Nico Huber
Change-Id: I7bb142d9f936b73e84d301028069d85cc15d596a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/25143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-03-07util/x86: add page page table generatorAaron Durbin
Certain platforms need paging enabled during cache-as-ram because dirty lines are being evicted by a heavy speculative frontend. Paging needs to be enabled in order to utilize the NX (no execute) bit for the regions that are strictly data (such as the stack). This utility creates 32-bit PAE page tables using a static address space, and the resulting tables have entries for all the PDPTEs such that it makes it easy to enable 2MiB naturally aligned DRAM mappings once memory is trained. Either binary files can be generated or C files. The pages that are linked use a default base address of 0xaa000000 that can be changed at runtime to reflect where the page tables are actually loaded. Or specify a physical address on the command line that is known a priori. iomap.txt: 0xd0000000, 0x100000000, UC, NX # All of MMIO 0xff000000, 0x100000000, WP, # memory-mapped SPI 0xffff8000, 0x100000000, WP, # XIP bootblock 0xfef00000, 0xfefc0000, WB, NX # CAR 0xfef40000, 0xfefc0000, WB, # verstage 0xfef20000, 0xfefc0000, WB, # romstage 0xfef40000, 0xfefc0000, WB, # fsp-m $ go run util/x86/x86_page_tables.go --iomap_file=iomap.txt Merged address space: 00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small 00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small 00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small 00000000fefc0000 -- 00000000ff000000 UC NX : 0 big 64 small 00000000ff000000 -- 0000000100000000 WP : 8 big 0 small Total Pages of page tables: 5 Pages linked using base address of 0xaa000000. BUG=b:72728953 Change-Id: I47625a24979b196011e2293712a8cdbdbb880d79 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/24919 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06cbfstool: Add install target to MakefileDenis 'GNUtoo' Carikli
Change-Id: I5df7033e1e52c78e97cdbd26aef2d7824ea67f8b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/12403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22util/amdfwtool/amdfwtool.c: Check fstat returnRichard Spiegel
Funtion fstat will return -1 if there's any error, 0 if successful. Check that fstat return is equal to 0, print error message and exit if not 0. This fixes CIDs 1353018 and 1353020 BUG=b:72062481 TEST=Build no errors Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20util: make-spike-elf.sh: Fix busybox mktemp compatibilityJonathan Neuschäfer
Busybox mktemp does not support patterns with any characters after the XXXXXX part. Drop the .o extension to make make-spike-elf.sh work on Alpine Linux. Change-Id: I2e37ceef115c6d4d31eb617558481b2284dada83 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-19util/cbmem: Re-order regex for "cbmem -1"Furquan Shaikh
In case of console dump for only the last boot, cbmem utility checks for a list of regex in provided order. When pre-cbmem console overflows, "Pre-CBMEM <stage> console overflowed.. " message is added before "... <stage> starting" message. This change fixes the order of regex in cbmem utility to match this. Test=Verified on soraka that "cbmem -1" correctly dumps the data starting from Pre-CBMEM romstage overflowed. Change-Id: I9c5667bbd02ed3e93ac77a4f42e87d754a062919 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16board_status: Make board_status more friendly for local usageDavid Hendricks
board_status.sh was originally written for use cases where the DUT is remote, i.e. accessed via serial port or SSH. This lead to some issues when attempting to run the script on the DUT itself. This patch attempts to handle the local use case more gracefully. sudo is used when running the cbmem command, and the '-c' option can be used to set cbmem path in case it's not in the default path used by sudo. Change-Id: I62957678ccae65fc46fd6ddf5ae92983d36cffad Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/21566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16board_status: Don't fetch dmesg via SSH when run over serialDavid Hendricks
It doesn't make much sense to try and obtain dmesg via SSH if we're using the serial port. Serial should only be used to obtain dmesg if SSH is unavailable. Change-Id: Iec70e64666f9446cf7e98a0fbcaa1cd5cefd8898 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/21567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-10util/broadcom/secimage: Add distclean targetMartin Roth
When running 'make distclean' on coreboot, the build cleans the tools as well. Since secimage didn't have a distclean target, it gave an error that the distclean target didn't exist. This didn't actually affect anything more than the secimage clean, but it was impossible to tell that from the warning: % make distclean make[1]: *** No rule to make target 'distclean'. Stop. Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06util/broadcom/secimage: Add HMAC testAlex Thiessen
One of responsibilities of the `secimage` tool is signing the image using the HMAC-SHA256 algorithm. The test being added verifies that secimage's internal call yields same result as the according openssl tool does. Change-Id: I8de4328f435af56901a861e3d5e733657c3c7f78 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-06inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPIArthur Heymans
Tested to display the register content correctly on a Lenovo Thinkpad X220. Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-06inteltool: Fix displaying 64bit spi registersArthur Heymans
The registers were taken from the wrong addess since the spibar offset was not added to it. This also fixes the endianness. Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23478 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06nvramtool: Fix message when option table is not foundArthur Heymans
Having an option table pertains to CONFIG_USE_OPTION_TABLE. Change-Id: Ia8a84e3e59ee50444c7f7d17b34bea86ee475909 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-31util/docker/coreboot-sdk: Add libftdi1-devMartin Roth
chromeec uses libftdi1-dev, so add it to the image. Change-Id: I517e3f073062dcc6b0b8e3adaf7b0123290a1698 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-30autoport: Don't do writes to FD in romstageArthur Heymans
ff4025c5f "sb/intel/bd82x6x: Reduce function-disable mess" Removed most of the writes to RCBA(FD) and renamed the function to mainboard_rcba_config. Writes to FD are properly handled in ramstage, so no need to do it in romstage. Change-Id: I4edb75569ceec2d2f1308755a66d286202ca0ae6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-01-29util/lint/checkpatch.pl: Untaint filenameMartin Roth
This fixes the warning that is seen on the jenkins server: Insecure dependency in piped open while running setgid at util/lint/checkpatch.pl line 958. Change-Id: I476efa76ef6a275584a47ec0ecf2315948d53e9d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-26util/lint: Apply `final newlines` check to scriptsAlex Thiessen
The `lint-extended-015-final-newlines` script skips over executable files and thus leaves script files unchecked. Use `file` to find scripts and include them in the `final newlines` checks. Whitelisting is used including bash, perl, python and sh scripts. Change-Id: I8649b261b7e2cbbac7f9b90a9ace3f1c7b0eedeb Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23325 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25sconfig: Add a new mmio resource typeJustin TerAvest
Add support for a mmio resource in the devicetree to allow memory-mapped IO addresses to be assigned to given values. AMD platforms perform a significant amount of configuration through these MMIO addresses, including I2C bus configuration. BUG=b:72121803 Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24util/docker/coreboot-sdk: Add msitools & rsyncMartin Roth
- The em100 project needs msitools. - Flashrom uses rsync. Change-Id: Ie01064adede25471a860bc22c0a59b31202b56c2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24util/amdfwtool/amdfwtool.c: Verify it actually read bytesRichard Spiegel
The function read() returns the number of bytes actually read. Program is assuming it actually read the required number of bytes without checking. This is wrong. This fixes CIDs 1353019 and 1353021 BUG=b:72062481 TEST=Build no errors Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23util/amdfwtool/amdfwtool.c: Check for negative returnRichard Spiegel
File open function <open()> will return -1 if there's any error. Check that the return is greater or equal to 0 before using fstat(). Print error message and exit if there's an error. This fixes CIDs 1353018, 1353020, 1353027 and 1353028 BUG=b:72062481 TEST=Build no errors Change-Id: I77d6973d1ad1eadb93922866e618038045be5937 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23util/lint: Unify checks for git worktreeAlex Thiessen
Linters try to determine whether they are running in a git worktree so that `git grep` can be used instead of `grep`. These checks are done in different not truly correct ways and thus the linters don't use `git grep` when running from a worktree subdirectory, e.g. in a git subtree environment. Unify checks using `git rev-parse --is-inside-work-tree`. Change-Id: I3f54afc99ad0f0e3052cffdd32bdd9649cf3d720 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23util/genbuild_h: Add gitfile supportAlex Thiessen
`genbuild_h.sh` checks whether it is running from a coreboot's own git worktree to decide whether to use git as the time source. This check fails when `${top}/.git` is a gitfile, e.g. when coreboot is a submodule. Add a proper `git rev-parse` call to check the condition, remove `$top` which is not used anymore. Change-Id: I8bb13d607a01f4f28fa8b165769e0a1f702da362 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23util/gitconfig: Replace printf with heredocAlex Thiessen
The `gitconfig.sh` script contains a call to `printf` with a lengthy argument where no format string is used at all. Replace it with a heredoc for better readability. Change-Id: I42dbaa570ab9661991fa5d9b4577c9aed05c2981 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23util/bincfg: don't use fp shared variableDenis 'GNUtoo' Carikli
Change-Id: Ie710f8c6c06332830c3edb9e5490d1e4877ee33b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23util/blobtool: move declaration to their own headerDenis 'GNUtoo' Carikli
Change-Id: I556a122753e8a35c4ed32df460a5e12fa85de7f7 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23util/bincfg: cleanups: use static whenever possibleDenis 'GNUtoo' Carikli
Some non-static declaration remains. If they were made static, the compiler would output some warnings: bincfg.y:30:1: warning: useless storage class specifier in empty declaration }; ^ bincfg.y:47:1: warning: useless storage class specifier in empty declaration }; ^ bincfg.y:22:12: warning: ‘yylex’ used but never defined static int yylex (void); ^~~~~ bincfg.y:456:13: warning: ‘set_input_string’ used but never defined static void set_input_string(char* in); ^~~~~~~~~~~~~~~~ Change-Id: I753e99c4a8290f9edd9abcda9af8e33b6ccfe406 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23243 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23autoport: Add missing command to readmeChristoph Pomaska
The readme.md file was missing the instruction to also compile superiotool, because autoport errors out without a working version of it. Change-Id: Ic426b7312f68d59e2e0503d61da694adc9d4fb3f Signed-off-by: Christoph Pomaska <cp_public@gmx.de> Reviewed-on: https://review.coreboot.org/23282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-01-23util/gitconfig: Use `make` in git hooksAlex Thiessen
As the code was moved from the Makefile.inc to a separate file in commit 9ab8ae6a (util/gitconfig: Make gitconfig a bash script),`$(MAKE)` was replaced by `remake`, introducing dependency on this tool which is basically a `make` with debugging capabilities. Many developers don't have `remake` installed, leading to pre-commit hooks being not executed properly. Apparently this was an unintentional change. Furthermore, special treatment of `make` tool via the `%MAKE%` substitution performed during hooks' deployment is still desired. Use case is calling `remake gitconfig` to set `remake` as the `make` tool in the hooks. To accomplish this, add a parameter that is passed from the Makefile.inc to gitconfig.sh. Change-Id: Ia78e06567b904b342dc9b7778569201fe02e6897 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23util/*: Fix final newlines in scriptsAlex Thiessen
Some script files under the `util` directory have no final newline or multiple final newlines. This is fixed so that an adapted `util/lint/lint-extended-015-final-newlines` does not bark at them anymore. Change-Id: Icec08f1fc7ea837906653475b7f821aa1a143169 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-22util/gitconfig: Replace subshells with bracesAlex Thiessen
The check for `user.name` and `user.email` being set is done in `gitconfig.sh` and it uses two subshells where none is actually needed. Stream redirection can be consolidated. Change-Id: Ia1d19eb3c11f9d11f030dcc179bc175956cd7116 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-22util/gitconfig: Update `sup-destroy` git aliasAlex Thiessen
The `git sup-destroy` alias uses a subshell in order to make `git submodule deinit` deinitialize all submodules. This isn't necessary as the `--all` switch does the same. Furthermore, `git submodule init && git submodule update` equals to `git submodule --init`. Change-Id: Ib690d66795da4049bb0bb350a0609cf2e6b5c4c4 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-20drivers/mrc_cache: Always generate an FMAP regionArthur Heymans
This automatically generates an FMAP region for the MRC_CACHE driver which is easier to handle than a cbfsfile. Adds some spaces and more comments to Makefile.inc to improve readability. Tested on Thinkpad x200 with some proof of concept patches. Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-20autoport: Don't include default_irq_route.aslArthur Heymans
This file is no longer there since ACPI pirq routing is now done in an automated fashion in SSDT. Change-Id: I8bafafbf670fe0fc2f20b46b5d8abee722931c6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christoph Pomaska <cp_public@posteo.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-20autoport: Remove '-' from Kconfig optionsArthur Heymans
This won't compile since '-' is an operator in C. Change-Id: Icf900c959cbcbd0b07cd83a1f6866bf255fdcf01 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christoph Pomaska <cp_public@posteo.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-18util/gitconfig: Fix too long lines in gitconfig.shAlex Thiessen
Change-Id: Iaff0852259f0a91fb4c906e1a01d77b92f8a49f1 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18util/gitconfig: Make gitconfig.sh support gitfileAlex Thiessen
The `gitconfig.sh` script installs hooks to the according directories (for coreboot and its submodules). It has the `hooks` directory hard-coded to be `.git/hooks`, which makes the installation fail when coreboot itself is a submodule because then `.git` becomes a gitfile. Replace hard-coded path handling using the according `git rev-parse` calls. Change-Id: I778e20be24bb27d0081c9e1c12883117d6d50347 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18util/bincfg: Fix some whitespacesDenis 'GNUtoo' Carikli
Change-Id: I674a3f58a576948dc3c0cd32ef06b42ef13353ee Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18util/blobtool: rename to bincfgDenis 'GNUtoo' Carikli
The name blobtool is confusing as 'blob' is also used to describe nonfree software in binary form. Since this utility deals with binary configurations it makes more sense to call it bincfg. Change-Id: I3339274f1c42df4bb4a6b30b9538d91c3c03d7d0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17util/release: Improve git worktree checksAlex Thiessen
The bash script `genrelnotes` checks for `.git` to be present to determine whether the current directory is the top directory of a git worktree. This check is rather weak and doesn't handle many edge cases like that of a broken gitfile. Add a proper `git rev-parse` call to check the condition. Change-Id: I32b06ca982d55fd8e88e55651b6bc53014905823 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15inteltool: Dump Sunrise Point PCH-H GPIO groupsNico Huber
Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15inteltool: Support for nasty Primary to Sideband Bridge (P2SB)Nico Huber
The Primary to Sideband Bridge (P2SB) is the interface to Private Con- figuration Registers (PCR) including GPIO configuration. Of course, access is restricted to Intel partners and criminals, so the PCI device is hidden from the OS. Probably we only need to fetch the SBREG_BAR address and can hide the PCI device again after that. Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15buildgcc: Add patch to work around Musl libc issueNico Huber
GCC includes `sched.h` after poisoning calloc(). This results in a build failure with Musl libc. We work around the issue by including `sched.h` earlier and throw around some void pointers so we only have to do it in one place. Change-Id: I1d5462eb9a448147a95dd4ec50361b3f5a28910c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-01-15buildgcc: Drop libelf/elfutilsNico Huber
Looks like we were unnecessarily dragging this around for some time now. GCC's installation manual doesn't mention libelf as a requirement and a build of crossgcc-i386 doesn't show any sign of it being used. This also fixes a lot issues on non-GNU distributions that were intro- duced by switching to the elfutils version of libelf. Change-Id: Iff308a9bed9ae3842557d251b75d1faadfafe0da Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15util/crossgcc: Output apt-get commands on debianAlex Thiessen
In the buildgcc script, there is a check that the tools required are installed. When a tool is missing, a message is output suggesting an installation method, e.g. `sudo apt-get install foo` on debian-based systems. When run on a true, vanilla debian system, the error message provides only a generic hint because the `please_install()` function fails to detect the OS kind. Detection is based on definition of `ID_LIKE` in `/etc/os-release` yet such systems only define `ID` to `debian`. This commit closes the detection gap. Tested on debian 9 (stretch). Change-Id: I3c867837e9157bee13010bd0a005028c369ce55f Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15util/superiotool: dump VT1211 registersLubomir Rintel
Change-Id: Id01b72a2194ebf3359a11c3ff382efaedf28f9e1 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15util/superiotool: distinguish between VT82C686 and VT1211Lubomir Rintel
They both have a device id of 0x3c. The former is part of the PCI chip set accessible via port 0x3f0 while the latter is a standalone LPC chip accessible via 0x2e/0x4e depending on strapping. They're not register compatible: the VT82C686 only provides a FDC, LPT and part of UARTs. The VT82C686 documentation suggests it has revision 0x00 while the VT1211 datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a revision of 0x02. Thus the revision is probably not good enough to tell one from the another. Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>