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2021-07-17util/kconfig: Stop trying to make sense of Linux configsPatrick Georgi
It only leads to missing symbol errors. Change-Id: Idbce93232ba2b54561abab5b2747c418d6efa92b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15util/ifdtool: Add APL to IFDv2 platformsSubrata Banik
Initially APL was considered as IFDv2 platform irrespective being added into ifd_2_platforms[], hence commit hash 621ed4c had migrated APL into IFDv1 which break its FLMSTR1/FLMSTR2/FLMSTR3 Read/Write access. This change adds APL into the list of IFDv2 platforms to fix booting issue on the LeafHill board. Change-Id: Ied59ddb2fe05b421266a6b119fd6eab17b8beedc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56300 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rick Lee <rick.lee@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14Revert "amdfwtool: Use relative address for EFS gen2"Kangheui Won
This reverts commit 0fc87e31e0b9ad15dd199fe96189a2ade6abf240. Reason for revert: Breaks psp_verstage in guybrush BUG=b:182477057 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14util/sconfig: Remove unused devicetree keywords ESPI & LPCMartin Roth
The ESPI & LPC keywords were added for the zork program, but it was found that they weren't needed, so they were never used. BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3a78afc55477d62eac8056e2ca4bcdd3ab12ea47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56197 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13util/kconfig: Uprev to Linux 5.13's kconfigPatrick Georgi
This was originally several commits that had to be squashed into one because the intermediate states weren't able to build coreboot: - one to remove everything that wasn't our own code, leaving only regex.[ch], toada.c, description.md and Makefile.inc. - one to copy in Linux 5.13's scripts/kconfig and adapt Makefile.inc to make the original Makefile work again. - adapt abuild to use olddefconfig, simplifying matters. - apply patches in util/kconfig/patches. - Some more adaptations to the libpayload build system. The patches are now in util/kconfig/patches/, reverse applying them should lead to a util/kconfig/ tree that contains exactly the Linux version + our own 5 files. Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-13util/abuild: Fix overriding results with the default configurationArthur Heymans
I a file in configs/* has no suffix, then the default configuration will override the results of the build generated by the configfile from configs/*. Fix this by adding a '_' to the buildname. Change-Id: Ic47105fafca41f1905a6569943079623bec5405a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-08amdfwtool: Fix the NULL pointer in parametersZheng Bao
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08amdfwtool: Use relative address for EFS gen2Zheng Bao
The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. Chips like Cezanne can run in both cases, so no problem comes up so far. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-07util/ifdtool: Add sklkbl to IFDv2 platformsJan Tatje
Currently ifdtool breaks the descriptor because it treats it as IFDv1. This change adds it to the list of IFDv2 platforms. Fixes boot for X11SSH-LN4F. Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset") Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05util/board_status: Do not display grep messagePaul Menzel
Redirect stdout and stderr from grep to check for unknown timestamps, when no timestamps are stored, which is already logged earlier. Failed to run "/root/coreboot/util/cbmem/cbmem -t", ignoring Getting remote dmesg grep: /tmp/coreboot_board_status.dXmbUIBP/emulation/qemu-i440fx/4.14-876-gdb28040ee1/2021-07-02T23_14_33Z/coreboot_timestamps.txt: No such file or directory Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-02util/cbfstool: Allow setting alignment for payloadRaul E Rangel
The -a flag was already implemented, it just wasn't exposed for the add-payload command. Setting the alignment of the payload will enable using the SPI DMA controller to read the payload on AMD devices. BUG=b:179699789 TEST=cbfstool foo.bin add-payload -a 64 ... Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02util/intelp2m: use import once for all included modulesMaxim Polyakov
There is no need to repeat "import" for each module in GoLang. Use this keyword only once in each file for code cleanliness. Change-Id: Ibb24fafd409b31b174946a39ca1f810d59b87e76 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage()Arthur Heymans
The dereferced parameter is never updated so passing a copy would work too. Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55792 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28security/intel/cbnt: Build test CBnT provisioningArthur Heymans
This updates the intel-sec-tools submodule pointer to include a fake acm binary to be included for buildtesting. Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-26cbfstool: Unset ${DEBUG} when making vboot hostlibNico Huber
Vboot's Makefile is controlled by a ${DEBUG} environment variable. As the name is very generic, it may be set by accident without any intention to change the build. Having it set would break reproduci- bility at least but it also turns out that the hostlib build would be incomplete so that linking cbfstool fails due to internal calls to vb2api_fail() which is not built in. Change-Id: I2a9eb9a645c70451a320c455b8f24bfed197117c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-26util/ifdtool: Add Xeon SP Lewisburg PCH platform support under IFDv2Johnny Lin
After commit 8c082e5fe (util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset) w/o this xeon_sp/cpx would be detected as IFDv1 and see build error. Fixes: 8c082e5fe ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset") Change-Id: I444e7d35a85d9d42fc25d654e57386f38cf1ec85 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25cbfstool: Make use of spurious null-terminationNico Huber
The null-termination of `filetypes` was added after the code was written, obviously resulting in NULL dereferences. As some more code has grown around the termination, it's hard to revert the regression, so let's update the code that still used the array length. This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read) which actually did fix something, but only one path while it broke two others. We should be careful with fixes, they can always break something else. Especially when a dumb tool triggered the patching it seems likely that fewer people looked into related code. Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-22docker/coreboot.org-status: Update URL schemes to git reposPatrick Georgi
We moved from gitweb to cgit to gitiles and some of the URL schemes were lost during the transitions. Update to the gitiles scheme so board-status links work again. Change-Id: Id2a840bf89fab172e0eab21e303ac0c4666b6751 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-20util/ifdtool: Use ICH Strap Length (ISL) to identify APL chipsetSubrata Banik
Use offset FLMAP1 bit 24:31, called ISL (ICH Strap Lenth) to uniquely identify the chipsets without any additional logic. +---------+-----------+ | Chipset | PSL Value | +---------+-----------+ | APL | 0x13 | +---------+-----------+ BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on APL (IFDv1) Platform. > ifdtool -d coreboot.rom PCH Revision: Apollo Lake: N3xxx, J3xxx Change-Id: I02bcc6b1ca61c4ee59582f1b310ed0fba0ef1d9a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-20util/ifdtool: Use -p platform name to detect IFDv2 platform and chipsetSubrata Banik
ifdtool uses `chipset` information to determine how certain straps are decoded. This has been used for IFDv1 platforms as well as IFDv2 platforms (CHIPSET_500_600_SERIES_TIGER_ALDER_POINT). IFDv2 platforms are all expected to pass in `-p` argument to identify the platform. This platform information can be used to identify the appropriate chipset information. For IFDv1 since `-p` argument is not provided, ifdtool needs to use certain fields in the descriptor (e.g. strap length) for unique identification of IFDv1 chipset. This change updates `check_ifd_version()` function to: 1. Determine if IFD version is v1 or v2 based on `-p` argument. If `-p` is not provided, it assumes that the platform is using IFDv1. 2. Based on IFD version, it calls either `ifd2_platform_to_chipset()` or `ifd1_guess_chipset()` to determine chipset information. This fixes the issue reported with CB:44815, where ifdtool is unable to identify Alder Lake chipsets. BUG=b:153888802 TEST=Able to dump FD contains correctly with platform quirks on Brya Platform. > ifdtool -d coreboot.rom -p adl PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54305 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18util/ifdtool: Add Elkhart Lake platform support under IFDv2Lean Sheng Tan
Add EHL under same family tree as TGL & JSL, also fix a spacing inconsistency line. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ice09861c104c4e339fc83631c75089fa069b3931 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16util/intelp2m/fsp: Update some deprecated macrosBenjamin Doron
Avoid using deprecated macros, where possible. "GpioResetPwrGood" represents multiple valid updated values, depending on the GPIO community and will be more difficult to update. While Kabylake supports both sets of macros, it will cause build errors on Coffeelake. In the GPD group, replace with "GpioDswReset." Replace with "GpioResumeReset" in any GPP group. Change-Id: Iab0bb09adad997bef3a2133c443471d4c634f423 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2021-06-15treewide: Disable R_AMD64_32S relocation supportPatrick Rudolph
This fixes a hard to debug hang that could occur in any stage, but in the end it follows simple rules and is easy to fix. In long mode the 32bit displacement addressing used on 'mov' and 'lea' instructions is sign-extended. Those instructions can be found using readelf on the stage and searching for relocation type R_X86_64_32S. The sign extension is no issue when either running in protected mode or the code module and thus the address is below 2GiB. If the address is greater than 2GiB, as usually the case for code in TSEG, the higher address bits [64:32] are all set to 1 and the effective address is pointing to memory not paged. Accessing this memory will cause a page fault, which isn't handled either. To prevent such problems - disable R_AMD64_32S relocations in rmodtool - add comment explaining why it's not allowed - use the pseudo op movabs, which doesn't use 32bit displacement addressing - Print a useful error message if such a reloc is present in the code Fixes a crash in TSEG and when in long mode seen on Intel Sandybridge. Change-Id: Ia5f5a9cde7c325f67b12e3a8e9a76283cc3870a3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-14amdfwtool: Null check the pointers before using themZheng Bao
BUG=b:188769922 Reported-by: Coverity (CID:1438963) Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14util: Add DDR4 generic SPD for MT40A512M16TB-062E:RWisley Chen
Add SPD support for DDR4 memory part BUG=b:190020997 TEST=none Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12util/intelp2m/fsp: Fix wrong register decoding for direction and interruptBenjamin Doron
Using the wrong registers to build the fields led to incorrect GPIO direction and interrupt trigger values. Change the calls to fix the tables. Change-Id: Icbeeb1fec6a863d0f86659c21924e15ae6765d47 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54973 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-09amdfwtool: Add missing license headerZheng Bao
Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09amdfwtool: Move EFS related definitions to header fileZheng Bao
EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-08lint: checkpatch: Add SUSPICIOUS_CODE_INDENT testJulius Werner
This patch adds a new test to checkpatch that identifies cases where a line after a conditional statement is incorrectly intended (possibly indicating the mistake of forgetting to add braces), like this: if (a) b; c; Unfortunately, it seems like checkpatch is partially unmaintained in upstream Linux at the moment with maintainers either not responding at all or not even willing to look at new patches [1]. Since detecting this error class is important to coreboot, let's just carry this feature locally for now. [1] https://lkml.org/lkml/2021/4/15/1488 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7bb90b56dfc7582271d2b82cb42a2c1df477054f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-07amdfwtool: Print the entry type when dumping the firmwaresZheng Bao
Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07amdfwtool: Set the region_type as 0 for entry "BIOS level 2"Zheng Bao
This region_type is actually not used. But we need to set it explicitly as a known value. We can refer "PSP spec #55758" or the link below: https://doc.coreboot.org/soc/amd/psp_integration.html Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07sb/intel/bd82x6x: Drop P_LVLx support in FADTAngel Pons
IO MWAIT redirection is not enabled, and C-states are reported using the _CST ACPI object, which overrides the P_LVLx values. Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-06util/crossgcc: Avoid complex filename setsPatrick Georgi
bin/{foo,bar,baz} can fail if one of the files doesn't exist (depending on the shell in use). Instead, cd into the directory and list the files individually. Change-Id: I042b2e45fded1b63551d8e65ead2a7bbbf96b1e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-06util/crossgcc: Update to clang 12Patrick Georgi
Change-Id: I38fc64fa872e2ecb0a10fb5378b3ce0d6a02443c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-04Revert "util/vboot_lib: Add description.md"Angel Pons
This reverts commit 255b6f8646903594fb728f8228908792bad766f0. No longer needed after commit dd01e0131a8ba901bedec48844502fe85663390a (Revert "util/lint: Add test for documentation in util dirs") has been submitted. Plus, `util/vboot_lib/description.md` gets deleted whenever one runs `make -C util/cbfstool clean`, which is rather annoying. Change-Id: Ic93da096b6186d1d2af12243a74ec597694960c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55162 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04util/cbfstool/linux_trampoline.h: Fix typo in commentAngel Pons
inlucde ---> include Change-Id: I38987119ddabb08c457c9a7c8aecb8025fe2d9d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55161 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 configAmanda Huang
CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-02cbfstool/linux_trampoline.S: Fix up the e820 tableArthur Heymans
The e820 type don't fully match the LB_TAG_MEMORY types, so change all unknown types to e820 to '2', reserved memory. TESTED with Linuxboot: e820 now shows the CBMEM region as reserved. Change-Id: Ie0e41c66e002919e41590327afe0f543e0037369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55074 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Rocky Phagura Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01soc/amd/picasso: introduce and use chipset device treeFelix Held
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01util/cbfstool/Makefile: Check out vboot before trying to use itPatrick Georgi
Change-Id: Ie2044d73b97663f7816964c4d908a46570aafdbc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-27util/cbfstool/fit.c: Fix getting the topswap tableArthur Heymans
There is a function to fetch the fit table at both the regular address and the TS address. So reuse that function instead of attempting to find the TS fit using some pointer aritmetics that is incorrect. Change-Id: I9114f5439202ede7e01cd0fcbb1e3c4cdb8698b0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54680 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25autoport: add a go.mod fileIru Cai
Go 1.16 needs this when running `go build` without GO111MODULE=off. Change-Id: I9dcb134a68b7a726f1466a472a415c9558f60524 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24sconfig: Emit probe_list in all stagesFurquan Shaikh
`probe_list` member in `struct device` is present in all stages, however, util/sconfig emits the list only when !DEVTREE_EARLY. This change ensures that `probe_list` is emitted in all stages. In follow up changes, this is used to get the correct device state using probe conditions. Change-Id: I61f7e909d48b616ac2127a5a9f36bdf4817a5165 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-22util/spd_tools/lp4x: Add new memory part to to global memory definitionDtrain Hsu
This new definition is for MT53E512M32D1NP-046 WT:B used on Cret. BUG=b:183057749 TEST=Generate SPDs Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ica5df61d96d2c4cbe62a560a53bd3bd08eb121f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-22util/crossgcc: Update acpica to 20210331Patrick Georgi
Change-Id: Ic517a2b9c9b7122d2a65f67380d3ce368303d725 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2021-05-18util/mb/google: add support for bryaPaul Fagerburg
Add the file templates for creating a new variant of Brya. BUG=b:177017247 Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: If141d9b43ea5b845c1855f12e03e7d0cf535d2ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/54489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18util/testing/Makefile.inc: Add new line as help section separatorJakub Czapiga
coreboot test targets help section was missing an empty line at the end. This caused the next help section to be visually merged with it. Empty line makes help output more aesthetic. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I2f7202b0a636f62b60788215058611c9c86183de Reviewed-on: https://review.coreboot.org/c/coreboot/+/54367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-18amdfwtool:cezanne: use correct bootloader binary for whitelist supportNikolai Vyssotski
PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type 0x73 entry and not type 0x01 (stage1 bootloader). We will also need to change WHL BL filename (Type0x01->Type0x73) in a separate CL. BUG=b:181135622 Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-18amdfwtool: Remove the misleading option charactersZheng Bao
Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-05-12util/crossgcc: Update mpc to 1.2.1Patrick Georgi
Change-Id: Ic1422464d0a95c9cba1c417aaa05e4f1fe799d26 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12util/crossgcc: Update gmp to 6.2.1Patrick Georgi
Change-Id: I871942f66e8fc496ebe523fdab539ea20950a202 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12util/genbuild_h: Update IASL location finding codeMartin Roth
Update the iasl path finding code to use XGCCPATH if it's set, and to look for iasl on the path if it's not set and not under util/crossgcc. On the jenkins builders, iasl is in the path, not in util/crossgcc/xgcc. On the systems of people who have multiple copies of coreboot, it makes sense to just have a single copy of the toolchain and define XGCCPATH in the environment to point to it. Previously, either of these situations resulted in a warning from the genbuild_h tool that iasl was not found under util/crossgcc, which was true, but not particularly relevant, and generated confusion. If xcompile already existed before make was run, the correct path would be found, but on an initial build, this check couldn't find iasl. BUG=None TEST=Build with iasl in /util/crossgcc/xgcc/bin, in the path and in a directory pointed to with XGCCPATH. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ic2f8dca0be8bfb54d3c672fab6cf6f005bb394c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-10util/cbfstool: Do not set -D_XOPEN_SOURCE on FreeBSDIdwer Vollering
Fixes compilation on FreeBSD CURRENT, and possibly other releases. The compiler, clang, complained about: util/cbfstool/cbfstool.c:181:40: error: implicit declaration of function 'memmem' is invalid in C99 [-Werror,-Wimplicit-function-declaration] util/cbfstool/cbfstool.c:181:31: error: incompatible integer to pointer conversion initializing 'struct metadata_hash_anchor *' with an expression of type 'int' [-Werror,-Wint-conversion] Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I45c02a21709160df44fc8da329f6c4a9bad24478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53996 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10inteltool: add initial support for Emmits Burg PCHJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I6a4027bf51b3a189e64211e77621b3dd6c80b00d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-10inteltool: add initial suppot for Sapphire Rapids Scalable ProcessorJonathan Zhang
Intel Sapphire Rapids Scalable Processor is a 4th generation processor of Intel Xeon Scalable Processor family. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Idf492d6e7993b9d55d6cd865e721c81876cee9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52863 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05util/intelp2m: Set GO111MODULE environment parameter explicitlyArthur Heymans
With go1.16 the default for GO111MODULE changed to on which break building this tool. Change-Id: I93a516ff76c8da4b7f37157d58ecd4c0b09c582c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52862 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05util/sconfig: Fix null pointer dereferencesTim Wawrzynczak
Should use `name` instead of `field->name`, because `field is supposed to be NULL at this point. TEST=add new field from bits 29-64 to volteer, ensure sconfig prints an error instead of segfaulting. Change-Id: I933330494e0b10e8494a92e93d6beb58fbec0bc1 Found-by: Coverity CID 1452916 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52888 Reviewed-by: Duncan Laurie Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03util/sconfig: Add support for discontiguous FW_CONFIG fieldsTim Wawrzynczak
Sooner or later, some board was going to need extra FW_CONFIG bits for a field that was already in production, so this patch adds support for adding extra (unused) bits to a field. The extra are appended via a syntax like: `field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...` and the suffixed bits are all treated as if they are contiguous when defining option values. BUG=b:185190978 TEST=Modified volteer fw_config to the following: field AUDIO 8 10 | 29 29 | 31 31 option NONE 0 option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 option MAX98360_ALC5682I_I2S 5 option RT1011_ALC5682I_I2S 6 option AUDIO_FOO 7 option AUDIO_BAR 8 option AUDIO_QUUX 9 option AUDIO_BLAH1 10 option AUDIO_BLAH2 15 option AUDIO_BLAH3 16 option AUDIO_BLAH4 31 end which yielded (in static_fw_config.h): FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700 FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500 FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700 Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52747 Reviewed-by: Duncan Laurie <duncan@iceblink.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30amdfwtool: Cleanup the message of helpZheng Bao
1. Wrap the long lines. 2. Align the message. 3. Add new SOC name, Cezanne. 4. Fix the cases. Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-29migrate out of flashrom deprecated optionsDaniel Campello
This change replaces --diff and --fast-verify for the supported equivalent flashrom options Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I8c48c7f819f968c3ddd94278415e5e9e0ef93924 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-04-23util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 configMartin Roth
The revision B version of the MT53E1G32D2NP-046 memory chip will be used in the next guybrush build. It has a different internal layout than the Revision A part, with 2 ZQ lines per module instead of 1. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I066f40eb890648a9be17cfe0cee20d299000c11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-18util/kconfig_lint: Update handle_expressions()Nico Huber
More relational operators were added to Kconfig in 2015. Now we can make use of them. Change-Id: I640e5c3ee1485348f09fcb0b0d5035eb53a2c98e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18util/kconfig_lint: Turn handle_expressions() into a parserNico Huber
I wished there was a way to do this in smaller steps, but with every line fixed an error somewhere else became visible. Here is a (probably incomplete) list of the issues: * Only one set of parentheses was supported. This is a hard to solve problem without a real parser (one solution is to use an recursive RE, see below). * The precedence order was wrong. Might have been adapted just to give a positive result for the arbitrary state of the tree. * Numbered match variables (e.g. $1, $2, etc.) are not local. Calling handle_expressions() recursively once with $1, then with $2, resulted in using the final $2 after the first recursive call (garbage, practically). Also, symbol and expression parsing was mixed, making things harder to follow. To remedy the issues: * Split handle_symbol() out. It is called with whitespace stripped, to keep the uglier REs in handle_expressions(). * Match balanced parentheses and quotes when splitting expressions. In this recursive RE /(\((?:[^\(\)]++|(?-1))*\))/ the `(?-1)` references the outer-most group, thus the whole expression itself. So it matches a pair of parentheses with a mix of non-parentheses and the recursive rule itself inside. This allows us to: * Order the expression matches according to their precedence rules. Now we can match `<expr> '||' <expr>` first as we should and everything else falls into its place. * Remove the bail-out that silenced the undefined behavior. Change-Id: Ibc1be79adc07792f0721f0dc08b50422b6da88a9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-15checkpatch_json: Mark robotic comments as roboticPatrick Georgi
Gerrit now knows to differentiate between "regular" comments and "robot" comments, with some later changes to the UI in the pipeline (e.g. to filter out robot messages) Change-Id: I3a545d1cf6c04b331964becd2b24eb38018394eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-04-14maintainers.go: Work around common mistake in MAINTAINERSMichael Niewöhner
Gerrit is able to add reviewers based on entries in the `MAINTAINERS` file. For inclusion and exclusion matches either paths or regular expressions can be used. The syntax is described in the header of the file. When matching a path, there are two sensible possibilities: - `path/to/file` matches a file. - `path/to/dir/` matches a folder including its contents recursively. - `path/to/dir/*` matches all files in that folder, without recursing into its subfolders. The trailing slash in the second example is essential. Without it, only the directory entry itself matches when, for example, the folder gets deleted, renamed or its permissions get modified. Reviewers in the list won't get added to changes of any files or directories below that path. However, from time to time entries get added without this trailing slash. Thus, implement a workaround in `maintainers.go` to check, if a path entry is actually a directory. In such case a trailing slash gets appended, so that the contents will match, too. Example: `path/to/dir` will become `path/to/dir/` Tests: 1. output before and after does not differ 2. manual test of resulting regex when running `maintainers.go` Change-Id: Ic712aacb0c5c50380fa9beeccf5161501f1cd8ea Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52276 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14maintainers.go: correct handling of globsMichael Niewöhner
maintainers.go does not handle globs as described in MAINTAINERS. Instead of only matching the files inside a directory, it also matches everything below. Also, a glob used in between (`e.g. path/to/*/dir`) could lead to matching many more paths unexpectedly. This is caused by the way paths using globs are converted to regegular expressions for use with gerrit: 1. The script converts all paths with trailing slash to a path with trailing glob. That means, a recursive match on a directory gets converted to match only the files in the directory (at least according to the documentation - if there wasn't 2). Example: `path/to/dir/` becomes `path/to/dir/*` 2. When converting the path to a regex, all globs get converted to prefix matching by replacing the glob by `.*`. Instead of only matching the files in the directory, everything below matches, which is a) not what the documentation states and b) the opposite of what 1. did first. Example: `path/to/dir/*` becomes `^path/to/dir/.*$` In sum, this leads to all sorts of issues. Examples: - `path/*/dir` becomes `^path/.*/dir$` - `path/to/dir/*` becomes `^path/to/dir/.*$` - `path/to/*.c` becomes `^path/to/.*\.c$` This change fixes that behaviour by: - dropping the wrong conversion from 1. above. - fixing glob matching by replacing `*` by `[^/]`. - handling paths with trailing `/` as prefix, as documented. The change was not split because these changes depend on each other and splitting would break recursive matching between the commits. Tests: 1. diffed output before and after is equal (!= the same) 2. manual testing of glob matching Change-Id: I4347a60874e4f07e41bdee43cc312547bea99008 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-14Rename do_printk() to printk()Nico Huber
The indirection seems unnecessary. The macros throw features like `-Wmisleading-indentation` off, though. Default build for QEMU/Q35 is unchanged. Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-13lint: MAINTAINERS: check path matches to not only cover the directoryMichael Niewöhner
Gerrit is able to add reviewers based on entries in the `MAINTAINERS` file. For inclusion and exclusion matches either paths or regular expressions can be used. The syntax is described in the header of the file. When matching a path, there are two sensible possibilities: - `path/to/file` matches a file. - `path/to/dir/` matches a folder including its contents recursively. - `path/to/dir/*` matches all files in that folder, without recursing into its subfolders. The trailing slash in the second example is essential. Without it, only the directory entry itself matches when, for example, the folder gets deleted, renamed or its permissions get modified. Reviewers in the list won't get added to changes of any files or directories below that path. Thus, add a linter script to ensure a path match on a directory always ends with `/` or `/*` as shown above. Change-Id: I9873184c0df4a0b4455f803828e2719887e545db Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-09util/genbuild_h: add COREBOOT_BUILD_EPOCH seconds since epochAlexander Couzens
To use SOURCE_DATE_EPOCH for the kernel build, extend genbuild_h to contain COREBOOT_BUILD_EPOCH. Change-Id: Iaa79d3e7df8101a1ba1b37a361d8992f7eab2d52 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-07util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET))Martin Roth
This change was promised as a follow-up in change ID: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-06lint: checkpatch: Only exclude specific src/vendorcode/ subdirectoriesJulius Werner
Some of the src/vendorcode/ directories are used to import a whole codebase from somewhere else which uses a completely different coding style. For those directories, excluding them from checkpatch makes sense. However, other directories are simply implementing vendor-specific extensions that were written by coreboot developers specifically for coreboot in coreboot's coding style. Those directories should be covered by checkpatch. This patch narrows the existing blanket exception of src/vendorcode/ to the amd, cavium, intel and mediatek directories (which actually include large amounts of foreign source). The eltan, google and siemens directories (which seem to contain code specifically written for coreboot) will now be covered by checkpatch. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1feaba37c469714217fff4d160e595849e0230b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51827 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06util/crossgcc: Add date to the toolchain revisionMartin Roth
With the current version method, it's not possible to determine if a different version is older or newer than the current version without digging into the repository and finding the dates for the version numbers. This change adds the commit date to the start of the toolchain version which will let us tell at a glance how old or new the toolchain is. It's not perfect because multiple toolchain commits can go in on the same day, but adding the time made the string even longer, and really doesn't help that much. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c6d27667b922dc15e7a6e132e1beff69eed839c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-06util/kconfig_lint: Drop exception for paths without quotesNico Huber
The tree is clean at the moment. Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52066 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06util: Add DDR4 generic SPD for Micron MT40A1G16RC-062E-B 16GbKevin Chiu
Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb BUG=b:184024142 TEST=none Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-05util/bincfg: Clean up MakefileMartin Roth
- Enable warnings - Enable warnings as errors - Remove debug flag -g - Add targets for all, distclean, and help - Add dependency of the bincfg file for output targets - Add all phony targets to .PHONY BUG=None TEST=Build all targets Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50654 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22util: Add DDR4 generic SPD for H4AAG165WB-BCWENick Vaccaro
Add SPD support for DDR4 memory part H4AAG165WB-BCWE. BUG=b:181732562 TEST=none Change-Id: I923fcbd08875a2a581fba4b1db00a4d1c1bb11cf Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19util/ifittool: Add an option to set the FIT pointer a CBFS fileArthur Heymans
The purpose of this is to eventually move the FIT table out of the bootblock, generate it separately as a cbfs file and then have the FIT pointer point to that cbfs file. TESTED: extracted a FIT table using dd, added it as a cbfs file and see that the FIT pointer correctly points to it. Also test that trying to add a non valid FIT cbfs file results in an error. Change-Id: I6e38b7df31e6b30f75b0ae57a5332f386e00f16b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-18util/qualcomm: fix python syntax warningsBaruch Siach
Don't use 'is' and 'is not' for comparison with literals. This fixes warnings like: .../mbn_tools.py:1097: SyntaxWarning: "is not" with a literal. Did you mean "!="? if int(off) is not 0: Change-Id: Idd68acfcbd1a07cbbb9ab41d9581c4850a431445 Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-17cbfs: Move stage header into a CBFS attributeJulius Werner
The CBFS stage header is part of the file data (not the header) from CBFS's point of view, which is problematic for verification: in pre-RAM environments, there's usually not enough scratch space in CBFS_CACHE to load the full stage into memory, so it must be directly loaded into its final destination. However, that destination is decided from reading the stage header. There's no way we can verify the stage header without loading the whole file and we can't load the file without trusting the information in the stage header. To solve this problem, this patch changes the CBFS stage format to move the stage header out of the file contents and into a separate CBFS attribute. Attributes are part of the metadata, so they have already been verified before the file is loaded. Since CBFS stages are generally only meant to be used by coreboot itself and the coreboot build system builds cbfstool and all stages together in one go, maintaining backwards-compatibility should not be necessary. An older version of coreboot will build the old version of cbfstool and a newer version of coreboot will build the new version of cbfstool before using it to add stages to the final image, thus cbfstool and coreboot's stage loader should stay in sync. This only causes problems when someone stashes away a copy of cbfstool somewhere and later uses it to try to extract stages from a coreboot image built from a different revision... a debugging use-case that is hopefully rare enough that affected users can manually deal with finding a matching version of cbfstool. The SELF (payload) format, on the other hand, is designed to be used for binaries outside of coreboot that may use independent build systems and are more likely to be added with a potentially stale copy of cbfstool, so it would be more problematic to make a similar change for SELFs. It is not necessary for verification either, since they're usually only used in post-RAM environments and selfload() already maps SELFs to CBFS_CACHE before loading them to their final destination anyway (so they can be hashed at that time). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-16cbfstool: Move alignment/baseaddress handling into cbfs_add_component()Julius Werner
The --alignment flag is currently only handled by cbfstool add, but there seems little reason to not handle it for all file-adding commands (the help text actually mentions it for add-stage as well but it doesn't currently work there). This patch moves the related code (and the related baseaddress handling) into cbfs_add_component(). As a nice side effect this allows us to rearrange cbfs_add_component() such that we can conclusively determine whether we need a hash attribute before trying to align the file, allowing that code to correctly infer the final header size even when a hash attribute was implicitly added (for an image built with CBFS verification enabled). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idc6d68b2c7f30e5d136433adb3aec5a87053f992 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47823 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16util/cbfstool/ifittool: Remove dead codeArthur Heymans
The 'x' option is not set up in the getopt options. Change-Id: Ib4aa10b0ea2a3f97e8d2439152b708613bcf43db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-13cbfstool: Add support for platform "fixups" when modifying bootblockJulius Werner
To support the new CONFIG_CBFS_VERIFICATION feature, cbfstool needs to update the metadata hash embedded in the bootblock code every time it adds or removes a CBFS file. This can lead to problems on certain platforms where the bootblock needs to be specially wrapped in some platform-specific data structure so that the platform's masked ROM can recognize it. If that data structure contains any form of hash or signature of the bootblock code that is checked on every boot, it will no longer match if cbfstool modifies it after the fact. In general, we should always try to disable these kinds of features where possible (they're not super useful anyway). But for platforms where the hardware simply doesn't allow that, this patch introduces the concept of "platform fixups" to cbfstool. Whenever cbfstool finds a metadata hash anchor in a CBFS image, it will run all built-in "fixup probe" functions on that bootblock to check if it can recognize it as the wrapper format for a platform known to have such an issue. If so, it will register a corresponding fixup function that will run whenever it tries to write back modified data to that bootblock. The function can then modify any platform-specific headers as necessary. As first supported platform, this patch adds a fixup for Qualcomm platforms (specifically the header format used by sc7180), which recalculates the bootblock body hash originally added by util/qualcomm/createxbl.py. (Note that this feature is not intended to support platform-specific signature schemes like BootGuard directly in cbfstool. For anything that requires an actual secret key, it should be okay if the user needs to run a platform-specific signing tool on the final CBFS image before flashing. This feature is intended for the normal unsigned case (which on some platforms may be implemented as signing with a well-known key) so that on a board that is not "locked down" in any way the normal use case of manipulating an image with cbfstool and then directly flashing the output file stays working with CONFIG_CBFS_VERIFICATION.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I02a83a40f1d0009e6f9561ae5d2d9f37a510549a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13cbfstool: Support CONFIG_CBFS_VERIFICATION and metadata hash anchorJulius Werner
This patch adds support for the new CONFIG_CBFS_VERIFICATION feature to cbfstool. When CBFS verification is enabled, cbfstool must automatically add a hash attribute to every CBFS file it adds (with a handful of exceptions like bootblock and "header" pseudofiles that are never read by coreboot code itself). It must also automatically update the metadata hash that is embedded in the bootblock code. It will automatically find the metadata hash by scanning the bootblock for its magic number and use its presence to auto-detect whether CBFS verification is enabled for an image (and which hash algorithm to use). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41121 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12util/qemu: Add additional config file for QEMU/Q35Nico Huber
The `q35-alpine.cfg` adds a lot of PCIe devices to resemble the topology inside an Intel Alpine Ridge Thunderbolt controller. By no means could this be detected as such a controller. But having a real-world example of such a topology can help to test the allocator and other algorithms on a deeper tree. It adds two levels of PCIe switches (`alpine-root` and `alpine-1`), and two endpoints (a `pci-testdev` and an xHCI controller). It can be added to the default `q35-base.cfg` config, e.g. with: $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg Change-Id: Ieab09c5b67a5aafa986e7d68a6c1a974530408b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51329 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03util: Add new memory part to LP4x listAmanda Huang
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03util/spd_tools/lp4x: Add 2 new parts to global memory definitionMartin Roth
This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-27crossgcc: Delete conflicting, stale symbolic linkNico Huber
If a previous build failed or the build dir is still around for other reasons (e.g. buildgcc's `-t`) the symbolic link to our `bin` dir we create there is also still around and can't be created again without removing it first. Attempts to use `ln -f` also fail as the existing destination is treated as directory and a new symbolic link would be created inside. Change-Id: I7a2720b0286e33d1ba26ea01f323dbf4f8afaea0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27Revert "util/lint: Add test for documentation in util dirs"Nico Huber
This reverts commit 15e379aaf334e7931710b4208ccedf2f9ee44b0d. It triggers on directories that only contain artifacts and no checked in code. As this happens a lot when switching branches, it makes it impossible to commit new code. Change-Id: I38a86c8a5d5dc14ca5f6cba789bcb8c0fcaefb0b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27util/spd_tools: Run go fmt on all .go filesMartin Roth
This just reformats these files. go fmt should probably be run on the check-in of every .go file. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I70ced115bad42d123474b18bbff2e4c0a16f3d88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51019 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27util/spd_tools: Add Cezanne support to lp4x/gen_spd.goMartin Roth
To supply memory information for Guybrush, the lpddr4x script for generating SPDs needs to be updated for Cezanne. BUG=b:178722935 TEST=Add the part used on Majolica to the global lpddr4x json file and verify that the output is similar to the actual SPD used for Majolica. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1f522cb4a92b4fe4c26cad0689437c33ec44befe Reviewed-on: https://review.coreboot.org/c/coreboot/+/51015 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26util/autoport: Add dsdt_top.aslKyösti Mälkki
Fix required after commit cf246d5166 that added a top-level ASL file. Change-Id: Ifd3ef021a6024950021406cfbd13ccaa7bbdbce5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/lint: Check for windows line endingsMartin Roth
The codebase currently has only unix line endings, so add a lint tool to check for windows line endings. BUG=None TEST=Verify that line endings are caught both inside and outside a git repo. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I6faf99a3184e4843640fb8965f8124de0bc52ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/ectool: Update MakefileMartin Roth
- Add a help target - Add the -Wshadow and -Werror options - Add a way to disable -Werror Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0d9fe5beb3a2e103a0bf4603712c3a5ed15f93be Reviewed-on: https://review.coreboot.org/c/coreboot/+/50850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/cbmem: Update MakefilesMartin Roth
- Add a help target - Add the -Wshadow option - Add a way to disable -Werror Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icd4e5cf51d60254d274c6e5093285cd49ff1607a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/cbfstool: Update MakefilesMartin Roth
- Add a distclean target - Add a help target - Add the -Wshadow option Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie31d61bd0e28b1e228656dfa09b5ab1996868706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/bucts: Clean up Makefile to match othersMartin Roth
- Add a TARGET variable - Enable optimization and additional warnings - Add distclean target - Add help target Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8eb190abd1ab20da7dd1ae43ef0358ba91df000e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/bucts: Fix compiler complaints shown with -WextraMartin Roth
This fixes the following 2 complaints: bucts.c: In function ‘main’: error: unused parameter ‘envp’ error: ‘bucts_state’ may be used uninitialized in this function. The bucts_state wasn't real, but the compiler couldn't tell, so use one variable to check for modifications instead of two. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iff1aae3441ec366d272e88b6b6634980d61cb8ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/50846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20sconfig: Use get_chip_instance() to set base_chip_instanceFurquan Shaikh
Now that multiple device trees are supported (chipset, base, override), base_chip_instance parameter for override device needs to be set to the base chip instance of the corresponding device in base/primary tree. This can be achieved by using `get_chip_instance()` instead of using base_dev->chip_instance in `update_device()`. TEST=Verified that coreboot.rom generated using timeless shows no change for all boards. Change-Id: I42e3f4b83c55f3479b95dbbd7a3721558c32b1c8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4Julius Werner
cbfstool has always had a CBFS_FILENAME_ALIGN that forces the filename field to be aligned upwards to the next 16-byte boundary. This was presumably done to align the file contents (which used to come immediately after the filename field). However, this hasn't really worked right ever since we introduced CBFS attributes. Attributes come between the filename and the contents, so what this code currently does is fill up the filename field with extra NUL-bytes to the boundary, and then just put the attributes behind it with whatever size they may be. The file contents don't end up with any alignment guarantee and the filename field is just wasting space. This patch removes the old FILENAME_ALIGN, and instead adds a new alignment of 4 for the attributes. 4 seems like a reasonable alignment to enforce since all existing attributes (with the exception of weird edge cases with the padding attribute) already use sizes divisible by 4 anyway, and the common attribute header fields have a natural alignment of 4. This means file contents will also have a minimum alignment guarantee of 4 -- files requiring a larger guarantee can still be added with the --alignment flag as usual. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I43f3906977094df87fdc283221d8971a6df01b53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>