summaryrefslogtreecommitdiff
path: root/util
AgeCommit message (Collapse)Author
2008-12-05flashrom: Add AMD SB700 flash enableNiels Ole Salscheider
This patch adds SB700 support to flashrom. The code for enabling the flash rom is the same as for SB600. It was tested (read, write, verify) with an ASUS M3A-H/HDMI which contains a Macronix MX25L8005. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05flashrom: Fix compilation of r3797 with gcc-4.3.2Peter Stuge
Thanks to Niels Ole Salscheider for the problem report. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05flashrom: Check if erase succeeds and exit with error on failure.Peter Stuge
flashrom used to exit 0 even if erase failed. Not anymore. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04Patch to util/inteltool:Stefan Reinauer
* PMBASE dumping now knows the registers. * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04Add RDID/REMS IDs for the following flash chips:Carl-Daniel Hailfinger
SST_25VF512A_REMS SST_25VF010_REMS SST_25VF020_REMS SST_25VF040_REMS SST_25VF040B_REMS SST_25VF080_REMS SST_25VF080B_REMS SST_25VF032B_REMS SST_26VF016 SST_26VF032 W_25X16 W_25X32 W_25X64 Straight from the data sheets. The REMS IDs help in case the RDID opcode is unavailable (due to opcode lockdown) or unsupported by the chip. Some day, we need to pair probe functions together with IDs. Multiple pairs can exist per chip and duplicating chip definitions does not really make sense. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03flashrom: gcc thinks base could be used uninitialized, so shut it up.Peter Stuge
Bug from r3791. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03flashrom: Fix bug in r3790Peter Stuge
If flashbase was set before probe_flash() it would only ever be used once, for the very first flash chip probe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03Replace #ifdefs for sc520 systems by run time probing.Stefan Reinauer
fixes #109 Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-02build_opt_tbl:Stefan Reinauer
make sure the temporary files are created in the same directory as the target files so they can be rename()d. This fixes a compilation issue on machines with the build directory living on another partition than /tmp. Pretty trivial. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01The Winbond Super I/O chips have another indirection of registers. TheStefan Reinauer
hwmon has generic registers and banked registers, mostly temperature handling, and SMI/GPIO stuff. Not all LDNs are switched via register offset 0x07, make it a parameter. Add support for dumping the hardware monitor of Winbond W83627THF/THG parts with the -e option. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-30ok, another attempt to the build_opt_tbl problem:Stefan Reinauer
- create temp files and move them afterwards - remove dummy option -b - fix usage - drop implicit creation of .c file if no --option is specified. Now let's see if this fixes the issue. :-) We don't want to take 24s instead of 6s to build an image reliably (Yes, yes, I know Tiano takes over 20 minutes) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-29Copyright update by Jason Wang for freshly written sb600 code.Jason WangQingpei.wang
Signed-off-by: Jason Wang<Qingpei.wang@amd.com> Reviewed-by: Joe, Bao <Zheng.Bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Declare special commands to support the Atmel AT25F512A.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28If a chip has any TEST_BAD_* flag set, we don't even list theCarl-Daniel Hailfinger
unsupported functions, giving the user the impression that the unsupported functions are tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Add support for the AMD/ATI SB600 southbridge SPI functionality.Jason Wang
This has been tested by Uwe Hermann on an RS690/SB600 board. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28This patch fixes the ugly race condition created through build_opt_tblStefan Reinauer
running twice at the same time, overwriting its output files. This caused a depending rule to produce an object file with no symbols in it. This should silence up the regularly happening build failure messages on the mailing list since we moved to the newer, much faster server. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Add SST25VF080B flash chip support.Jason Wang
This is the first chip which uses the infrastructure for alternative erase commands, namely spi_chip_erase_60_c7(). Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Flashrom already has the following probe functions:Carl-Daniel Hailfinger
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID - probe_spi_res with opcode 0xab, usually 1 byte ID We are missing the following probe function: - probe_spi_rems with opcode 0x90, usually 2 bytes ID RDID provides best specifity (manufacturer, device class and device) and RES is supported by quite a few old chips. However, RES only returns one byte and there are multiple flash chips with different sizes on the market and all of them have the same RES ID. REMS is from the same age as RES, but it provides a manufacturer and a device ID. It is therefore on par with the probing for parallel flash chips and specific enough. The order in which chips should be detected is as follows: 1. RDID 2. REMS 3. RES Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-27The existing check in probe_spi_res() was right for SPI controllersCarl-Daniel Hailfinger
which support all commands, but may not exist. For controllers which support only a subset of commands, it will fail in unexpected ways. Even if a command is supported by the controller, it may be unavailable if the controller is locked down. The new logic checks if RDID could be issued and its return values made sense (not 0xff 0xff 0xff). In that case, RES probing is not performed. Otherwise, we try RES. There is one drawback: If RDID returned unexpected values, we don't issue a RES probe. However, in that case we should try to match RDID anyway. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: FENG yu ning <fengyuning1984@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-25msrtool: Use libpci to let system and target probes find PCI devices.Peter Stuge
And some more notes in TODO. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-24Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli.Tero O Peippola
File util/flashrom/flash.h already had correct ID for that part. Signed-off-by: Tero O Peippola <xeropp@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22msrtool: Very small fixes I made after sending out the rc1 tarball.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22msrtool: Release Candidate 1Peter Stuge
msrtool can decode MSRs and print the value of every field in human readable form. It can also be used to save a set of MSRs to a file, and at a later time compare the saved values with current values in hardware. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18Currently flashrom assumes every vendor BIOS shares our view about whichCarl-Daniel Hailfinger
SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18Check for failed SPI command execution in flashrom. Although SPI itselfCarl-Daniel Hailfinger
does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18Implement read support for the following Atmel chips:Carl-Daniel Hailfinger
AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 I double-checked the data sheets and am confident this will work. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-17flashrom: SST39VF020 TEST_OK_ PROBE READ ERASE WRITEMart Raudsepp
Tested fully on a ThinCan DBE61A Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-15The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.Carl-Daniel Hailfinger
The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-12Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E,Uwe Hermann
IT8780F, and Fintek F71863FG. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10cosmetic update for getpir. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08flashrom: SST39SF040 TEST_OK_ PROBE READ ERASE WRITEPeter Stuge
Per report from Mario Rogen. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-05The ST M25P16 chip has been confirmed to work fine for probe, read,Carl-Daniel Hailfinger
erase and write by Stéphan Guilloux. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-04Add support for 8 new chips to flashrom and fix up 2 existing chipsCarl-Daniel Hailfinger
as well. Replace age-old TODO comments with real explanations. Fixed chips: Fujitsu MBM29F400TC (ID definition) Macronix MX29F002T (chip name) New chips: Fujitsu MBM29F004BC Fujitsu MBM29F004TC Fujitsu MBM29F400BC Macronix MX25L512 Macronix MX25L1005 Macronix MX25L2005 Macronix MX25L6405 Macronix MX29F002B Straight from the data sheets, compile tested only. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03Dump ICH8/ICH9/ICH10 SPI registers in flashrom.Carl-Daniel Hailfinger
This helps a lot if we have to track down configuration weirdnesses. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03Add additional SPI sector erase and chip erase command functions toCarl-Daniel Hailfinger
flashrom. Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Drop nr/opcode_index parameter from run_opcode and search the opmenu for the ↵Stefan Reinauer
opcode instead. This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Add support for the ST M50FW002 chip to flashrom. Identification only,Carl-Daniel Hailfinger
erase/write are not implemented. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested and Acked-by: Elia Yehuda <z4ziggy@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02inteltool 82945G/GZ/P/PL Support (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31Move the nvramtool manpage to section 8 (as it's only really usable as root),Uwe Hermann
as we've done with the superiotool and flashrom manpages, too (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Allow nvramtool to build and work on FreeBSD. Tested on FreeBSD 7.Andriy Gapon
Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30Mark two more chips as fully tested (trivial).Uwe Hermann
- SST SST39SF010A - Winbond W29C011 Tested by me on actual hardware, all operations. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Flashrom support for some Numonyx parts (M25PE)Stefan Reinauer
using block erase d8 as discussed with Peter Stuge Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Enable SPI boot flash support on EP80579, which has the ICH7 register setEd Swierk
(trivial). Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Ed Swierk <eswierk@aristanetworks.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28Allow superiotool to compile and work on FreeBSD. Tested on FreeBSD 7.Andriy Gapon
Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28Mark Winbond W39V040FA" (512 KB) as fully supported, tested byUwe Hermann
Martin Stecklum <stecky@gmx.net> (both write and erase). The tests were done on an MSI MS-7065 board, so that's supported now too (wiki page will be updated). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28Add support for the Intel 82371MX (MPIIX) southbridge (trivial).Uwe Hermann
Untested, but should work just as well as the other *PIIX* southbridges according to the datasheets. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-26Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges.Uwe Hermann
Tested on PIIX3 hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-25Add support for the VIA VT82C586A/B chipset, improve documentation.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-23Add support for the ITE IT8661F/IT8770F, IT8673F, and IT8671F/IT8687R.Urja Rannikko
They all use a different init sequence than the more modern ITE Super I/Os. For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be valid. Contrary to other Super I/Os, the config port for these is _not_ hardcoded via hardware, instead it can be programmed by software, i.e. you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd. Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21Reduce serial output, otherwise flashing will fail very often (trivial).Uwe Hermann
This has been tested on hardware by me. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-19Add register definitions for W83627HF based on publicly availableAndriy Gapon
specification and local testing. Also tweak a little bit algorithm for (internal) device ID calculation: Chips from the W83627HF/F/HG/G family have an ID of 0x52 and a multitude of revisions (0x1x, 0x3a, 0x41, maybe more), chips from the W83627HF/GF family have the same device ID but revisions 0xfx. Please note that the last line of the patch simply fixes the comment about internal device ID composition (upper half of reg 0x21 is used). I chose the most conservative way of detecting W83627HF - only if reg 0x21 value matches 0xFx we skip the previous logic and keep using it for all other revisions. Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18Coding-style fixes for flashrom, partly indent-aided (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18flashrom: Allow the SiS 620 chipset to detect and read at least 256kb chips.Urja Rannikko
Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info about SiS620. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-15SB600 has four write once LPC ROM protect areas. It is not possible to writeMarc Jones
enable that area once the register is set so print a warning. Signed-off-by: Marc Jones <marcj.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-14Drop global register 0x07 for all Super I/Os (trivial).Uwe Hermann
This is useless, as it changes with each access; it doesn't convey any useful information at all. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-14Add dump support to ITE IT8726F, and add comments and a missing GPIOJosh Profitt
register to ITE IT8718F. Signed-off-by: Josh Profitt <zorn169@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-10Add ICH10 support to flashrom.Carl-Daniel Hailfinger
The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash interfaces, so this just adds the required PCI IDs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-10flashrom: Check that a filename was specified also when using force readPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-09Add Fintek F71882FG support (trivial).Uwe Hermann
Tested on actual hardware, the MSI K9AG Neo2-Digital (MS-7368). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-07Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.Mats Erik Andersson
Probing, reading, and erasing use the Jedec-routines, whereas writing resort to the recent write_en29f002a(), since also these chips use a byte wise algorithm. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01Add some more Super I/O IDs/names (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30Add an abuild command line option for -fno-stack-protect for toolchains that ↵Marc Jones
might require it. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30This patch fixes support for the AT49F002N(T) chip in the flashrom tool.Tim ter Laak
It replaces the write function to one based on write_byte_program_jedec() instead of write_page_write_jedec(), as this part does not support page programming. I have verified the NT variant to fully work now, and adjusted the test status accordingly. The N variant *should* also work with this patch, but remains untested. Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30flashrom: ST M29F040B status TEST_OK_ PROBE READ ERASE WRITEPeter Stuge
Per report from Daniel Lindenaar. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29flashrom: Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW)Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29Mark the SyncMOS S29C51002T as working (trivial).Uwe Hermann
All operations tested by me on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-27Add string support to nvramtool.Stefan Reinauer
To add a string to your cmos.layout, you need to specify type 's': #start len type unused name 416 512 s 0 boot_devices With this patch you can do $ nvramtool -w boot_devices="(hd0,0);(hd2,1);(hd3)" And FILO will attempt to load a menu.lst from any of these devices in that order. The patch is not exactly pretty, but a cleaner solution might have resulted in a complete rewrite of the tool, which I did not want. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26Activate proper support for EN29F002(A)(N)[BT].Mats Erik Andersson
Fully tested for Probe/Read/Erase/Write on EN29F002NT. Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()' are still in use, but a tailored 'write_en29f002a()' is needed due to a byte wise writing mechanism for this chip. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18fix two minor bugs in nvramtool. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-10flashrom: Winbond W49V002A TEST_OK_ PROBE READ ERASE WRITEPeter Stuge
Per report from Kevin O'Connor. Thanks Kevin! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-07flashrom: Debug print actual time base calculated by myusec_calibrate_delay()Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04This changes the python generated makefilesCarl-Daniel Hailfinger
targets/*/*/Makefile targets/*/*/normal/Makefile targets/*/*/fallback/Makefile to use a common copy of romcc, and to leave this compiler untouched by 'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ . 'make clean' in targets/*/*/ will clean romcc. Thanks to Mats for the initial idea and implementation of a tool to do this. This patch has almost the same behaviour as the original tool without having to run the tool each time. Tested for abuild-friendliness. The patch saves ~10-12 seconds for every target using romcc. For a full abuild run, this is ~20% time saved. For the first 38 abuild targets, total build time is down to 13m24s instead of 16m22s on my machine. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03flashrom: Only find "unknown .. SPI chip" if no other chip was foundPeter Stuge
This removes the false positive matches we've been seeing, and also removes the true positive match in case there is more than one flash chip and the 2nd or 3rd are unknown - but I think that case is uncommon enough to warrant the improvement in the common case. Use flashrom -frc forced read if you have the uncommon case, and/or please add the flash chip to the flashchips array. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02flashrom: SST49LF016C TEST_OK_ PROBE READ ERASE WRITEPeter Stuge
Per test report from Bari Ari. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27flashrom: SST25VF016B TEST_OK_ PROBE READ ERASE WRITEPeter Stuge
Per test report from Ward. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20flashrom: Recognize the Intel EP80579 LPC flash interface.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20split the one file, as the several printing functions will continue to growStefan Reinauer
immensly when they know more systems / cpus / chipsets Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20use seperate array for core 2 cpus (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19Add support for MSI KT4V to flashrom. The KT4V is autodetected and supportsSean Nelson
the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet). Signed-off-by: Sean Nelson <snelson@nmt.edu> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18inteltool: match cpuid before attempting to print MSRs (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-15fix typo in superiotool (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12flashrom: Fix error -EINVAL on mmap()Segher Boessenkool
Don't calculate "flash_baseaddr" until the final value of "size" is known, otherwise we end up trying to map a page right after the end of memory. Fixes #112. Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08flashrom: ST M50FW040 TEST_OK PROBE READ ERASE WRITEPeter Stuge
Per test report from Marcel Konrad. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-06Add the contents of buildrom'sWard Vandewege
packages/mkelfimage/mkelfimage-autoconf.patch packages/mkelfimage/mkelfImage-2.7-x86_64.patch to our svn copy of mkelfimage. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Jordan Crouse <jordan.crouse@amd.com> These are the original commit messages from the buildrom svn tree: ----------------------------------------------------------------------- r61 | jcrouse | 2007-11-28 13:06:23 -0500 (Wed, 28 Nov 2007) | 9 lines [BUILDROM] Fixup mkelfimage My patch makes it so all targets use vmlinux and 2.7. Including the mkelfimage patch from Yhinghai Lu. Signed-off-by: Myles Watson <myles@pel.cs.byu.edu> Acked-by: Jordan Crouse <jordan.crouse@amd.com> ------------------------------------------------------------------------ r80 | jcrouse | 2007-12-10 13:56:40 -0500 (Mon, 10 Dec 2007) | 8 lines [BUILDROM] Fix breakage in the new mkelfimage autoconf scripts Whack the autoconf scripts in mkelfimage to allow us to pass our stack protection flags in. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> ------------------------------------------------------------------------ git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02update copyright year (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02tested another intel chip (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix build warnings for buildrom (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01fix typos in config.g, and don't arbitrarily hide some build informationStefan Reinauer
(doesn't make sense in v2). For silent build, use make -s (trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21flashrom: Winbond W39V040C and MSI K8T Neo2-FPeter Stuge
W39V040C does standard JEDEC commands except chip erase so add a small driver. probe_w39v040c() prints the block lock pin status when a chip is found. The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs. Many thanks to Daniel McLellan for testing all of this on hardware! Build tested by Uwe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19superiotool: add support for SMSC SIO10N268 (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19add support for 2 new SMSC superio chips. Information is a bit ambiguousStefan Reinauer
and scattered within the datasheets. (trivial patch) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-11Fix and clean up coreboot image detection heuristic.Carl-Daniel Hailfinger
Additional compile fix for NetBSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07flashrom: Trivial SPI cleanupsPeter Stuge
While writing a new SPI driver I fixed some things in the SPI code: All calls to spi_command() had unneccessary #define duplications, and in some cases the read count define could theoretically become harmful because NULL was passed for the read buffer. Avoid a crash, should someone change the #defines. I also noticed that the only caller of spi_page_program() was the it87 driver, and spi_page_program() could only call back into the it87 driver. Removed the function for easier-to-follow code and made it8716f_spi_page_program() static. The ichspi driver's static page functions are already static. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07flashrom: Trivial indent fix in ichspi.cPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06r3415 removed symbolic constants for device IDs by accident.Carl-Daniel Hailfinger
flash.h is a database of known IDs, whereas flashchips.c is a database of chips for which support has been implemented. Keep it that way. Trivial. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06flashrom: Add AMIC A29002Andreas Thienemann
This patch adds support to the AMIC A29002 chip in its top and bottom configuration to flashrom. Additionally, the alphabetic order of the AMIC chips was fixed. The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>. A29002T PREW functionality was tested and works. This flash chip has asymmetric sector layout so it is important to use the mx29f002 driver, which does chip erase before writing, rather than am29f040b, which uses sector erase. Signed-off-by: Andreas Thienemann <andreas@bawue.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05Adding support for flashing system with Nvidia MCP67Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05flashrom: Add PCI IDs for EPIA-CNPeter Stuge
Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices with their 1106:aa08 subsystem id:s for autodetection. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03Minor cosmetics, e.g. make stuff fit in 80 chars/line etc. (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03Mark SST49LF040B as tested.Carl-Daniel Hailfinger
Thanks to Paul Seidler and Ward Vandewege for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 07:18:47 +0000