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2021-04-09util/genbuild_h: add COREBOOT_BUILD_EPOCH seconds since epochAlexander Couzens
To use SOURCE_DATE_EPOCH for the kernel build, extend genbuild_h to contain COREBOOT_BUILD_EPOCH. Change-Id: Iaa79d3e7df8101a1ba1b37a361d8992f7eab2d52 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-07util/bincfg/Makefile: change ./bincfg to $(abspath $(TARGET))Martin Roth
This change was promised as a follow-up in change ID: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9a41b46cc90684746e2b240c8ee442df1b3d7cf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-06lint: checkpatch: Only exclude specific src/vendorcode/ subdirectoriesJulius Werner
Some of the src/vendorcode/ directories are used to import a whole codebase from somewhere else which uses a completely different coding style. For those directories, excluding them from checkpatch makes sense. However, other directories are simply implementing vendor-specific extensions that were written by coreboot developers specifically for coreboot in coreboot's coding style. Those directories should be covered by checkpatch. This patch narrows the existing blanket exception of src/vendorcode/ to the amd, cavium, intel and mediatek directories (which actually include large amounts of foreign source). The eltan, google and siemens directories (which seem to contain code specifically written for coreboot) will now be covered by checkpatch. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1feaba37c469714217fff4d160e595849e0230b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51827 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06util/crossgcc: Add date to the toolchain revisionMartin Roth
With the current version method, it's not possible to determine if a different version is older or newer than the current version without digging into the repository and finding the dates for the version numbers. This change adds the commit date to the start of the toolchain version which will let us tell at a glance how old or new the toolchain is. It's not perfect because multiple toolchain commits can go in on the same day, but adding the time made the string even longer, and really doesn't help that much. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c6d27667b922dc15e7a6e132e1beff69eed839c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-06util/kconfig_lint: Drop exception for paths without quotesNico Huber
The tree is clean at the moment. Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52066 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06util: Add DDR4 generic SPD for Micron MT40A1G16RC-062E-B 16GbKevin Chiu
Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb BUG=b:184024142 TEST=none Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-05util/bincfg: Clean up MakefileMartin Roth
- Enable warnings - Enable warnings as errors - Remove debug flag -g - Add targets for all, distclean, and help - Add dependency of the bincfg file for output targets - Add all phony targets to .PHONY BUG=None TEST=Build all targets Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ic0302f663cbc931325334d0cce93d3b0bf937cc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50654 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22util: Add DDR4 generic SPD for H4AAG165WB-BCWENick Vaccaro
Add SPD support for DDR4 memory part H4AAG165WB-BCWE. BUG=b:181732562 TEST=none Change-Id: I923fcbd08875a2a581fba4b1db00a4d1c1bb11cf Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19util/ifittool: Add an option to set the FIT pointer a CBFS fileArthur Heymans
The purpose of this is to eventually move the FIT table out of the bootblock, generate it separately as a cbfs file and then have the FIT pointer point to that cbfs file. TESTED: extracted a FIT table using dd, added it as a cbfs file and see that the FIT pointer correctly points to it. Also test that trying to add a non valid FIT cbfs file results in an error. Change-Id: I6e38b7df31e6b30f75b0ae57a5332f386e00f16b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-18util/qualcomm: fix python syntax warningsBaruch Siach
Don't use 'is' and 'is not' for comparison with literals. This fixes warnings like: .../mbn_tools.py:1097: SyntaxWarning: "is not" with a literal. Did you mean "!="? if int(off) is not 0: Change-Id: Idd68acfcbd1a07cbbb9ab41d9581c4850a431445 Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-17cbfs: Move stage header into a CBFS attributeJulius Werner
The CBFS stage header is part of the file data (not the header) from CBFS's point of view, which is problematic for verification: in pre-RAM environments, there's usually not enough scratch space in CBFS_CACHE to load the full stage into memory, so it must be directly loaded into its final destination. However, that destination is decided from reading the stage header. There's no way we can verify the stage header without loading the whole file and we can't load the file without trusting the information in the stage header. To solve this problem, this patch changes the CBFS stage format to move the stage header out of the file contents and into a separate CBFS attribute. Attributes are part of the metadata, so they have already been verified before the file is loaded. Since CBFS stages are generally only meant to be used by coreboot itself and the coreboot build system builds cbfstool and all stages together in one go, maintaining backwards-compatibility should not be necessary. An older version of coreboot will build the old version of cbfstool and a newer version of coreboot will build the new version of cbfstool before using it to add stages to the final image, thus cbfstool and coreboot's stage loader should stay in sync. This only causes problems when someone stashes away a copy of cbfstool somewhere and later uses it to try to extract stages from a coreboot image built from a different revision... a debugging use-case that is hopefully rare enough that affected users can manually deal with finding a matching version of cbfstool. The SELF (payload) format, on the other hand, is designed to be used for binaries outside of coreboot that may use independent build systems and are more likely to be added with a potentially stale copy of cbfstool, so it would be more problematic to make a similar change for SELFs. It is not necessary for verification either, since they're usually only used in post-RAM environments and selfload() already maps SELFs to CBFS_CACHE before loading them to their final destination anyway (so they can be hashed at that time). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-16cbfstool: Move alignment/baseaddress handling into cbfs_add_component()Julius Werner
The --alignment flag is currently only handled by cbfstool add, but there seems little reason to not handle it for all file-adding commands (the help text actually mentions it for add-stage as well but it doesn't currently work there). This patch moves the related code (and the related baseaddress handling) into cbfs_add_component(). As a nice side effect this allows us to rearrange cbfs_add_component() such that we can conclusively determine whether we need a hash attribute before trying to align the file, allowing that code to correctly infer the final header size even when a hash attribute was implicitly added (for an image built with CBFS verification enabled). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idc6d68b2c7f30e5d136433adb3aec5a87053f992 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47823 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16util/cbfstool/ifittool: Remove dead codeArthur Heymans
The 'x' option is not set up in the getopt options. Change-Id: Ib4aa10b0ea2a3f97e8d2439152b708613bcf43db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-13cbfstool: Add support for platform "fixups" when modifying bootblockJulius Werner
To support the new CONFIG_CBFS_VERIFICATION feature, cbfstool needs to update the metadata hash embedded in the bootblock code every time it adds or removes a CBFS file. This can lead to problems on certain platforms where the bootblock needs to be specially wrapped in some platform-specific data structure so that the platform's masked ROM can recognize it. If that data structure contains any form of hash or signature of the bootblock code that is checked on every boot, it will no longer match if cbfstool modifies it after the fact. In general, we should always try to disable these kinds of features where possible (they're not super useful anyway). But for platforms where the hardware simply doesn't allow that, this patch introduces the concept of "platform fixups" to cbfstool. Whenever cbfstool finds a metadata hash anchor in a CBFS image, it will run all built-in "fixup probe" functions on that bootblock to check if it can recognize it as the wrapper format for a platform known to have such an issue. If so, it will register a corresponding fixup function that will run whenever it tries to write back modified data to that bootblock. The function can then modify any platform-specific headers as necessary. As first supported platform, this patch adds a fixup for Qualcomm platforms (specifically the header format used by sc7180), which recalculates the bootblock body hash originally added by util/qualcomm/createxbl.py. (Note that this feature is not intended to support platform-specific signature schemes like BootGuard directly in cbfstool. For anything that requires an actual secret key, it should be okay if the user needs to run a platform-specific signing tool on the final CBFS image before flashing. This feature is intended for the normal unsigned case (which on some platforms may be implemented as signing with a well-known key) so that on a board that is not "locked down" in any way the normal use case of manipulating an image with cbfstool and then directly flashing the output file stays working with CONFIG_CBFS_VERIFICATION.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I02a83a40f1d0009e6f9561ae5d2d9f37a510549a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13cbfstool: Support CONFIG_CBFS_VERIFICATION and metadata hash anchorJulius Werner
This patch adds support for the new CONFIG_CBFS_VERIFICATION feature to cbfstool. When CBFS verification is enabled, cbfstool must automatically add a hash attribute to every CBFS file it adds (with a handful of exceptions like bootblock and "header" pseudofiles that are never read by coreboot code itself). It must also automatically update the metadata hash that is embedded in the bootblock code. It will automatically find the metadata hash by scanning the bootblock for its magic number and use its presence to auto-detect whether CBFS verification is enabled for an image (and which hash algorithm to use). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41121 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12util/qemu: Add additional config file for QEMU/Q35Nico Huber
The `q35-alpine.cfg` adds a lot of PCIe devices to resemble the topology inside an Intel Alpine Ridge Thunderbolt controller. By no means could this be detected as such a controller. But having a real-world example of such a topology can help to test the allocator and other algorithms on a deeper tree. It adds two levels of PCIe switches (`alpine-root` and `alpine-1`), and two endpoints (a `pci-testdev` and an xHCI controller). It can be added to the default `q35-base.cfg` config, e.g. with: $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg Change-Id: Ieab09c5b67a5aafa986e7d68a6c1a974530408b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51329 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03util: Add new memory part to LP4x listAmanda Huang
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03util/spd_tools/lp4x: Add 2 new parts to global memory definitionMartin Roth
This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-27crossgcc: Delete conflicting, stale symbolic linkNico Huber
If a previous build failed or the build dir is still around for other reasons (e.g. buildgcc's `-t`) the symbolic link to our `bin` dir we create there is also still around and can't be created again without removing it first. Attempts to use `ln -f` also fail as the existing destination is treated as directory and a new symbolic link would be created inside. Change-Id: I7a2720b0286e33d1ba26ea01f323dbf4f8afaea0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27Revert "util/lint: Add test for documentation in util dirs"Nico Huber
This reverts commit 15e379aaf334e7931710b4208ccedf2f9ee44b0d. It triggers on directories that only contain artifacts and no checked in code. As this happens a lot when switching branches, it makes it impossible to commit new code. Change-Id: I38a86c8a5d5dc14ca5f6cba789bcb8c0fcaefb0b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27util/spd_tools: Run go fmt on all .go filesMartin Roth
This just reformats these files. go fmt should probably be run on the check-in of every .go file. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I70ced115bad42d123474b18bbff2e4c0a16f3d88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51019 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27util/spd_tools: Add Cezanne support to lp4x/gen_spd.goMartin Roth
To supply memory information for Guybrush, the lpddr4x script for generating SPDs needs to be updated for Cezanne. BUG=b:178722935 TEST=Add the part used on Majolica to the global lpddr4x json file and verify that the output is similar to the actual SPD used for Majolica. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1f522cb4a92b4fe4c26cad0689437c33ec44befe Reviewed-on: https://review.coreboot.org/c/coreboot/+/51015 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26util/autoport: Add dsdt_top.aslKyösti Mälkki
Fix required after commit cf246d5166 that added a top-level ASL file. Change-Id: Ifd3ef021a6024950021406cfbd13ccaa7bbdbce5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/lint: Check for windows line endingsMartin Roth
The codebase currently has only unix line endings, so add a lint tool to check for windows line endings. BUG=None TEST=Verify that line endings are caught both inside and outside a git repo. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I6faf99a3184e4843640fb8965f8124de0bc52ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/ectool: Update MakefileMartin Roth
- Add a help target - Add the -Wshadow and -Werror options - Add a way to disable -Werror Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0d9fe5beb3a2e103a0bf4603712c3a5ed15f93be Reviewed-on: https://review.coreboot.org/c/coreboot/+/50850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/cbmem: Update MakefilesMartin Roth
- Add a help target - Add the -Wshadow option - Add a way to disable -Werror Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icd4e5cf51d60254d274c6e5093285cd49ff1607a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/cbfstool: Update MakefilesMartin Roth
- Add a distclean target - Add a help target - Add the -Wshadow option Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie31d61bd0e28b1e228656dfa09b5ab1996868706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/bucts: Clean up Makefile to match othersMartin Roth
- Add a TARGET variable - Enable optimization and additional warnings - Add distclean target - Add help target Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8eb190abd1ab20da7dd1ae43ef0358ba91df000e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25util/bucts: Fix compiler complaints shown with -WextraMartin Roth
This fixes the following 2 complaints: bucts.c: In function ‘main’: error: unused parameter ‘envp’ error: ‘bucts_state’ may be used uninitialized in this function. The bucts_state wasn't real, but the compiler couldn't tell, so use one variable to check for modifications instead of two. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iff1aae3441ec366d272e88b6b6634980d61cb8ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/50846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20sconfig: Use get_chip_instance() to set base_chip_instanceFurquan Shaikh
Now that multiple device trees are supported (chipset, base, override), base_chip_instance parameter for override device needs to be set to the base chip instance of the corresponding device in base/primary tree. This can be achieved by using `get_chip_instance()` instead of using base_dev->chip_instance in `update_device()`. TEST=Verified that coreboot.rom generated using timeless shows no change for all boards. Change-Id: I42e3f4b83c55f3479b95dbbd7a3721558c32b1c8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18cbfstool: Replace FILENAME_ALIGN 16 with ATTRIBUTE_ALIGN 4Julius Werner
cbfstool has always had a CBFS_FILENAME_ALIGN that forces the filename field to be aligned upwards to the next 16-byte boundary. This was presumably done to align the file contents (which used to come immediately after the filename field). However, this hasn't really worked right ever since we introduced CBFS attributes. Attributes come between the filename and the contents, so what this code currently does is fill up the filename field with extra NUL-bytes to the boundary, and then just put the attributes behind it with whatever size they may be. The file contents don't end up with any alignment guarantee and the filename field is just wasting space. This patch removes the old FILENAME_ALIGN, and instead adds a new alignment of 4 for the attributes. 4 seems like a reasonable alignment to enforce since all existing attributes (with the exception of weird edge cases with the padding attribute) already use sizes divisible by 4 anyway, and the common attribute header fields have a natural alignment of 4. This means file contents will also have a minimum alignment guarantee of 4 -- files requiring a larger guarantee can still be added with the --alignment flag as usual. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I43f3906977094df87fdc283221d8971a6df01b53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18cbfstool: Ensure attributes always come last in the metadataJulius Werner
In a rare placement edge case when adding a file with alignment requirements, cbfstool may need to generate a CBFS header that's slightly larger than it needs to be. The way we do this is by just increasing the data offset field in the CBFS header until the data falls to the desired value. This approach works but it may confuse parsing code in the presence of CBFS attributes. Normally, the whole area between the attribute offset and the data offset is filled with valid attributes written back to back, but when this header expansion occurs the attributes are followed by some garbage data (usually 0xff). Parsers are resilient against this but may show unexpected error messages. This patch solves the problem by moving the attribute offset forwards together with the data offset, so that the total area used for attributes doesn't change. Instead, the filename field becomes the expanded area, which is a closer match to how this worked when it was originally implemented (before attributes existed) and is less confusing for parsers since filenames are zero-terminated anyway. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3dd503dd5c9e6c4be437f694a7f8993a57168c2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18cbfstool: Remove location pointer from parse_elf_to_stage()Julius Werner
The *location argument to parse_elf_to_stage() is a relic from code all the way back to 2009 where this function was still used to parse XIP stages. Nowadays we have a separate parse_elf_to_xip_stage() for that, so there is no need to heed XIP concerns here. Having a pointer to represent the location in flash is absolutely irrelevant to a non-XIP stage, and it is used incorrectly -- we just get lucky that no code path in cbfstool can currently lead to that value being anything other than 0, otherwise the adjustment of data_start to be no lower than *location could easily screw things up. This patch removes it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia7f850c0edd7536ed3bef643efaae7271599313d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18rmodtool: Make memlayout symbols absolute and do not relocate themJulius Werner
Memlayout is a mechanism to define memory areas outside the normal program segment constructed by the linker. Therefore, it generally doesn't make sense to relocate memlayout symbols when the program is relocated. They tend to refer to things that are always in one specific spot, independent of where the program is loaded. This hasn't really hurt us in the past because the use case we have for rmodules (ramstage on x86) just happens to not really need to refer to any memlayout-defined areas at the moment. But that use case may come up in the future so it's still worth fixing. This patch declares all memlayout-defined symbols as ABSOLUTE() in the linker, which is then reflected in the symbol table of the generated ELF. We can then use that distinction to have rmodtool skip them when generating the relocation table for an rmodule. (Also rearrange rmodtool a little to make the primary string table more easily accessible to the rest of the code, so we can refer to symbol names in debug output.) A similar problem can come up with userspace unit tests, but we cannot modify the userspace relocation toolchain (and for unfortunate historical reasons, it tries to relocate even absolute symbols). We'll just disable PIC and make those binaries fully static to avoid that issue. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic51d9add3dc463495282b365c1b6d4a9bf11dbf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-17treewide: Remove trailing whitespaceMartin Roth
Remove trailing whitespace in files that aren't typically checked. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8dfffbdeaadfa694fef0404719643803df601065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16docker/coreboot-jenkins-node: Add more tools for zephyrPatrick Georgi
To build a CrOS-style zephyr, we need a couple of u-boot tools, so add them here instead of rebuilding them on every zephyr build (which is also harder to get right because search paths are no strength of python) Change-Id: Ib95fcb644ac87c5f35f2228fe081c922452b5213 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-16util/bincfg: Fix all issuesMartin Roth
This fixes the following issues: bincfg.l: In function ‘parsehex’: error: declaration of ‘val’ shadows a global declaration bincfg.y: In function ‘generate_binary_with_gbe_checksum’: error: comparison of integer expressions of different signedness bincfg.y: In function ‘yyerror’: bincfg.y:408:28: error: unused parameter ‘fp’ bincfg.y: In function ‘main’: bincfg.y:452:15: error: unused variable ‘pos’ bincfg.y:451:16: error: unused variable ‘c’ BUG=None TEST=Build outputs and make sure they're identical. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I60039b741c226a6b6ba53306f6fa293da89e5355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/archive: Clean up MakefileMartin Roth
- Add warnings - Enable warnings as errors: - Add distclean target - Add help target BUG=None TEST=make help; make all; make all WERROR="" Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1ae8a837003491f3ab123b3761e220556258e0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-16util/archive: fix warningsMartin Roth
Gets rid of these 4 warnings: archive.c: In function ‘set_file_name’: warning: comparison of integer expressions of different signedness archive.c: In function ‘add_file’: warning: comparison of integer expressions of different signedness archive.c: In function ‘archive_files’: warning: comparison of integer expressions of different signedness archive.c: In function ‘convert_endian’: warning: comparison of integer expressions of different signedness BUG=None TEST=Build and run Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I57ee8b31bbc9e97168e3b818c4d053eadf8a4f84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-16util/amdfwtool: Clean up MakefileMartin Roth
- Add method to disable warnings as errors - Add help target - Add phony targets to .PHONY BUG=None TEST=make all; make help; make all WERROR="" Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icd0cfd3e2579c9016ebb616e371d1076a5a171b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/amdfwtool: Enable warnings as errorsMartin Roth
BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7746430c24dd052c435561236454b456bc597517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-16util/amdfwtool: Fix all warningsMartin Roth
Fixes these warnings: warning: alignment 1 of 'struct _psp_directory_table' is less than 16 [-Wpacked-not-aligned] warning: alignment 1 of 'struct _psp_combo_directory' is less than 16 [-Wpacked-not-aligned] In function 'find_register_fw_filename_bios_dir': warning: implicit conversion from 'enum _amd_fw_type' to 'amd_bios_type' {aka 'enum _amd_bios_type'} [-Wenum-conversion] BUG=None TEST=Build and verify binaries are identical. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I761d9893ac6737b42af96c4b2a57c5a4fc61ab05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-15Documentation: util/board_status/README formattingAlexey Vazhnov
Improve markdown formatting. Split paragraphs to avoid too long text. Change-Id: Ia3a74460a49f28301c5e2e3b061aeb1e0eeb6c16 Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-14util/cbfstool: Fix build in 32-bit userspaceKyösti Mälkki
Fix regression from commit 0dcc0662f3 util/cbfstool: Introduce concept of mmap_window. Use of region_end() wraps around at 4 GiB, if utility is run in 32bit userspace. The build completes with an invalid coreboot.rom, while one can find error message in stdout or make.log: E: Host address(ffc002e4) not in any mmap window! Change-Id: Ib9b6b60c7b5031122901aabad7b3aa8d59f1bc68 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-12Revert "abuild: Allow disabling mainboards"Patrick Georgi
This reverts commit 3ac3c4ebac8 ("abuild: Allow disabling mainboards"). This mechanism helped getting Chrome OS' coreboot divergence sorted out in the 2015/2016 timeframe but hasn't been used by anybody since then. Let's not encourage people to push non-working builds without good reason and discussion (the result of which could be that we re-introduce this mechanism). Change-Id: I8e2f2e1a5d4617baa49cbcb1a640a1ea270007ef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50518 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12util/superiotool: Add ITE IT8616E/IT8656E supportAngel Pons
Datasheet is not publicly available. Derive which registers to dump from IT8625E, since there are mainboards that can use either chip depending on BOM configuration. Default values are taken from an HP 280 G2 running a coreboot build that does not configure the Super I/O. Change-Id: Icc8c56e9cd19e940e85176ac51b8ef978275eb71 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-12util/superiotool: Add ITE IT8625E supportAngel Pons
Values as per "IT8625E Preliminary Specification V0.3 (For D Version)". Change-Id: Ic3ff13d93f66d09a1f2ea953736336b201a7114c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-11util/abuild: Ensure that non-Chrome OS builds are non-Chrome OSPatrick Georgi
Sometimes boards enable it by default, making the Kconfig option impossible to disable without messing with the Kconfig files. This shouldn't happen, so report on such occurrences early. TEST=Tried building GOOGLE_KOHAKU through abuild with -x, without -x and both cases after having added a "select CHROMEOS" for testing and it failed in the "without -x with select" scenario while properly configuring and passing all other builds. Change-Id: Ieb6bcbf3e9ca8cd4ced85c7c9ffaa39505f5a9b7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11util/msrtool: teach the configure script to use clangIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I5d0cbbb0c415df0d7b899cf5eb1a9a52dd98bef9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-10mb/google: order matters in mem_parts_used.txtPaul Fagerburg
* Add comments to mem_parts_used.txt to point out that the order of the entries matters when assigning IDs, so always add a new part to the end of the file. * Update existing mem_parts_used.txt to add the same comment. * No updates to Zork variants, because they use an optional ID, so the order actually doesn't matter there. BUG=b:175898902 TEST=create a new variant of dalboz, trembyle, volteer, waddledee, or waddledoo, and observe that mem_parts_used.txt has the new verbiage. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-02-09util/bincfg: Add MAC address example to gbe-ich9m.setEvgeny Zinoviev
It's not obvious how to set specific byte of a multi-byte field in the set file. Add an example (and a template) for setting MAC address. Change-Id: Iea983071682ffebd61757497d43c70cc8214043d Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-02-07util/autoport: Fix a typo in readme.mdEvgeny Zinoviev
Change-Id: Ifa1e751354c644e2ad9613253b90eb5db0a1f043 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-03amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)Zheng Bao
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-31util/vboot_lib: Add description.mdKyösti Mälkki
Fixes lint-stable-025 error. Change-Id: I4aa2b2a2ffca69f894a23d7487926016830c9e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50114 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30util/testing/Makefile.inc: Fix up license headerAngel Pons
Drop unnecessary leading empty lines in comment. Change-Id: Idc0f9d1548336dc2df2d59b18af8d717efa60b68 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-01-29docker/coreboot-jenkins-node: Add GNU parallelPatrick Georgi
Change-Id: I958e65f3c758e7e46d6b628a05009c1b4727d40a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50087 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28util/lint: Add test for documentation in util dirsMartin Roth
Make sure that any new directories added to the util directory get documentation added. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8bb415c72cf05b91c84f0a945d7767134a74c44c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48967 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28Update util.md documentationMartin Roth
This is the new output of the util_readme.sh script. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia46924474f75692192ef4b52aab714f5071f9534 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48966 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28docker/coreboot-jenkins-node: Add zephyr-sdk toolchainPatrick Georgi
There are efforts to replace Chrome EC with Zephyr. To ensure Chromebook specific Zephyr developments (that can eventually be built as part of a coreboot build just like Chrome EC now, and are built with coreboot-sdk) don't break with Zephyr's toolchain, add the toolchain to our builders so we can do some sanity checking. Change-Id: I645a298bc350ebe7651c08aea630bdc6b93856aa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-28util/docker: Split build into multiple partsPatrick Georgi
Take the test build entirely out of the image creation process. This also allows splitting up the build steps a bit, providing more break points in case some build/test fails. Change-Id: Ie05d4a09f79350fd3e5415430da1edbcb3bcb443 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28util/docker: Don't try to test-build non-existing crostools targetPatrick Georgi
Change-Id: Id6afbff1fd91744da3ba1d5e3e9aa339c46b29b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28gitconfig/test: Adapt test to current tree layoutPatrick Georgi
The test expects a README file to exist under revision control, but we converted it to markdown, together with a rename over 2 years ago in commit ee8780eb7880477. Change-Id: I7768e116a10cb373ca35fa1c874a5949dabaa111 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28util/amdfwtool: Add "all" target to MakefilePatrick Georgi
The test-tools make target requires it. Change-Id: I20819f8d587e6b3a472cdc32751e9edf505d5ba6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28docker/coreboot-sdk: clone coreboot submodules when doing test buildPatrick Georgi
Change-Id: I2315beda31bdc8edc92d21b6665eb5ebd07da2e6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-27superiotool: Add ID for Nuvoton NCT6797DClay
Test Result: clay@clay-MS-7C37:~$ sudo superiotool [sudo] password for clay: superiotool r4.13-823-g221351f81b Found Nuvoton NCT6797D (id=0xd451) at 0x4e Change-Id: I1a5f962f2fd9dc479ddbbaf5e1bebea2c7c9e03f Signed-off-by: Clay <clay.daniels.jr@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49112 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25util/board_status/board_status.sh: invoke md5 on FreeBSDIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I8d9493ce0c3fa97ea9c3c2f60a0106bb98bd8315 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49309 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25util/board_status/board_status.sh: improve mktemp behaviour on non-linux OSesIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I763b0e7c7c81a2447ed20db0a25047d106e30606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49308 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25util/board_status/board_status.sh: improve getopt detection and usage onIdwer Vollering
non-linux OSes Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: Iba50d8a8609eda974f12b0d9802e04d7371aed5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49307 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25util/board_status/board_status.sh: select the right gnu make binaryIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I4523b1b235064f89c01530b47c9cb4c3c11c9761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49306 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25util: Update all shebangs to use /usr/bin/envMartin Roth
Instead of hardcoding paths to the executables, use the version in the path. This allows the scripts to work on more systems, and allows the binary version to be changed more easily if needed. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ifcc56aa21092cd3866eacb6a02d198110ec6051d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25util/crossgcc: Remove obsolete dockerfileMartin Roth
This file was added here before util/docker existed. Anyone using this dockerfile should use the coreboot-sdk docker container instead. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7114abc9c91ba2d6fcfef80ae6e7d1a7a3d253cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22util/docker: Replace all variables in DockerfileMartin Roth
When updating the variables in the dockerfile, if there were two or more variables on a line, only the first would be updated. This fixes that issue. Change-Id: I011ccb299c7c8527b79d234075cab18be998ab43 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22sconfig: Handle smbios_slot_desc in overridetreeFrans Hendriks
SMBIOS slot information in overrridetree is not overriden if device already exist in devicetree. Add support to handle this information from override. BUG= N/A TEST= Verify generated static.c on Intel Coffee Lake CRB Change-Id: I532436aee1d71b79171463124f7b205c145d5b05 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49738 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21msrtool: fix build with gcc 10.Michal Suchanek
[ 84s] /usr/lib/gcc/i586-suse-linux/10/../../../../i586-suse-linux/bin/ld: msrutils.o:(.bss+0x0): multiple definition of `PresentTypes'; msrtool.o:(.bss+0x14): first defined here [ 84s] /usr/lib/gcc/i586-suse-linux/10/../../../../i586-suse-linux/bin/ld: msrutils.o:(.bss+0x4): multiple definition of `MsrTypes'; msrtool.o:(.bss+0x18): first defined here There should be typedefs, not variable definitions. Change-Id: I663a011e9f1fc169126570d5eac7abe82d204a90 Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2021-01-17util/lint/spelling.txt: Disable `pres`Angel Pons
It would seem that `pres` is an abbreviation for `presence`. Personally, over the last ~2.5 years, I have seen checkpatch complaints about `pres` on several occasions, and all of them were abbreviations for `presence`. Given the high false positive rate for this entry, comment it out. Change-Id: I72f1811fb1f766e7de7c4957fd9ba844c0728029 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49463 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13util/cbfstool: unbreak compilation on FreeBSDIdwer Vollering
Compilation has been broken in commit I022468f6957415ae68a7a7e70428ae6f82d23b06 Adding a missing define solved this. See https://cgit.freebsd.org/src/tree/sys/sys/fcntl.h#n319 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I3433e4c9269880d3202dd494e5b2e962757a6b87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-13util/superiotool: add IT5570E registersMichael Niewöhner
Add registers from IT5570E datsheet v0.3.1. Tested on Clevo L141CU. Change-Id: Idc764c6180e235298835d7639fcb0b562a2c21a4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48922 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12util/ifdtool: Add coreboot build system supportPatrick Georgi
When building as part of the coreboot build system, use the same mechanism as other tools (cbfstool, amdfwtool, ...) so that abuild builds ifdtool once into sharedutils instead of once per board (while avoiding other race conditions, too). Change-Id: I42c7b43cc0859916174d59cba6b62630e70287fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-12util/superiotool: Add IT8720F EC registersMichael Büchler
Registers and their default values are from the datasheet ("IT8720F", "Preliminary Specification V0.1"). Tested on an Acer G43T-AM3. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: I69987be4f5cb50b3c20f06733f30b308891d5ad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-11util/sconfig: Emit chip config pointers for PCI devices on root busFurquan Shaikh
This change emits chip config pointers for PCI devices on root bus in static_devices.h so that the config structure can be accessed directly without having to reference the device structure. This allows the linker to optimize out unused parts of the device tree from early stages like bootblock. Change-Id: I1d42e926dbfae14b889ade6dda363d8607974cae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49214 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11util/sconfig: Change __pci*|__pnp* device pointers to constFurquan Shaikh
This change updates the device pointers exposed in static_devices.h to const instead of DEVTREE_CONST. The pointer itself doesn't really need to be DEVTREE_CONST. Change-Id: I061b05d994fc5c4156ee8bddabadf940f0aeeac3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-10superiotool/nuvoton: Set NCT6791D GPIO inputs to NANANico Huber
There were several default values given for GPIO data and status registers. As all GPIO are configured as inputs by default, we can't predict the values of these registers, hence set their default values to NANA. Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Clay Daniels <clay.daniels.jr@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-10util/autoport: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-08util/amdfwtool,post: add missing distclean targetFelix Held
Without this target some spurious errors occurred when running make distclean at the top level of coreboot. Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08util/testing: remove genprof targetFelix Held
commit 8c99c27df10f6c5a120e41ffb0948e357f5a2d20 removed util/genprof, so it needs to be dropped here as well to avoid spurious breakages of the build. Change-Id: I420b5c43e2d97373a8e665f457463a06e16ecfb9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49226 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08util/crossgcc/.gitignore: Add cmakeArthur Heymans
Change-Id: I5ce346515f4468699396e214acfaa3b62f6d891d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08cbfstool: Use flock() when accessing CBFS filesJulius Werner
Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-06cpu/intel/model_206ax: Rename `cX_acpower` optionsAngel Pons
They aren't specific to AC power operation anymore. Also adapt autoport. Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06cpu/intel/model_206ax: Unify ACPI C-state optionsAngel Pons
All mainboards use the same values for AC and battery, even desktop boards without a battery. Use the AC values everywhere and drop the battery values. Subsequent commits will rename the AC power options accordingly, and will also clean up the corresponding acpigen code. This is intentional so as to ease reviewing the devicetree changes. Also update util/autoport accordingly. Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-06util/testing: Build test more of our toolsPatrick Georgi
https://qa.coreboot.org/job/untested-coreboot-files reports a bunch of untouched Makefiles, so we never even attempt to build those tools. Change-Id: I70ca658d9642b84fa8388c72ecb83327a6a74291 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-04drivers/vpd: Add VPD region to default FMAP when selectedMatt DeVillier
Currently, use of the VPD driver to read VPD tables from flash requires the use of a custom FMAP with one or more VPD regions. Extend this funtionality to boards using the default FMAP by creating a dedicated VPD region when the driver is selected. Test: build qemu target with CONFIG_VPD selected, verify entry added to build/fmap.fmd. Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-04util: Make sure all util dirs have description files at top levelMartin Roth
New util directories have been added with no description.md file. The description file for supermicro was added at a secondary level, which doesn't help a user find the util since no path was added. Move it up to the top level. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
2020-12-31util/amdfwtool: portability fixes for FreeBSDIdwer Vollering
Add the stdint.h header, and drop the GLIBC section from amdfwtool.h to build this tool on FreeBSD as well as Linux. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I295fd308b0f5e2902931f02c9455823a614976de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29util/xcompile: fix XGCCPATH handlingrnhmjoj
This patch fixes the build with an external (coreboot) toolchain. When the toolchain is not under util/crossgcc/xgcc, setting XGCCPATH to /path/to/toolchain results in the error: toolchain.inc:169: The coreboot toolchain version of iasl '<date>' was not found The reason is that the xcompile script incorrectly assumes XGCCPATH to have a trailing slash. Change-Id: Ifcc4bd2b081fa3603420dc0a8cab3b47967ebc65 Signed-off-by: Michele Guerini Rocco <rnhmjoj@inventati.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28device + util/sconfig: introduce new device `gpio`Michael Niewöhner
Introduce a new device `gpio` that is going to be used for generic abstraction of gpio operations in the devicetree. The general idea behind this is that every chip can have gpios that shall be accessible in a very generic way by any driver through the devicetree. The chip that implements the chip-specific gpio operations has to assign them to the generic device operations struct, which then gets assigned to the gpio device during device probing. See CB:48583 for how this gets done for the SoCs using intelblocks/gpio. The gpio device then can be added to the devicetree with an alias name like in the following example: chip soc/whateverlake device gpio 0 alias soc_gpio on end ... end Any driver that requires access to this gpio device needs to have a device pointer (or multiple) and an option for specifying the gpio to be used in its chip config like this: struct drivers_ipmi_config { ... DEVTREE_CONST struct device *gpio_dev; u16 post_complete_gpio; ... }; The device `soc_gpio` can then be linked to the chip driver's `gpio_dev` above by using the syntax `use ... as ...`, which was introduced in commit 8e1ea52: chip drivers/ipmi use soc_gpio as gpio_dev register "bmc_jumper_gpio" = "GPP_D22" ... end The IPMI driver can then use the generic gpio operations without any knowlege of the chip's specifics: unsigned int gpio_val; const struct gpio_operations *gpio_ops; gpio_ops = dev_get_gpio_ops(conf->gpio_dev); gpio_val = gpio_ops->get(conf->bmc_jumper_gpio); For a full example have a look at CB:48096 and CB:48095. This change adds the new device type to sconfig and adds generic gpio operations to the `device_operations` struct. Also, a helper for getting the gpio operations from a device after checking them for NULL pointers gets added. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-23Makefile: Add $(xcompile) to specify where to write xcompileRaul E Rangel
This file was being written to the root src directory. It is the only file being written to src during a normal build, while all others are being written to $(obj). I added a new variable to allow specifying the xcompile path. This allows generating a single file if building multiple boards. I also moved the default location into $(obj) so we don't pollute the src directory by default. I also cleaned up the generation of xcompile by removing the unnecessary eval and NOCOMPILE check. I also left .xcompile in distclean so it cleans up stale files. Since .xcompile is written into $(obj), `make clean` will now remove it. The tegra Makefiles are outside of the normal build process, so I just updated those Makefiles to point to the default xcompile location of a normal build. The what-jenkins-does target had to be updated to support these special targets. We generate an xcompile specifically for these targets and pass it into the Makefile. Ideally we should get these targets added to the main build. BUG=b:112267918 TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-21amdfwtool: Add support of cezanne and renoirZheng Bao
Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17util: Modify LPDDR4 spd_tools to generate SPDs for ADL boardsAmanda Huang
Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. BUG=b:173132516 Change-Id: I4964ec28d74ab36c6b6f2e9dce6c923d1df95c84 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48526 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17autoport: Add a license header to non-empty filesIru Cai
Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45464 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14src/lib: Add Kconfig option for SPD cache in FMAPMatt DeVillier
Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>