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* Add Makefile dependency to source file
* Add argument support
* Add help support
* Print usage on wrong arguments
* Add support for parsing VBT binary file
* Add support for parsing PCI Option ROM
* Add support for writing VBT binary file
* Add support for patching PCI Option ROM
* Keep support for accessing legacy VGA area Option ROM
* Keep support for dumping VBT contents to stdout
Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed.
The required arguments have been changed:
./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename]
SOURCECMD set the VBT source. Supported:
inlegacy : Legacy BIOS area at phys. memory 0xc0000
invbt : Read raw Intel VBT file
inoprom : Read VBT from Intel Option ROM file
DESTCMD set the VBT destination. Supported:
outdump : Print VBT in human readable form
outvbt : Write raw Intel VBT file
patchoprom: Patch existing Intel Option ROM
Any combination of SOURCECMD and DESTCMD is possible.
Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Until now, autoport used to create a dummy "romstage.c", then write
romstage code to "early_southbridge.c". While it works, it makes more
sense to write to "romstage.c" instead, as virtually all mainboards do.
Change-Id: If9f9375f9a659e7e685de5f884163813261fa656
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28851
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, an entry being removed is cleared only if the next entry
is also null or deleted.
This patch ensures the entry being removed is cleared regardless of
the next entry type.
BUG=chromium:889716
BRANCH=none
TEST=Run cbfstool bios.bin remove -n ecrw.
Verify bios.bin has 0xFF in the space of the removed entry.
TEST=Run cbfstool bios.bin remove -n fallback/payload (located at the end).
Verify fallback/payload is removed.
TEST=Run sign_official_build.sh on recovery_image.bin. Extract
firmware contents from chromeos-firmwareupdate in the resigned image.
Run 'futility vbutil_firmware --verify' for vblock_A's and FW_MAIN_A
extracted from bios.bin. See the bug for details.
Change-Id: I62540483da6cc35d0a604ec49b2f2b7b11ba9ce5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/28886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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One occurence of this parameter was changed from LBROOT to CBROOT in
f8ee1806ac ("Rename almost all occurences of LinuxBIOS to coreboot.").
Change the others, too.
Change-Id: Ic0da24c32cd6d2f0577de037b5463c800f455786
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This board doesn't support the newest RISC-V Privileged Architecture
spec (1.10), and it's based on an FPGA so it's a moving target.
Now that there's actual RISC-V silicon out there (from SiFive),
mb/lowrisc/nexys4ddr will only continue to bitrot.
Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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They allow reducing the visible set of options to remove clutter.
Change-Id: I18c953c7feae23c0752392a2bf8f49783c17310e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since CBMEM console became a ring buffer, logs from several boots can be
stored. We are only interested in the current boot.
> -c | --console: print cbmem console
> -1 | --oneboot: print cbmem console for last boot only
For CBMEM time stamps only the time stamps of the current boot are
stored, so only the commands for the CBMEM console need to be adapted.
Change-Id: I18caa4aeebbd5576b9e218d176a7db5a8e868b74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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For devices supporting both Linux and Windows, we may find some ACPI
devices that only need drivers in Linux and should not even be shown in
Windows Device Manager UI.
The new 'hidden' keyword in device tree 'device' statement allows
devices sharing same driver to call acpi_gen_writeSTA with different
values.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: Iae881a294b122d3a581b456285d2992ab637fb8e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.
Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.
Further changes are needed in the bootblock
Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Change-Id: Icbf21b02d3092815bbe876eceea72ebba8dd54da
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This SuperIO is supported by coreboot and used in two Asus boards. However,
superiotool was lacking a register dump for this chip. Add the corresponding
data from datasheet W83667HG-B revision 1.3 into superiotool.
The SuperIO's datasheet was obtained by requesting it to Nuvoton.
Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Otherwise it reduces its expectations on what as and ld take in terms
of arguments, which breaks some edk2 related builds because tons of
-I$path_to_stuff arguments aren't passed along.
Change-Id: I53f87442de03d5ead8a6632d3102d5502065b828
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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- Check payloads, the root Makefiles and toolchain.inc
- 3rdparty is already not checked, so remove
- The marks around COPYING, LICENSE, and README were not needed
- Skip checking .ico files
Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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On FreeBSD, this test was failing with the error:
"grep: Argument list too long"
I found that changing this to other forms takes MUCH longer, so I left
the original method mostly unchanged except for moving the include &
exclude lists into variables.
Currently, I'm setting all non-linux operating systems to use the second
version. I'll update that if I find other that other OSes support the
first.
Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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When building the toolchain under BSDs, this missing backslash is
needed.
Change-Id: I40b0adaa73b241713493fd74f24c93f85e7aabbe
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28362
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I045383eedbcf438270e9c64329a8d910bb941ab8
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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FreeBSD doesn't have bash in /bin, so use env to find it. This is
already done in many other scripts that are used in the actual build
path.
Change-Id: If6fb6bc3c55835e2144599fea1cdb2f7abefb0fc
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
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Change-Id: Ibfcb870bb6e7ed747f8875520ab094def49e53cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ia9f0f1f527476900e6c54c60508600e16bea786f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I6967a106ce1286d633ddeeb041f582e65f9ea78c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: If906e230c0cb71fc3cd283aeb85f8d1338c303c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I36ed2c33f9bed3e640871283c2cb163d6800d1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I0a704cba80d0439ae95db34a6b73df7be5b3b862
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28290
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I53ddff302681737006f40ca8b79ec0735f1e6e45
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I62fed1084efc3224c9563619d57fbdc5040ddbbc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I05ccb5a9a861fe44efec794aafe1805062543d53
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/27776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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According to the datasheet (rev. 1.6) there is no SP2 (apart from
some typos) and the IR is actually implemented as SP3 in LDN 0x16.
Additionally, there is LDN 0x15 to set up CIR-specific options of the
IR serial port, which was missing as well.
Change-Id: I34d90d8c44f11a4f62ccc4b836409cc443fb7952
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since ifdfake has been deprecated in favor of better alternatives, there
is no need to support it any further. Remove it from "util/", as well as
any leftover references in other files.
Change-Id: I45fe3d9fd606a61d5c3b9d0e6489a1df6d6510f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With Alpine base, use pip to install Sphinx 1.7 and Sphinx-autobuild
Alpine, a 4.5MB base, is used over Debian Stable, 101MB, to cut down the
total size of the docker image.
Change-Id: I53f246206458b1de34cd7f3a42481b91ca285ff0
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Idce2587a87c5e0677a4571b59ef40e5486c22da9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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`superiotool` follows its own style (e.g. lot's of missing spaces
and odd placement of braces in the register descriptions).
Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28214
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I13c5464cd0b5bc9c21d7b4831a0b7fdd9fbc85c6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This allows us to add encoding information.
Change-Id: Ic9a12a13f11fd22eeec96fbcca6b706312876b07
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27874
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Port the newest feature of me_cleaner to ifdtool
(https://github.com/corna/me_cleaner/ , Discussed in
https://github.com/corna/me_cleaner/issues/53 ) to
set AltMeDisable (or HAP for skylake/ME11) bit to the
IFD to disable ME.
In this commit I use (ifd_version >= IFD_VERSION_2) to
judge whether HAP instead AltMeDisable should be set,
since this condition is only fulfilled on skylake
or newer platforms.
This feature needs to guess ich revision, which needs
guess_ich_chipset() from flashrom to be ported here.
Routines to dump those bits are also added.
Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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acpidump now creates dumps with 4 spaces instead of 2 in front of the hex dump,
so be a bit smarter about the input with regexp.
Tested with X220 autoport logs: Still creates the same coreboot code.
Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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No idea where the escaped parentheses come from but they
are no good. Without this patch I see errors with bash and dash:
./buildgcc: line 1198: (: command not found
./buildgcc: line 1199: (: command not found
The patch uses curly brackets for grouping since they don't
launch a subshell - unlike using unescaped parentheses which
would work too.
shellcheck is happy with either variant (and the original one(!)).
Change-Id: I44fbc659f5b54515e43e85680b1ab0a824b781a7
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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"acknowledgement" is not commonly used but correct.
Change-Id: I0aa469d77904d65288f5b7133bec10be3688a596
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Taken from Linux upstream commit ffe075132af8b7967089c361e506d4fa747efd14
Change-Id: I43d09a912fafe896c045df080c0f75fe6d908087
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28046
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Comment out 'sepc' and add a comment about it at the top so that it
doesn't get added back in accidentally in a future update.
Change-Id: Iaa909d97d0d97d7bf0799e48fc237a9673d549aa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Using recent versions of parecord produces the following:
Failed to open audio file.
According to the manual:
-r | --record
Capture audio data and write it to the specified file or to STDOUT if none is specified. If the
tool is called under the name parec this is the default.
so we suggest parec instead.
Change-Id: I8b821df67b10e9d6533c4cbe19c646c84d436c27
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
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Change-Id: Ie3a6a777f5b667e881a4462bdd44a34dbace5520
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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RISC-V has a register named 'sepc' but checkpatch identifies it as a
misspelling of 'spec'. Remove it from the list.
Change-Id: I7b092d6f04e28fba36095c607bc59346fb5c605d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I109f620bb644c3979ae297bdf544d295cdbac57f
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The Upper Map section in the descriptor contains a database of flash
chips (VSCC Table). Its offset is located at a fixed offset from
the beginning of the image. ifdtool falsely calculates the offset
from the descriptor signature which has moved by 16 bytes with
step b of the Ibex Peak (5 series) chipset. This produces bogus
output for all chipsets older than that.
This patch corrects the behavior by calculating the offset of
flumap by adding 4096 - 256 - 4 to the start of the image.
Change-Id: I14f029fe702c129dfd8069a58fbd41113700f7ef
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Check if an argument is given and if not print the usage.
Check if all arguments are handled by getopt and if not print the usage.
Change-Id: I40dbd2a51d018eb549e9b2fa4365b3e4f9355bff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
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Check if all arguments are handled by getopt and if not print the usage.
Change-Id: Iccbb65ca768a62791af54afd9b7903495bc690af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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To install this hook, run
make install-git-commit-clangfmt
This will install a pre-commit-msg hook that runs clang-format
on all .c and .h files that are staged.
It will add a clang-formatted-by: <git username>
line to the commit message to indicate that clang-format
was run on the files and that further processing of them
is not needed.
Change-Id: I1773f55b5b4677dad8f4bea017b6328fd93df20c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27779
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add short explanation of Utility list
Change-Id: I5fc45ebe29cd42c1aa18c59dabc3ac3db3107bd7
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Fix 6 new errors found by shellcheck 0.4.6
SC2155: Declare and assign separately to avoid masking return values.
4 x SC2086: Double quote to prevent globbing and word splitting.
SC2196: egrep is non-standard and deprecated. Use grep -E instead.
One of the SC2086 errors is masked because it needs word splitting.
Change-Id: I7f869e6d208f7247f739619c538be6075b802719
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
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- Use TARGET variable for location of passing/failing boards files.
This should better handle the directory, wherever it is.
- Don't save make.log location if make.log is being deleted.
Change-Id: I28e55feef85c9b642ac5ff70ecef113cf7978707
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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* Read and print the TCPA ACPI log.
Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/26244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: Iefeb47bca3676a1f807b7a66b74a07491e351362
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Descriptions are taken from the files themselves or READMEs. Description
followed by a space with the language in marked up as code.
Change-Id: I5f91e85d1034736289aedf27de00df00db3ff19c
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Bash script to concatenate description.md files into ./util/README.md
and Documention/Util.md
Change-Id: I015ae6816ea74cacb7f0332fda2c3ebef205c1e2
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27564
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
When extracting a payload from CBFS, ignore compression fields for
these types of payload segments:
- PAYLOAD_SEGMENT_ENTRY
- PAYLOAD_SEGMENT_BSS
- PAYLOAD_SEGMENT_PARAMS
These types of payload segments cannot be compressed, and in certain
cases are being erroneously labeled as compressed, causing errors
when extracting the payload.
For an example of this problem, see creation of PAYLOAD_SEGMENT_ENTRY
segments in cbfs-mkpayload.c, where the only field that is written to
is |load_addr|.
Also, add a linebreak to an ERROR line.
BUG=https://ticket.coreboot.org/issues/170
TEST=cbfstool tianocore.cbfs extract -m x86 -n payload -f /tmp/payload -v -v
Change-Id: I8c5c40205d648799ea577ad0c5bee6ec2dd7d05f
Signed-off-by: kitching@google.com
Reviewed-on: https://review.coreboot.org/27520
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
This fixes most of the simpler shellcheck errors in shellcheck 0.4.6.
There are still a few warnings left that weren't simple to fix or
would have required more testing before I was confident in them.
Change-Id: I79ab3614cc1d69d3dfe1e0374e930313f2011cbf
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
- Add the Do-not-assume-glibc-glob-internals patch to fix segfaults.
- Update glob_interface_v2 patch to the patch directly from the
make git repository instead of translating it. This gives better
attributution to the original author.
Change-Id: Ibc936fc00925a4ca2170a6f5dca7c2b8d8d62f02
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
- Exclude build flags that generate warnings when scanbuild is running
- Add the SCANBUILD_ARGS variable to abuild so we can pass in arguments
to scanbuild.
- Set the default scanbuild argument to -k (--keep-going) so that even
if an error occurs it continues with the scan. This is similar to what
we do with coverity runs.
Change-Id: I82e7c13d7fd7432b43c17a31834ec82fca158a07
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
- Create a new target, docker-jenkins-attach, to access the running
jenkins server
- Update docker-shell target to set term & size.
Change-Id: Ifa67afb62d4a216281ebece405e9b26fd4d14622
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27494
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Without the second set of braces it fails (due to -Werror) with
"suggest braces around initialization of subobject"
Change-Id: I63cb01dd26412599551ee921c3215a4aa69f4e17
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27551
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We don't block commits for failing checkpatch in gerrit, and we
shouldn't block them here. This allows checkpatch to still run, so
users can see the issues, but won't prevent the commit.
Adds a delay if checkpatch fails so that the issues can be seen.
Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/27534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Some types of payload segment headers do not use all fields.
If these unused fields are not initialized to 0, they can
cause problems in other software which consumes payloads.
For example, PAYLOAD_SEGMENT_ENTRY does not use the compression
field. If it happens to be a non-existent compression type,
the 'cbfstool extract' command fails.
BUG=https://ticket.coreboot.org/issues/170
TEST=cbfstool tianocore.cbfs create -s 2097152 -m x86
cbfstool tianocore.cbfs add-payload -f UEFIPAYLOAD.fd -n payload -c lzma -v
xxd tianocore.cbfs | head # visually inspect compression field for 0
Change-Id: I359ed117ab4154438bac7172aebf608f7a022552
Signed-off-by: kitching@google.com
Reviewed-on: https://review.coreboot.org/27540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The linux trampoline was modifying the existing GDT
to add the 0x10 and 0x18 descriptors for Linux.
This will not work when the existing GDT is in ROM.
Change the code to set up a new GDT in what we know to be
RAM.
Tested by booting a linux payload. The main reason this works
is that Linux almost immediately loads its own GDT and then
segment registers. This GDT is a very temporary bridge.
Note that none of this change used to be necessary; the coreboot
GDT was originally compatible with Linux (ca 2000);
then Linux changed.
Change-Id: I13990052fbfd6a500adab8a2db8f7aead1d24fa6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Even though we were setting V=1 in the build, this wasn't getting passed
to abuild, so the builds there didn't have additional debug information.
That made it difficult to debug issues on the builder. This sets the
verbose flag for abuild if V=1 is set.
Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Because earlier versions of debian set /dev as a standard tmpfs
filesystem, that was a simple place to build. Now, this has been
changed and /dev isn't a standard tmpfs that will grow to 50% of
memory. It's a fixed, very small size, and can no longer even be
resized.
Because of this, create a new directory to build in and add it to
/etc/fstab. Mount it when the container is started.
As long as we're at it, make the other build directories (ccache
and slave-root/workspace) tmpfs as well. The builders we're using now
have plenty of memory, so don't write any of the files to disk.
Update the Makefile to get rid of all references to ccache directory.
Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
In case multiple FMAP regions are specified, print the FMAP name.
Useful if VBOOT is enabled and multiple CBFS are printed.
Change-Id: Id6f29ebeda8a9bde6dfe39362e0f2a5e33c86b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26862
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Convert Cavium's BDK devicetree blob to a static C file.
The resulting file must be included in mainboard folder to provide
board specific configuration values to BDK functions.
Example call:
python devicetree_convert.py --in sff8104.dtb --out bdk_devicetree.c
Change-Id: I76a5588aefe4f680228eca46a0e4dba7e695931c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26228
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- Update stable directories
- Remove duplicated directories
There are currently 220 files that still need to have headers added or
be excluded from the lint-000-license-headers test.
Change-Id: I40046a2fb7359262b130f6813eda1f2c30916b46
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
In Windows Cygwin enviroment, compiler reports
redefinition error at cbfstool/ifwitool.c
on _packed and __aligned.
Skip new defines when vales are already defined.
Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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commit c1072f2 [cbfstool: Update FIT entries in the second bootblock]
incorrectly changed the value of type_checksum_valid for microcode
entries from FIT_TYPE_MICROCODE to 0, breaking microcode loading on
Skylake/FSP1.1 devices (and others?). Correct this by reverting to the
previous value.
Test: build/boot google/chell, observe FspTempRamInit no longer fails,
device boots as expected.
Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27266
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Also update patches as necessary.
Change-Id: I1e8074954d5d7a4eff590abb7439e9be7d3762aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25997
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Copied from the GNU make repository
author Paul Smith <psmith@gnu.org>
commit 48c8a116
configure.ac: Support GLIBC glob interface version 2
Change-Id: Id70a2b98dad6349ee56985d8dd6d4f0d87b470e6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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With -D, the newly built toolchain isn't installed into $prefix/...
but into $DESTDIR/$prefix/... while being built for $prefix alone.
This is useful for distributions, but it breaks down when the build
host already has the toolchain installed in $prefix without proper
build isolation (cf. gentoo):
In such cases libgcc etc are built using the new compiler (as gcc's
build system is smart enough to state the path explicitly), but that
compiler then uses its regular algorithm to determine the path to as,
ld, ...
That makes it use the tools from $prefix, which might differ in formats
(assembly, certain object file flags, ...): nds32le-elf in particular
has rather unstable formats still, and so new compilers can't work
with old binutils.
The approach to deal with this is to take an unused path that's
specified by gcc's build system ($out/gcc/$arch/$version) and symlink
it to the new toolchain - these explicitly given directories take
precedence over the default search path, and so the new binutils
are used.
Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27241
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Once a second bootblock has been added using topswap (-j)
option, Update the entries in second FIT using -j option with
update-fit command.
Additionally add a -q option which allows to insert the address of
a FMAP region (which should hold a microcode) as the first entry in
the second FIT.
BUG=None
BRANCH=None
TEST= Create ROM images with -j options and update FIT using -q option.
example:
./build/util/cbfstool/cbfstool coreboot.tmp create \
-M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY
build/util/cbfstool/cbfstool coreboot.tmp add \
-f build/cbfs/fallback/bootblock.bin -n bootblock -t \
bootblock -b -49152 -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \
-n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16
build/util/cbfstool/cbfstool coreboot.tmp. update-fit \
-n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A
Also try the failure scenarion by providing invalid topswap size.
Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/26836
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add an option '-j' which takes the size of topswap boundary.
This option serves both as a bool and a size for creating
a second bootblock to be used with topswap feature in Intel CPUs.
'-j' is also used in conjunction with add-master-header to
update the location of cbfs master header in the second bootblock.
BUG=None
BRANHC=None
TEST=add bootblock entry to the image with -j option specifying different
topswap sizes and also use the -j option for add-master-header.
Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22537
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are many boards in coreboot which support multiple
variants. When abuild is used to compile a single target, it builds
all its variants. If a target has 5 variants, then abuild takes nearly
10x the time to compile all variants of the target. This change adds
an option -b/--board-variant to enable abuild to compile only a single
variant of the target.
TEST=Verified:
1. abuild builds all variants of the target if -b option is not
provided.
2. abuild builds a single variant if -b option is provided.
3. abuild prints appropriate error message if invalid variant name is
provided.
Change-Id: I3781568c6409c5ec2610a8386a21d86037428e7f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
"ops" field was used in device structure only to add
default_dev_ops_root for root device. It was always set to NULL for
all other devices. This change gets rid of ops field from struct
device and instead hardcodes default_dev_ops_root in pass1 for root
device.
BUG=b:80081934
TEST=Verified that static.c generated with and without this change is
exactly the same.
Change-Id: I0848788610c2ed27274daf4920de3068a9784d4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support to allow variants to override the devices and
properties in base device tree by providing an override device
tree. It works as follows:
1. Both base and override device trees are parsed from provided input
files.
2. Walk through the trees in lockstep fashion using depth-first
traversal checking if a node in override tree has a matching node in
base tree.
- If matching node is found, then update the properties of base node
using the override node. Continue walking the children of the nodes.
- If matching node is not found, then copy the entire override
subtree of the node under the current base parent. In addition to
that, chip instance pointers of the nodes in override tree need to be
updated if they were pointing to the override parents chip instance.
Since chip always expects a device to be present, it leads to a
side-effect that overriding chip registers requires that a device is
always provided for the chip in the override tree as well.
BUG=b:80081934
Change-Id: I6604e4f8abe3fc48240e942fea32da96031e1e46
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27206
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change allows sconfig utility to accept an extra optional
parameter to specify override device tree that can be used to override
the properties or add new devices in addition to that provided by base
device tree. This is helpful for variants that share most of the
devicetree but have to override certain registers or add some devices
which might not be applicable to base devicetree.
In order to support the override devicetree, following changes are
made in this CL:
1. override_root_dev and override_root_bus are provided.
2. main() function is updated to accept an optional argument.
3. If override device file is provided, then parse_devicetree is
called for override_devtree as well.
This change in itself does not provide the override feature. It is
only a small step towards the final goal. The override devicetree
parsed by sconfig is currently unused.
BUG=b:80081934
Change-Id: I477e038c8922ae1a9ed5d8bf22a5f927a19a69c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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From checkpatch output, look for keywords starting with 'ERROR:' &
'WARNING:' .
Also check for keywork ': FILE:' instead of the same without the
colon (:).
BUG=None
BRANCH=None
TEST=Check if patch https://review.coreboot.org/#/c/coreboot/+/22537/21
is processed & json output is generated properly.
Change-Id: Ib690ab34a1ffabc4f83642634fd34beea16a64dc
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/27170
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Recent patches in coreboot have fixed the freeze issues related to the
use of me_cleaner on Nehalem.
However, at least on the Lenovo X201, with me_cleaner some PCIe devices
(like the SATA and USB controllers) disappear. In particular, setting
the AltMeDisable bit ("-S" or "-s" flag) makes them disappear
completely, while unsetting it makes them disappear only during cold
boots.
This kind of behaviour was already observed by Youness Alaoui on the
Purism Librem laptops ([1]), and it seems related to some required
board-specific PCIe configuration in the ME's MFS partition.
For this reason, on the Lenovo X201, "-w EFFS" has been added to the
me_cleaner arguments, which whitelists the MFS-equivalent partition for
ME generation 2. This fixes all the issues, and the PCIe devices work as
expected.
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/27178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Some older CPUs have a fixed size of 2048 bytes for microcode total size.
Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27090
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.
Intel Document 328904 is the datasheet for this PCH.
Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan@gmail.com>
Reviewed-on: https://review.coreboot.org/27168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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* Add LinuxBoot support
* Add u-root mode
* Download kernel and u-root from upstream sources.
* Add customization options
* Clean kernel only if directory exists
Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23071
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The endian conversion function be32toh() is defined in
src/include/endian.h, however this file is not used for cbfstool
compilation. Currently the one provided by the host is used and if the
host does not provide this endian.h file, the build will fail.
However, we do have endian conversion functions in commonlib/endian.h
which is available for cbfstool compilation.
Switch from be32toh() to read_be32() in order to avoid relying on a
host provided include file.
We use functions from commonlib/endian.h already in cbfstool.
Change-Id: I106274cf9c69e1849f848920d96a61188f895b36
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/27116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.
Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.
Starting at this point a CBFS payload/ can be either of type FIT or SELF.
Tested on Cavium SoC.
Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Move generators for the board status report and the kconfig options
report into a common directory and wrap them in a docker container.
Also rework to emit HTML not wiki syntax.
Change-Id: If42e1dd312c5fa4e32f519865e3b551bc471bc72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of checking each directory in series, kick off the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder by 60%.
This could probably be sped up even more by splitting up src/mainboard
into smaller sections.
This method does skip a few control files at the top level - .gitignore,
.checkpatch.conf, gnat.adc, etc. These could be added to the list of
files to check, but I didn't think it was needed.
Change-Id: I171977e713a9956cf4142cfc0a199e10040abb35
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In preparation to allow devicetree overrides, it will be necessary to
use the same parsing functions to prepare two separate parse
trees. This change does the following things:
1. Updates root device and bus names to add base_ prefix.
2. Adds a function parse_devicetree that sets the root_parent and
linenum before calling yyparse().
3. Updates all uses of root_dev to refer to the next base_root_dev.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built using
abuild is the same with and without this change.
Change-Id: I403a90c1ebf07ac66115ddfe137daf0980dc1a18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of checking each directory in series, kick off all the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder from 31 seconds to 6.
Change-Id: I1252a68a723370389d399f3d1a2aff3fad64c365
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Copy the script `scripts/config` from Linux (commit 427fbe89 (Merge
branch 'next' of
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux)) into the
newly created directory `scripts`. Here is the original commit message
from 2009.
> commit 8e54701ea85b0ab0971637825a628f5aa2b678a4
> Author: Andi Kleen <andi@firstfloor.org>
> Date: Sat Jan 3 03:21:41 2009 +0100
>
> kconfig: add script to manipulate .config files on the command line
>
> I often change single options in .config files. Instead of using
> an editor or one of the frontends it's convenient to do this from
> the command line. It's also useful to do from automated build scripts
> when building different variants from a base config file.
>
> I extracted most of the CONFIG manipulation code from one of my
> build scripts into a new shell script scripts/config
>
> The script is not integrated with the normal Kconfig machinery
> and doesn't do any checking against Kconfig files, but just manipulates
> that text format. This is always done at make time anyways.
>
> I believe this script would be a useful standard addition for scripts/*
>
> Sample usage:
>
> ./scripts/config --disable smp
> Disable SMP in .config file
>
> ./scripts/config --file otherdir/.config --module e1000e
> Enable E1000E as module in otherdir/.config
>
> ./scripts/config --state smp
> y
> Check state of config option CONFIG_SMP
>
> After merging into git please make scripts/config executable
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Change-Id: Ie32a4459398df8694956dd644f38692017a26388
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26243
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib417f435011f0331a1b0228734874ef0a62fb587
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This also removes a "chapters mode" that we never used.
Change-Id: Ib301e2f4db0b9678081fa987a5dcc7108bb103a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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SoCs from Skylake on have many settings as so called private con-
figuration registers (PCRs). These are organized as 256 ports with
a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's
BAR to access them.
Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19593
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Most things still need to be filled in, but this will allow us to build
boards which use this SOC.
BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26659
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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