coreboot.git - my copy of coreboot

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2020-05-28	testing: Add unit tests to what-jenkins-does procedure	Patrick Georgi
	They're not added as a dependency, even though that should be possible, because we want the build tests to run even when the unit tests fail. Change-Id: Ia3391d7b289160178fa773dfd7b7c51c6ef77805 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28	util/mb/google: remove zork template	Paul Fagerburg
	The templates for the zork reference boards are still being actively worked on in the trembyle-bringup branch. Remove the zork template from the main branch to avoid confusion when trembyle-bringup is merged. BUG=b:157099580 BRANCH=none TEST=N/A Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I0ff9de959c7b2646b90e68df05f0b2e9bdd60cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-28	util/lint: Check for SPDX identifiers by default	Jacob Garber
	The majority of the codebase has been converted to use SPDX identifiers now, so let's enforce those by default. The only exceptions are src/include and src/lib, which are not being checked since many of the files there do not have license headers at all. Files with custom licenses that aren't covered by SPDX can be listed as exceptions at the top of lint-000-license-headers. Change-Id: Ie6642153793d5735c74c5950bc9e27ee7eecacbc Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41602 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28	docker/coreboot-jenkins-node: Add meson and ninja	Patrick Georgi
	Our jenkins instance is also used for flashrom, which can be built with meson, a mode that we want to be able to test, so add that. ninja can be used as a backend to both meson and cmake (which coreboot will use to build cmocka for its unit tests) and may provide some additional coverage. Plus it's tiny but fast. Change-Id: If454164852303144eaa72c4071c03ee89e863318 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-27	util/apcb: Use python3 for apcb_edit.py	Raul E Rangel
	The code was written on a workstation that has python pointing to python3. BUG=b:157140753 TEST=Built trembyle and was able to boot to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I181d87aad1ffb10e12f8ffd7513318f6d6bcbc3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41739 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-25	drivers: Use SPDX identifiers	Jacob Garber
	Convert the remaining files in src/drivers to use SPDX identifiers. int15.h and default_brightness_levels.asl did not have license headers, but they were both copied from other GPL2 files, so they should be under the GPL2 as well. ne2k.c and drm_dp_helper.h are licensed under custom BSD-like licenses that do not have an SPDX equivalent, so they are added as exceptions to the license header lint. Change-Id: I87fb1c637b8d11b0463f7c19f70b847413e14aed Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-21	util/amdfwtool: Fix MAX_PSP_ENTRIES value	Rob Barnes
	Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have the ability to add. BUG=b:150862063 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I64eccfa28839768788f53327caf187a564842162 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18	util/apcb: Add apcb_edit tool	Rob Barnes
	On the Picasso architecture, the PSP is responsible for setting up DRAM before releasing the x86. The APCB (AGESA PSP Configuration Block) contains multiple SPDs and the GPIO numbers used to select the correct SPD. Since the source to build the APCBs is not public, it can't be built as part of the coreboot build. To work around this problem, we use a template APCB and inject the relevant information. BUG=b:147042464 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18	util/cbfstool: fix buffer over-read	Philipp Bartsch
	Fix unterminated array. When looking for a type not specified in filetypes (cbfs.h:204), the loop in lookup_name_by_type (cbfs_image.c:60) will run into a buffer over-read. Found-by: AFL++ 2.64d rev 1317433 Signed-off-by: Philipp Bartsch <phil@grmr.de> Change-Id: Ib82bb92e82b09fa1e26b9ca34529ec7b98e8f7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41421 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18	util/autoport/bd82x6x.go: Drop unused includes	Elyes HAOUAS
	Change-Id: Ifc0bf18dedc112e346062e0e0e988ac102991bb8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40826 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18	util/release: Check that HEAD isn't used as reference	Patrick Georgi
	genrelnotes moves the tree between commits and so a relative location like HEAD isn't stable. Since I ran into the HEAD issue while preparing for two consecutive releases, let's guard against it. Change-Id: I70c6812cdfe0d0671b3d653744a062d9920a2394 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41339 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18	util/release: Improve reporting of required tools	Patrick Georgi
	genrelnotes checks for cloc, git and rename but only reported about needing the first two, so mention `rename` in missing message. Change-Id: If91d759fc68760fd89b98756ac5b19ac3589c197 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12	util/sconfig: Add LPC and ESPI buses	Raul E Rangel
	Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12	inteltool: fix dumping of Lynx Point LP and Wildcat Point PM registers	Iru Cai
	Currently inteltool uses the addresses and names of the PCH of previous generations. It's wrong for Lynx Point LP and Wildcat Point. The addresses and names of the I/O registers can be found in "Mobile 4th Generation Intel Core Processor Family I/O Datasheet" (Document Number: 329003-003) for Lynx Point LP and "Mobile 5th Generation Intel Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor Family I/O Datasheet" (Document Number: 330837-004) for Wildcat Point. Change-Id: If6ba718ccff077aa89affec89018bd7923527466 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40273 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util/nvramtool: Remove license boiler plate from DISCLAIMER file, too	Patrick Georgi
	Change-Id: I7ce0f08efaddb07a5d5f484d313068e5db3c7e2e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41220 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util/qualcomm/scripts: use SPDX header	Patrick Georgi
	Change-Id: Ife2d84bac1973a10139db2a1489b7ea54360eee1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41219 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util/cbfstool: Add SPDX header to generated linux_trampoline code, too	Patrick Georgi
	Change-Id: Id84244bb0c54326ea27be8801246fdeff039fb63 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util: Use SPDX headers	Patrick Georgi
	Change-Id: I2858fdf74e782f425d56653491cdebe83c185d19 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11	treewide: Convert more license headers to SPDX style	Patrick Georgi
	Change-Id: Ia3de79c7d71049da00ed108829eac6cb49ff3ed6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41205 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util/lint: Allow use of the HPND license group	Patrick Georgi
	The Historical Permission Notice and Disclaimer (with and without permission to sell) is a BSD-style license family that OSI and SPDX consider deprecated - and yet, it's right here in our tree. Change-Id: I61624b6e54e9aba6e2f54822c1f68967c416ad3d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41221 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util/lint: Also accept BSD-2-Clause	Patrick Georgi
	It's also GPL compatible Change-Id: I3d9243708478f315d91473009ca34786fabffda4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-11	treewide: Replace BSD-3-Clause and ISC headers with SPDX headers	Patrick Georgi
	Commands used: perl -i -p0e 's\|\/\[\s]Permission[\s]to[\s]use,[\s]copy,[\s]modify,[\s]and.or[\s]distribute[\s]this[\s]software[\s]for[\s]any[\s]purpose[\s]with[\s]or[\s]without[\s]fee[\s]is[\s]hereby[\s]granted,[\s]provided[\s]that[\s]the[\s]above[\s]copyright[\s]notice[\s]and[\s]this[\s]permission[\s]notice[\s]appear[\s]in[\s]all[\s]copies.[\s]THE[\s]SOFTWARE[\s]IS[\s]PROVIDED[\s].AS[\s]IS.[\s]AND[\s]THE[\s]AUTHOR[\s]DISCLAIMS[\s]ALL[\s]WARRANTIES[\s]WITH[\s]REGARD[\s]TO[\s]THIS[\s]SOFTWARE[\s]INCLUDING[\s]ALL[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY[\s]AND[\s]FITNESS.[\s]IN[\s]NO[\s]EVENT[\s]SHALL[\s]THE[\s]AUTHOR[\s]BE[\s]LIABLE[\s]FOR[\s]ANY[\s]SPECIAL,[\s]DIRECT,[\s]INDIRECT,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s]OR[\s]ANY[\s]DAMAGES[\s]WHATSOEVER[\s]RESULTING[\s]FROM[\s]LOSS[\s]OF[\s]USE,[\s]DATA[\s]OR[\s]PROFITS,[\s]WHETHER[\s]IN[\s]AN[\s]ACTION[\s]OF[\s]CONTRACT,[\s]NEGLIGENCE[\s]OR[\s]OTHER[\s]TORTIOUS[\s]ACTION,[\s]ARISING[\s]OUT[\s]OF[\s]OR[\s]IN[\s]CONNECTION[\s]WITH[\s]THE[\s]USE[\s]OR[\s]PERFORMANCE[\s]OF[\s]THIS[\s]SOFTWARE.[\s]\\/\|/* SPDX-License-Identifier: ISC /\|s' $(cat filelist) perl -i -p0e 's\|(\#\#)\sPermission[\#\s]to[\#\s]use,[\#\s]copy,[\#\s]modify,[\#\s]and.or[\#\s]distribute[\#\s]this[\#\s]software[\#\s]for[\#\s]any[\#\s]purpose[\#\s]with[\#\s]or[\#\s]without[\#\s]fee[\#\s]is[\#\s]hereby[\#\s]granted,[\#\s]provided[\#\s]that[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice[\#\s]and[\#\s]this[\#\s]permission[\#\s]notice[\#\s]appear[\#\s]in[\#\s]all[\#\s]copies.[\#\s]THE[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED[\#\s].AS[\#\s]IS.[\#\s]AND[\#\s]THE[\#\s]AUTHOR[\#\s]DISCLAIMS[\#\s]ALL[\#\s]WARRANTIES[\#\s]WITH[\#\s]REGARD[\#\s]TO[\#\s]THIS[\#\s]SOFTWARE[\#\s]INCLUDING[\#\s]ALL[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY[\#\s]AND[\#\s]FITNESS.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL[\#\s]THE[\#\s]AUTHOR[\#\s]BE[\#\s]LIABLE[\#\s]FOR[\#\s]ANY[\#\s]SPECIAL,[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s]OR[\#\s]ANY[\#\s]DAMAGES[\#\s]WHATSOEVER[\#\s]RESULTING[\#\s]FROM[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA[\#\s]OR[\#\s]PROFITS,[\#\s]WHETHER[\#\s]IN[\#\s]AN[\#\s]ACTION[\#\s]OF[\#\s]CONTRACT,[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHER[\#\s]TORTIOUS[\#\s]ACTION,[\#\s]ARISING[\#\s]OUT[\#\s]OF[\#\s]OR[\#\s]IN[\#\s]CONNECTION[\#\s]WITH[\#\s]THE[\#\s]USE[\#\s]OR[\#\s]PERFORMANCE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE.\s(\# \n)\|\1 SPDX-License-Identifier: ISC\n\n\|s' $(cat filelist) perl -i -p0e 's\|\/\[\s]Redistribution[\s]and[\s]use[\s]in[\s]source[\s]and[\s]binary[\s]forms,[\s]with[\s]or[\s]without[\s]modification,[\s]are[\s]permitted[\s]provided[\s]that[\s]the[\s]following[\s]conditions[\s]are[\s]met:[\s][1. ]Redistributions[\s]of[\s]source[\s]code[\s]must[\s]retain[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer.[\s][\s][2. ]Redistributions[\s]in[\s]binary[\s]form[\s]must[\s]reproduce[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer[\s]in[\s]the[\s]documentation[\s]and.or[\s]other[\s]materials[\s]provided[\s]with[\s]the[\s]distribution.[\s][3. ].used[\s]to[\s]endorse[\s]or[\s]promote[\s]products[\s]derived[\s]from[\s]this[\s]software[\s]without[\s]specific[\s]prior[\s]written[\s]permission.[\s]THIS[\s]SOFTWARE[\s]IS[\s]PROVIDED.AS[\s]IS.[\s]AND[\s]ANY[\s]EXPRESS[\s]OR[\s]IMPLIED[\s]WARRANTIES,[\s]INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]THE[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY.FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.ARE[\s]DISCLAIMED.[\s]IN[\s]NO[\s]EVENT[\s]SHALL.LIABLE[\s]FOR[\s]ANY[\s]DIRECT,[\s]INDIRECT,[\s]INCIDENTAL,[\s]SPECIAL,[\s]EXEMPLARY,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s].INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]PROCUREMENT[\s]OF[\s]SUBSTITUTE[\s]GOODS[\s]OR[\s]SERVICES;[\s]LOSS[\s]OF[\s]USE,[\s]DATA,[\s]OR[\s]PROFITS;[\s]OR[\s]BUSINESS[\s]INTERRUPTION.[\s]HOWEVER[\s]CAUSED[\s]AND[\s]ON[\s]ANY[\s]THEORY[\s]OF[\s]LIABILITY,[\s]WHETHER[\s]IN[\s]CONTRACT,[\s]STRICT[\s]LIABILITY,[\s]OR[\s]TORT[\s].INCLUDING[\s]NEGLIGENCE[\s]OR[\s]OTHERWISE.[\s]ARISING[\s]IN[\s]ANY[\s]WAY[\s]OUT[\s]OF[\s]THE[\s]USE[\s]OF[\s]THIS[\s]SOFTWARE,[\s]EVEN[\s]IF[\s]ADVISED[\s]OF[\s]THE[\s]POSSIBILITY[\s]OF[\s]SUCH[\s]DAMAGE.[\s]\\/\|/ SPDX-License-Identifier: BSD-3-Clause /\|s' $(cat filelist) $1 perl -i -p0e 's\|(\#\#) Redistribution[\#\s]and[\#\s]use[\#\s]in[\#\s]source[\#\s]and[\#\s]binary[\#\s]forms,[\#\s]with[\#\s]or[\#\s]without[\#\s]modification,[\#\s]are[\#\s]permitted[\#\s]provided[\#\s]that[\#\s]the[\#\s]following[\#\s]conditions[\#\s]are[\#\s]met:[\#\s][1. ]Redistributions[\#\s]of[\#\s]source[\#\s]code[\#\s]must[\#\s]retain[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer.[\#\s][2. ]Redistributions[\#\s]in[\#\s]binary[\#\s]form[\#\s]must[\#\s]reproduce[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer[\#\s]in[\#\s]the[\#\s]documentation[\#\s]and.or[\#\s]other[\#\s]materials[\#\s]provided[\#\s]with[\#\s]the[\#\s]distribution.[\#\s][\#\s][3. ].used[\#\s]to[\#\s]endorse[\#\s]or[\#\s]promote[\#\s]products[\#\s]derived[\#\s]from[\#\s]this[\#\s]software[\#\s]without[\#\s]specific[\#\s]prior[\#\s]written[\#\s]permission.[\#\s]THIS[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED.AS[\#\s]IS.[\#\s]AND[\#\s]ANY[\#\s]EXPRESS[\#\s]OR[\#\s]IMPLIED[\#\s]WARRANTIES,[\#\s]INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]THE[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY.FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.ARE[\#\s]DISCLAIMED.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL.LIABLE[\#\s]FOR[\#\s]ANY[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]INCIDENTAL,[\#\s]SPECIAL,[\#\s]EXEMPLARY,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s].INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]PROCUREMENT[\#\s]OF[\#\s]SUBSTITUTE[\#\s]GOODS[\#\s]OR[\#\s]SERVICES;[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA,[\#\s]OR[\#\s]PROFITS;[\#\s]OR[\#\s]BUSINESS[\#\s]INTERRUPTION.[\#\s]HOWEVER[\#\s]CAUSED[\#\s]AND[\#\s]ON[\#\s]ANY[\#\s]THEORY[\#\s]OF[\#\s]LIABILITY,[\#\s]WHETHER[\#\s]IN[\#\s]CONTRACT,[\#\s]STRICT[\#\s]LIABILITY,[\#\s]OR[\#\s]TORT[\#\s].INCLUDING[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHERWISE.[\#\s]ARISING[\#\s]IN[\#\s]ANY[\#\s]WAY[\#\s]OUT[\#\s]OF[\#\s]THE[\#\s]USE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE,[\#\s]EVEN[\#\s]IF[\#\s]ADVISED[\#\s]OF[\#\s]THE[\#\s]POSSIBILITY[\#\s]OF[\#\s]SUCH[\#\s]DAMAGE.\s(\#* \n)\|\1 SPDX-License-Identifier: BSD-3-Clause\n\n\|s' $(cat filelist) Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11	util: Add SPDX header, replacing boiler plate where applicable	Patrick Georgi
	In a few cases a license was added: Stuff coming from Linux is "GPL-2.0" (not GPL-2.0-only!), build-release is by me and got the usual GPL-2.0-only treatment. uio_usbdebug and spkmodem had their licenses propagate to all their files. Change-Id: Ia5712bbaa417cb9e937834512351fcc0acfa16be Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41202 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util: Fix up a few comments after the "file is part of the" removal	Patrick Georgi
	Change-Id: I930739bea705988181b2e60f30516f4a7cb5c82d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41197 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
	Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " \|egrep ":( /\.\/\$\|#\|;#\|-- \| \ )" \| cut -d: -f1 \|grep -v crossgcc \|grep -v gcov \| grep -v /elf.h \|grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. /") -# This file is part of a set of unofficial pre-commit hooks available -/ This file is part of coreboot / -# This file is part of msrtool. -/ This file is part of msrtool. / - This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. / - This file is part of the coreboot project. - /* This file is part of the coreboot project. / -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/ This file is part of the coreboot project / -/ This file is part of the coreboot project. / -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. / -/ This file is part of the ectool project. / - This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. / -## This file is part of the superiotool project. -/ This file is part of the superiotool project / -/ This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	util/nvramtool: Remove "this file is part of" lines	Patrick Georgi
	As requested by Stefan. For nvramtool some of these lines are part of a paragraph of fluff, so manual processing was easier than adapting the script used for the rest of the tree. Change-Id: Id52c4c264cded0582a97da131b695a046cbd67c6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-11	util/lint: Omit more vendorcode from license header test	Patrick Georgi
	This is all code coming from the outside, so let's keep these files untouched as much as possible. A couple of files is added to the list by name because their license, while free, can't be properly modelled in SPDX: - lzmadecode is (LGPL OR CPL) WITH special-exception - stack.c and start16 are some weird (but free) US Gov't license grant - two XGI related files have "BSD except for Linux, where it's GPL" Change-Id: I42dec503b9c427a66792d3fec99ca8df1a360e47 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-09	util/: Replace GPLv2 boiler plate with SPDX header	Patrick Georgi
	Used commands: perl -i -p0e 's\|\/\[\s].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-2.0-only /\|' $(cat filelist) perl -i -p0e 's\|This[\s]program[\s]is[\s]free[\s]software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]either[\s]version[\s]2[\s]of[\s]the[\s]License,[\s]or[\s].at[\s]your[\s]option.[\s]any[\s]later[\s]version.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-2.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|\/\[\s].This[\s#]program[\s#]is[\s#]free[\s#]software[;:,][\s#]you[\s#]can[\s#]redistribute[\s#]it[\s#]and/or[\s#]modify[\s#]it[\s#]under[\s#]the[\s#]terms[\s#]of[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]as[\s#]published[\s#]by[\s#]the[\s#]Free[\s#]Software[\s#]Foundation[;:,][\s#]either[\s#]version[\s#]3[\s#]of[\s#]the[\s#]License[;:,][\s#]or[\s#].at[\s#]your[\s#]option.[\s#]any[\s#]later[\s#]version.[\s#]This[\s#]program[\s#]is[\s#]distributed[\s#]in[\s#]the[\s#]hope[\s#]that[\s#]it[\s#]will[\s#]be[\s#]useful[;:,][\s#]but[\s#]WITHOUT[\s#]ANY[\s#]WARRANTY[;:,][\s#]without[\s#]even[\s#]the[\s#]implied[\s#]warranty[\s#]of[\s#]MERCHANTABILITY[\s#]or[\s#]FITNESS[\s#]FOR[\s#]A[\s#]PARTICULAR[\s#]PURPOSE.[\s#]See[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]for[\s#]more[\s#]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-3.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\#\s]you[\#\s]can[\#\s]redistribute[\#\s]it[\#\s]and\/or[\#\s]modify[\#\s]it[\s\#]under[\s \#]the[\s\#]terms[\s\#]of[\s\#]the[\s\#]GNU[\s\#]General[\s\#]Public[\s\#]License[\s\#]as[\s\#]published[\s\#]by[\s\#]the[\s\#]Free[\s\#]Software[\s\#]Foundation[;,][\s\#]version[\s\#]2[\s\#]of[\s\#]the[\s\#]License.[\s\#]This[\s\#]program[\s\#]is[\s\#]distributed[\s\#]in[\s\#]the[\s\#]hope[\s\#]that[\s\#]it[\s\#]will[\#\s]be[\#\s]useful,[\#\s]but[\#\s]WITHOUT[\#\s]ANY[\#\s]WARRANTY;[\#\s]without[\#\s]even[\#\s]the[\#\s]implied[\#\s]warranty[\#\s]of[\#\s]MERCHANTABILITY[\#\s]or[\#\s]FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.[\#\s]See[\#\s]the[\#\s]GNU[\#\s]General[\#\s]Public[\#\s]License[\#\s]for[\#\s]more[\#\s]details.\s(# \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.\s(#* \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) Change-Id: I1008a63b804f355a916221ac994701d7584f60ff Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09	AUTHORS, util/: Drop individual copyright notices	Patrick Georgi
	We have the git history which is a more reliable librarian. Change-Id: Idbcc5ceeb33804204e56d62491cb58146f7c9f37 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-05-07	util/sconfig: Drop use of ref_count for chip_instance	Furquan Shaikh
	chip_instance structure currently uses a ref_count to determine how many devices hold reference to that instance. If the count drops to zero, then it is assumed that the chip instance is a duplicate in override tree and has a similar instance that is already overriden in base device tree. ref_count is currently decremented whenever a device in override tree matches the one in base device tree and the registers from the override tree instance are copied over to the base tree instance. On the other hand, if a device in override tree does not match any device in base tree under a given parent, then the device is added to base tree and all the devices in its subtree that hold pointers to its parent chip instance are updated to point to the parent's chip instance in base tree. This is done as part of update_chip_pointers. However, there are a couple of issues that this suffers from: a) If a device is present only in override tree and it does not have its own chip (i.e. pointing to parent's chip instance), then it results in sconfig emiiting parent's chip instance (which can be the SoC chip instance) in static.c even though it is unused. This is because update_chip_pointers() does not call delete_chip_instance() before reassigning the chip instance pointer. b) If a device is added under root device only in the override tree and it does not have its own chip instance (i.e. uses SoC chip instance), then it results in sconfig emitting a copy of the SoC chip instance and setting that as chip_ops for this new device in the override tree. In order to fix the above issues, this change drops the ref_count field from chip_instance structure and instead adds a forwarding pointer `base_chip_instance`. This is setup as per the following rules: 1. If the instance belongs to base devicetree, base_chip_instance is set to NULL. 2. If the instance belongs to override tree, then it is set to its corresponding chip instance in base tree (if present), else set to NULL. State of base_chip_instance is then used when emitting chips and devices using the following rules: 1. If a chip_instance has non-NULL base_chip_instance, then that chip instance is not emitted to static.c 2. When emitting chip_ops for a device, base_chip_instance is used to determine the correct chip instance name to emit. BUG=b:155549176 TEST=Verified that the static.c file generated for base/override tree combination is correct when new devices without chips are added only to override tree. Change-Id: Idbb5b34f49bf874da3f30ebb6a6a0e2d8d091fe5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41007 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-07	util/sconfig: Move chip instance id assignment to emit_chips()	Furquan Shaikh
	This change moves the assignment of id for chip instance from new_chip_instance() to emit_chips(). This is similar to the previous change for moving dev id assignment to happen much later. This ensures that the same ID gets assigned to a chip when adding support for device trees which makes it easier to compare static.c files. BUG=b:155549176 Change-Id: I3efa9af5ed91123675be42bce1cb389bad19cb62 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-07	util/sconfig: Drop id from struct device maintained by sconfig	Furquan Shaikh
	This change drops the id field from struct device as used by sconfig. It was primarily used for generating unique device names. This was maintained within device structure so that the order in which the device tree entries were parsed is clear. Since the ids are assigned in parsing order, it is problematic when a device is moved from base devicetree to override tree. The entire parsing order changes which makes it really difficult to compare what really changed in static.c file. By moving the dev name assignment to happen later when doing pass0 of static.c generation, the difference in static.c file is minimized when adding support for override trees. BUG=b:155549176 Change-Id: I31870ace5a2fd7d5f95ab5e30d794c3bc959ed46 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
	This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.as.published.by.the.Free.Software.Foundation[;,].version.2.of.the.License.or.(at.your.option).any.later.version.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/ SPDX-License-Identifier: GPL-2.0-or-later /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.as.published.by.the.Free.Software.Foundation[;,].version.2.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.version.2.as.published.by.the.Free.Software.Foundation[.;,].+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This software is licensed under.the.terms.of.the.GNU.General.Public.License.version.2.as.published.by.the.Free.Software.Foundation,.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only */\|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06	treewide: move copyrights and authors to AUTHORS	Patrick Georgi
	Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
	That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's\|/\.\n.This file is part of the coreboot project.\n.\\|/* This file is part of the coreboot project. /\n/\|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-05	sconfig: Allow `register` entries below devices, too	Nico Huber
	Every device belongs to a chip. And we already keep that relation by inheriting the `.chip_info` pointer if downstream devices don't have another chip specified. So we can also allow to specify `register` settings at the device level. Change-Id: I44e6b95d0cd708fef69b152ebc46b869b2bb9205 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40803 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04	treewide: Drop ACPI_VIDEO_DEVICE macro	Angel Pons
	It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
	This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" \| xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01	util/intelmetool: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
	Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-29	util/kconfig: Remove miniconfig script	Patrick Georgi
	It replicates the functionality of savedefconfig because back when the script was added, savedefconfig didn't work for us. It now does, is the official way of doing things, is recommended in our documentation and is also a fair bit faster. Change-Id: Ia8e0377537ff7cd638c564037ea6a77b01a87243 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28	Documentation: Spell vboot all lowercase	Patrick Rudolph
	Update all occurrences of vboot and spell it lowercase. Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-22	util/scripts/ucode_h_to_bin.sh: Fix .inc-lines with just comment	Werner Zeh
	There are microcodes in .inc format out in the wild which contains lines with just a comment. So these files look like the following example: ; External header dd 000000001h dd 00000001bh ... ; Data dd 000000000h ... The lines with just a comment starts with a ';' and will break the current awk formatting which is performed to reformat the content into C code style. As we are just interested in the data we can simply drop all lines that start with a ';' which sed can do pretty easy. Change-Id: I9ff5db51667672cffd9d776fb9497962b4a6083a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22	util/scripts/ucode_h_to_bin.sh: Drop disruptive quotes	Werner Zeh
	The double quotes around the remaining shell parameters '${@:2}' causes that the provided *.h files in $(CONFIG_CPU_MICROCODE_HEADER_FILES), which is a space separated list, cannot be broken down to every single file as needed but stay as a single parameter in the for-loop. Therefore, the called function 'include_file' will get a single parameter with all files which will lead to a broken C code in terms of a wrong #include-syntax. This causes the script to fail. To fix this remove the double quotes which works just fine. Change-Id: Iab7b0dc8d850973d6af764899907d383e9ec7743 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-22	util/scripts/ucode_h_to_bin.sh: Replace whitespace with TABs	Werner Zeh
	Newly added code in commit CB:25546 contains spaces instead of TABs for line indent. Replace every 4 spaces by a single TAB to match our coding guides. Change-Id: Ie3633bb42643f4abb5f1a8827a7dc2c9e023d6aa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20	Doc,util: Update list of utilities	Jacob Garber
	Remove entries for old utilities and add entries for new ones. Generated using util/util_readme, with some tweaks to preserve the markdown. Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20	util/cbfstool: Allow use of non-ASCII longopt	Furquan Shaikh
	CB:29744 ("util/cbfstool: Add optional argument ibb") added support for non-ASCII characters for long_options. However, there is a check later on which errors out since this character is not one of the commands[i].optstring. This change adds a function valid_opt() which does the following things: 1. Checks if the returned optchar is among the list of optstring supported by the command. 2. Checks if the returned optchar is a valid non-ASCII option. Currently, we do not maintain a list of non-ASCII options supported by each command. So, this function returns true if the optchar returned by getopt_long falls within the allowed range. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I27a4f9af9850e4c892573202904fa9e5fbb64df6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-16	autoport: use GMA_STATIC_DISPLAYS	Iru Cai
	Change-Id: Ie988b2caeb2cdc07a3d6466b7ae3501df469ef41 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16	autoport: Support bigger ACPI tables	Iru Cai
	DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB for an ACPI table and support lines in acpidump.log with address higher than 0x10000. Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14	src/Kconfig: enable USE_BLOBS by default	Felix Held
	To provide sane defaults for most of the user base, this patch switches on the USE_BLOBS option by default. Since it only changes the default, this behaviour can still be easily disabled. With this abuild doesn't have to select USE_BLOBS any more, so what abuild tests becomes the coreboot default again. Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13	util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licenses	Rajat Jain
	The Linux kernel UAPI header files are licensed under /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ Allows files with this license to be included in coreboot. For more details about this particular license: https://www.kernel.org/doc/html/v4.17/process/license-rules.html https://spdx.org/licenses/Linux-syscall-note.html Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e Signed-off-by: Rajat Jain <rajatja@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-10	util/nvramtool: Remove 2nd initialization	Elyes HAOUAS
	'result' is already defined as 'unsigned long long result = 0;' so no need to re-write 'result = 0;'. Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-05	fsp2_0: Clean up around `config FSP_USE_REPO`	Nico Huber
	We can make our lifes much easier by removing its dependency on `ADD_FSP_BINARIES`. Instead, we imply the latter if the repository is to be used. We can also hide a lot of unnecessary prompts in this case. Also, remove default overrides and selects for the two that are now unnecessary. Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30	util/sconfig: emit NULL sibling fields	Aaron Durbin
	It's helpful to see the sibling field, even when it's NULL, when debugging the static.c output from a devictree.cb file. Ensure the NULL fields are emitted for fullness. Change-Id: Ib6d5b8164769a6512e762d5a525c7df1f429c866 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-27	amdfwtool: Allow for up to 16 APCB entries	Rob Barnes
	Increase the number of allowed APCB entries in amdfwtool. BUG=b:150455865 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238 Reviewed-on: https://chromium-review.googlesource.com/2084944 Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25	util/board-status: Reject logs from dirty images	Paul Menzel
	Currently, there are a lot of uploads in the board status repository, where the logs say, that the coreboot image or payload were built from a dirty source tree. Add a check to reject such uploads. Change-Id: I920e26a10f74e1f3b9b4e5f8c9284c59692a519b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-24	drivers/intel/gma: Ditch `link_frequency_270_mhz` setting	Nico Huber
	The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24	util/inteltool: add inteltool path to include path	Michael Niewöhner
	Add the inteltool path to the include path to be able to avoid ugly include hacks like `#include "../inteltool.h"`. Change-Id: Id363fa20fe3b52248a224ca14b2626a8e3ce44a2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39744 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23	Doc/security/vboot: Add a script generated device list	Marcello Sylvester Bauer
	Add a script generated list of vboot enabled devices to the documentation. Add a entry to the release checklist. Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23	cbfstool: Build vboot library	Yu-Ping Wu
	Currently cbfstool cherry-picks a few files from vboot and hopes these files will work standalone without any dependencies. This is pretty brittle (for example, CL:2084062 will break it), and could be improved by building the whole vboot library and then linking against it. Therefore, this patch creates a new target $(VBOOT_HOSTLIB) and includes it as a dependency for cbfstool and ifittool. To prevent building the vboot lib twice (one for cbfstool and the other for futility) when building coreboot tools together, add the variable 'VBOOT_BUILD' in Makefile to define a shared build path among different tools so that vboot files don't need to be recompiled. Also ignore .o.d and .a for vboot library. BRANCH=none BUG=none TEST=make -C util/cbfstool TEST=make -C util/futility TEST=Run 'make tools' and make sure common files such as 2sha1.c are compiled only once TEST=emerge-nami coreboot-utils Change-Id: Ifc826896d895f53d69ea559a88f75672c2ec3146 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-21	util/inteltool: use read* macros instead of pointers	Michael Niewöhner
	Switch to using read* macros instead of pointers. Change-Id: I1fe54b496a5998597b79cdd7108f3a4075744a78 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20	util/inteltool: powermgt: add code for dumping config registers	Michael Niewöhner
	This adds the code required to dump config registers. Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-20	util/scripts/gerrit-rebase: Fix shell invocation	Patrick Georgi
	The single apostrophe confuses the shell that's calling the command. Change-Id: I7d3183e9a612de0121b2d208c06a45645b8d67f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20	util/autoport: Emit SPDX license headers	Angel Pons
	Change-Id: I8896b6c92c3126cc611e47b39d596108b90c6bf2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-20	util/xcompile: Split $CFLAGS_GCC	Nico Huber
	Split common flags that are not specific to the C language out of $CFLAGS_GCC into $FLAGS_GCC. This way, we can test for C specific flags, too, without adding them to $ADAFLAGS_*. Currently this is done for `-Wno-address-of-packed-member` which only applies to C. Change-Id: Ib793c62656efb07b6e5b3385f1ed1c96a40efd1d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39633 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19	util/bincfg: Add DDR4 SPD spec	Rob Barnes
	Additionally provide a simple script for decoding spd hex files using bincfg. BUG=b:148561711 TEST=Decoded spd files in zork BRANCH=None Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/2067697 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-03-18	util/lint/spelling.txt: Disable `afe`	Angel Pons
	Uppercase `AFE` is an acronym for `Analog Front-End`. As it is a valid spelling, comment out its entry to prevent false positives. Change-Id: Ib8612d970d33d4955c572838bda217cfdb49dfe6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18	util/lint/spelling.txt: Explain the commented-out entries	Angel Pons
	If they were removed instead, it would be too easy to end up adding them back again. They are kept in a comment so that they can be tracked. Also, explain why these two entries have been commented out. Change-Id: I8225944b5e3d1e022af169dda33e0344d4c3bccd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18	util/inteltool: powermgt: make Sunrise Point dumping work	Michael Niewöhner
	The existing Sunrise Point ids are assigned to the wrong implementation, which would never work for these chipsets. Assign them to the right dumping implementation, which works for both Sunrise Point PCH-H and PCH-LP. This also adds some missing device ids from doc#332691-003EN and doc#334659-005. Change-Id: Id102ef3809d675dc9a915d2cb3062e093487fa27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18	util/autoport: Correct formatting issues	Angel Pons
	There is no need to use hexadecimal values in azalia codec IDs, nor need to print a redundant "LPC bridge PCI-LPC bridge" comment. Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-18	util/inteltool: Makefile: add src/arch to includes.	Michael Niewöhner
	Add src/arch to includes. Change-Id: I157178a055a259e40c57f3915671d3b8966fbb96 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-17	util/amdfwtool: Fix file open error msg	Eric Peers
	Print out the name of the file that failed to open. BUG=none TEST=rerun build-board.sh with missing files BRANCH=none Signed-off-by: Eric Peers <epeers@google.com> Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb Reviewed-on: https://chromium-review.googlesource.com/2090667 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-17	util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl	Michael Niewöhner
	Add a bunch of missing chipsets to print_bioscntl. Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17	util/inteltool: add code for dumping LPC registers	Michael Niewöhner
	This adds the implementation for dumping LPC registers Change-Id: I50ae4913933f7594f0d63ce3f752302ed5c461e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: ahci: add Sunrise Point config and SIR registers	Michael Niewöhner
	This adds the Sunrise Point AHCI config and SIR registers from doc#332691-003EN. Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39506 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: ahci: add code for dumping config and SIR registers	Michael Niewöhner
	This adds the code required to dump config and SIR registers. Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: ahci: rework AHCI	Michael Niewöhner
	Rework AHCI to align the code with the rest of inteltool. Change-Id: I37116f8e269d0376e147dd6de7365c45ac90bda0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39504 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	inteltool: add support for CannonPoint-LP	Matt DeVillier
	Add support for CannonPoint-LP U Premium (CoffeeLake-U and WhiskeyLake-U) GPIO info taken from: - Intel doc #337867-002 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs.h Test: Read GPIOs from out-of-tree WhiskeyLake-U board Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I70f23eec71abb8d7c2a7a109c9e760bb31dee2ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/39393 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: Split GPIO community switch-case into its own function	Johanna Schander
	So far printing the GPIO groups chose the community definition. As the list of supported platforms grows the massive switch case gets repetetive and hinders the readers view. It also reduces the ability to reuse the code in a potential libinteltool. To takle these issues the detection logic was split into its own function. Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38631 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: Move Denverton definitions into their own header	Johanna Schander
	So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moved the Denverton definitions into its own header. Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: Move Lewisburg definitions into their own header	Johanna Schander
	So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Lewisburg definitions into its own header. Change-Id: I7900f1d8b3ca022112874ac2fa7326d538166008 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38629 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: Move Sunrise Point (LP) definitions into their own header	Johanna Schander
	So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Sunrise Point and Sunrise Point LP definitions into its own header. Change-Id: I06efbee700f1525770365428fb85ef700ac53b80 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38628 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: Move Apollo Lake definitions into their own header	Johanna Schander
	So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Apollo Lake definitions into its own header. Change-Id: I44b21092f5495f758c1f2151a913c074dfc658f5 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38627 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: Move Cannon Lake definitions into their own header	Johanna Schander
	So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Cannon Lake definitions into its own header. Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: Move Ice Lake definitions into their own header	Johanna Schander
	So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Ice Lake definitions into its own header. Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	Revert "crossgcc: Upgrade GCC to 9.2.0"	Patrick Rudolph
	Revert the upgrade as it breaks at least the devicetree parser on aarch64, tested on qemu aarch64 target. This reverts commit dfd3f211740be4cf0d234bf4621ac384758a24ce. Change-Id: I65607817188db21533014caa6d15be9a2004d498 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-16	util/crossgcc: Temporarily disable GDB build test on server	Martin Roth
	The latest debian builder image doesn't compile GDB correctly. Disable the build test until I can get it working again. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7852a39ed40a7364d24d0bbf014fd25058491083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39575 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16	util/inteltool: add 6th gen. mobile core u/y series	Michael Niewöhner
	This adds the 6th gen. mobile core u/y series. Change-Id: I7d802452353afe568e3880765dcd340f0437b392 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39568 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15	util/inteltool: powermgt: rename variable for consistency	Michael Niewöhner
	Rename size variable for consistency with the other subsystems. Change-Id: I9407193ac9e34685362619cfd45384156e2385c3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39507 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15	util/inteltool: powermgt: initialize register size variables	Michael Niewöhner
	Initialize register size variables to prevent segfaults. Change-Id: Ib89bf6f7c7582efdea1c54d1316ed8f33a87cfcc Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39513 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15	treewide: Replace uses of "Nehalem"	Angel Pons
	The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15	nb/intel/nehalem: Rename to ironlake	Angel Pons
	The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15	util/inteltool: powermgt: drop dead code	Michael Niewöhner
	Drop dummy entry. Change-Id: I1257115bd73fe90c6435116c8705cb5c98d945e1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39559 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15	util/inteltool: gpio: drop dead code	Michael Niewöhner
	Drop dummy entry. Change-Id: Ic2184453c628c034e40ba877791fab4b7fe1d934 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39558 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14	coreboot: add Volteer template files	Paul Fagerburg
	Add template files for making a new barebones-copy of Volteer. BUG=b:147483699 BRANCH=None TEST=N/A Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-03-10	util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format	Bartek Pastudzki
	Intel supplies microcode (at least for MinnowBoard) in Intel Assembly .inc format rather than C header. This change allow to pass in configuration directory with .inc files rather than list of *.h files. Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540 Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10	util/nvramtool: fix building on OpenBSD	Evgeny Zinoviev
	OpenBSD's gcc 4.2.1 doesn't know about _Noreturn Change-Id: Ie9e1885c483941d3d0ce8c8948af53f1ef8bb5db Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10	util/board_status: Add support of CMOS values dump	Evgeny Zinoviev
	Change-Id: I89f9a0e9622557b01dda52378f8f1323777bce39 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10	abuild: Always build the default config	Nico Huber
	Abuild allows us to add config files below `configs/` for each mainboard. So far, these were built instead of the default config. However, that allows to hide errors in the default config. Hence, we should build that too in any case. Change-Id: I94075dbaa6fabeb75bdbc92e56f237df80c15cef Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39382 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09	3rdparty/libgfxinit: Update submodule pointer	Nico Huber
	Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09	util/superiotool: Drop one SCH5317 entry	Angel Pons
	The SCH5317 can have either 0x85 or 0x8c as device ID. However, the former results in false positives on any ITE IT85xx series embedded controller, which has led some people to think that chip was actually in their laptops. Moreover, there is no register dump for the SCH5317. Since nobody has touched this in over a decade, avoid further confusion by dropping the misleading definition. Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>