coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2018-04-27	util/x86/x86_page_tables: add command line to generated files	Aaron Durbin
	In order to help the reader understand where things are generated from add a comment string that is composed of the command line used to generate the files. BUG=b:72728953 Change-Id: I1b93923f8b08192448ab19226fd27661cc09e853 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-23	util/x86/x86_page_tables: add license header to generated code	Aaron Durbin
	If one wants to check in generated page tables in C then coreboot complains about there not being a license. Therefore, add the BSD license to the generated page tables. BUG=b:72728953 Change-Id: I980d7a7c0c14c1ed5aa8ce37a1484943a6a100f2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23	util/x86/x86_page_tables: update PAT mapping to match linux	Aaron Durbin
	The linux kernel uses the following mapping for PAT entries: PTE encoding: PAT \|PCD \|\|PWT PAT \|\|\| slot 000 0 WB : _PAGE_CACHE_MODE_WB 001 1 WC : _PAGE_CACHE_MODE_WC 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS 011 3 UC : _PAGE_CACHE_MODE_UC 100 4 WB : Reserved 101 5 WP : _PAGE_CACHE_MODE_WP 110 6 UC-: Reserved 111 7 WT : _PAGE_CACHE_MODE_WT Update the page table generator to match what the linux kernel is using. This just makes things consistent with linux. BUG=b:72728953 Change-Id: Ie5ddab5c86d4e03688d7e808fcae34ce954b64f9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-07	util/x86: add page page table generator	Aaron Durbin
	Certain platforms need paging enabled during cache-as-ram because dirty lines are being evicted by a heavy speculative frontend. Paging needs to be enabled in order to utilize the NX (no execute) bit for the regions that are strictly data (such as the stack). This utility creates 32-bit PAE page tables using a static address space, and the resulting tables have entries for all the PDPTEs such that it makes it easy to enable 2MiB naturally aligned DRAM mappings once memory is trained. Either binary files can be generated or C files. The pages that are linked use a default base address of 0xaa000000 that can be changed at runtime to reflect where the page tables are actually loaded. Or specify a physical address on the command line that is known a priori. iomap.txt: 0xd0000000, 0x100000000, UC, NX # All of MMIO 0xff000000, 0x100000000, WP, # memory-mapped SPI 0xffff8000, 0x100000000, WP, # XIP bootblock 0xfef00000, 0xfefc0000, WB, NX # CAR 0xfef40000, 0xfefc0000, WB, # verstage 0xfef20000, 0xfefc0000, WB, # romstage 0xfef40000, 0xfefc0000, WB, # fsp-m $ go run util/x86/x86_page_tables.go --iomap_file=iomap.txt Merged address space: 00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small 00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small 00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small 00000000fefc0000 -- 00000000ff000000 UC NX : 0 big 64 small 00000000ff000000 -- 0000000100000000 WP : 8 big 0 small Total Pages of page tables: 5 Pages linked using base address of 0xaa000000. BUG=b:72728953 Change-Id: I47625a24979b196011e2293712a8cdbdbb880d79 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/24919 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>