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2024-01-24util/spd_tools: Update Makefile.inc references to Makefile.mkMartin Roth
Make sure that any new files generated get the Makefile.mk name. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3880d5911ff8de01751befdffc99ba5a961416f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80113 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-04-05util/spd_tools: Add support for Phoenix platformKarthikeyan Ramasubramanian
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform so that SPD can be generated for the memory parts used in that platform. SPD requirements for Phoenix and Mendocino platforms are identical. BUG=b:273383819 TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms share the platform manifest for LP5 memory parts. Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-02-18util/spd_tools/src/spd_gen/lp5.go: Support LP5X 8533MbpsKyle Lin
Add support for LP5X 8533Mbps in SPD tool. BUG=b:263189532 TEST=None Change-Id: I72b02514f68647dda996822f910db8bc93f61ca4 Signed-off-by: Kyle Lin <kylelinck@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marx Wang <marx.wang@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-13util/spd_tools: Format lp5 file to golang standardsRobert Zieba
This commit formats the lp5.go file according to goland standards. TEST=Built spd_tools Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If102c90f732efc51a90de6cc0e18c879d56699b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-29util/spd_tools: Change Mendocino to use 0x13 for LP5x memory typeRobert Zieba
Mendocino supports LP5x but currently doesn't support SPDs that use the LP5x memory type, 0x15. This commit updates set 1 SPDs, which are currently only used for mendocino, to use 0x13 for their memory type. BUG=b:245509394 TEST=Generated SPDs, verified that only set 1 have changed to 0x13 Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-07util/spd_tools: Update LP5X support for ADL/RPL/MTLCaveh Jalali
This updates the SPD utility and generated SPDs for LP5X to use memory type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on Intel Tech Advisory Doc ID #616599 dated May 2022, page 15. SPDs were regenerated with: "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5" This only affects the SPDs for 2 memory parts for Intel SoCs and the only board referencing these is rex. BUG=b:242765117 TEST=inspected SPD hex dump Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-30util/spd_tools: Add AMD Mendocino (MDN) platformEricKY Cheng
This patch adds support for MDN platform to the spd_tools. This change replaces SBR with MDN. BUG=b:243337816 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: If099af36de8a64e96fbfde32eaf15990f4b330c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-25util/spd_tools: Add support for LP5X SPDsRobert Zieba
This commit adds support for LP5X SPDs. The SPD format is identical to LP5 except that the memory type is set to 0x15 instead of 0x13. Since they are essentially the same, LP5/5X parts share the same parts JSON file and SPD directory. LP5X parts are distinguished by the optional `lp5x` attribute. This commit also updates two existing LP5X memory parts with the correct attribute. BUG=b:242765117 TEST=Generated SPDs, verified that SPDs generated from LP5X parts match their LP5 counterparts except for memory type byte. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-12util/spd_tools: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I404fcf59e89b75cd2488bcb51981aee2eb4ff0df Reviewed-on: https://review.coreboot.org/c/coreboot/+/66468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01util/spd_tools/spd_gen/lp5: Remove maxSpeed for SabrinaKarthikeyan Ramasubramanian
Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-19util/spd_tools: Limit memory speed to 5500 Mbps for SabrinaKarthikeyan Ramasubramanian
In Sabrina platform, memory speed is limited to 5500 Mbps. Update the SPD generation tool to limit to that speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-14util/spd_tools: Add support for 7500 MT/s lp5 modulesJack Rosenthal
spd_tools does not support LP5x modules yet, and the easiest way to do this is to add support for 7500 MT/s in lp5.go (reference the comments on CB:65063). BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=With follow-on CL, run: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14util/spd_tools: Add Intel Meteor Lake (MTL) platformSubrata Banik
This patch add support for MTL platform to the `spd_tools`. This would be useful to create dynamic SPD for rex variants. BUG=b:224325352 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-04-14util/spd_tools/part_id_gen: Support Sabrina SoCKarthikeyan Ramasubramanian
Add support to generate DRAM part ID for boards using Sabrina SoC. BUG=None TEST=Generate DRAM part ID for Skyrim mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-05util/spd_tools: Add ability to override SPD file for partsRobert Zieba
This commit adds the ability to override the SPD file that is used for a specific part. BUG=b:224884904 TEST=Verified that generated makefile uses specified SPD file and that it remains unchanged when this capability is not used Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-22util/spd_tools: Add support for exclusive IDsRobert Zieba
Currently memory parts that use the same SPD are assigned the same ID by spd_tools. This commit adds support for exclusive IDs. When given an exclusive ID a memory part will not share its ID with other parts unless they also have the same exclusive ID. BUG=b:225161910 TEST=Ran part_id_gen and checked that exclusive IDs work correctly and that the current behavior still works in their abscence. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-08util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)Karthikeyan Ramasubramanian
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Bank ArchitectureKarthikeyan Ramasubramanian
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or 16B Bank Architectures depending on the speed. This influences SDRAM Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the individual SoC advisories. BUG=b:211510456 TEST=Generate SPDs for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17util/spd_tools/spd_gen/lp5: Encode Optional SDRAM featuresKarthikeyan Ramasubramanian
ADL and Sabrina provide different advisories to encode Optional SDRAM features (byte indices 7 & 9). Encode those bytes as per the respective advisories. BUG=b:211510456 TEST=Generate the SPD binaries for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-08util/spd_tools/spd_gen/lp5: Update BusWidth EncodingKarthikeyan Ramasubramanian
ADL and Sabrina have different advisory regarding encoding the bus width. Encode the bus width as per the respective advisories. BUG=b:211510456 TEST=Build spd_gen and ensure that the bus width is encoded as expected. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia12a5bd8f70a70ca8a510ecf00f6268c6904ec25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07util/spd_tools/spd_gen: Add support for Sabrina SoCKarthikeyan Ramasubramanian
Add support to generate SPD binary for Sabrina SoC. Mainboards using Sabrina SoC are planning to use LP5 memory technology. Some of the SPD bytes expected by Sabrina differ from the existing ADL. To start with, memory training code for Sabrina expects SPD Revision 1.1. More patches will follow to accommodate additional differences. BUG=b:211510456 TEST=make -C util/spd_tools. Generate SPD binaries for the existing memory parts in lp5/memory_parts.json and observe that SPDs for Sabrina is generated as a separate set without impacting the ADL mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df Reviewed-on: https://review.coreboot.org/c/coreboot/+/61542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-09util/spd_tools: Document adding support for a new memory technologyReka Norman
Add documentation describing how to add support for a new memory technology to spd_tools: - Add a section to the README. - Document the memTech interface in spd_gen.go. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04util/spd_tools: Add LP5 support for ADLReka Norman
Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23util/spd_tools: Sort platforms_manifest entries by set numberReka Norman
Ensure that the order of entries in each platform manifest is consistent every time spd_gen is run. BUG=b:191776301 TEST=Run spd_gen for lp4x and ddr4, check that the manifests are unchanged. Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23util/spd_tools: Remove PLK platformReka Norman
Currently spd_tools treats PCO and PLK as separate platforms. This is unnecessary since they have the same SPD requirements. Remove PLK, and use PCO as the platform for all zork variants. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21util/spd_tools: Add 'Generated by' string to part_id_gen output filesReka Norman
Add a 'Generated by' string to the generated Makefile.inc and dram_id.generated.txt, showing the command used to generate the files. BUG=b:191776301 TEST=Run part_id_gen, check that the generated files contain the string Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ic9a7826212a732288f36f111b7bc20365a1f702d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21util/spd_tools: Automatically determine the SPD dir in part_id_genReka Norman
Currently, one of the arguments to part_id_gen is the directory containing the SPD files, e.g. spd/lp4x/set-0. This requires the user of the tool to understand the spd/ directory structure, and manually look up the set number corresponding to their platform. Change part_id_gen to take the platform and memory technology as arguments instead of the SPD directory, and automatically determine the SPD directory by reading the platforms manifest file generated by spd_gen.go. BUG=b:191776301 TEST=Run part_id_gen and check that the generated Makefile.inc and dram_id.generated.txt are the same as before. Example: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: I7cd7243d76b5769e8a15daa56b8438274bdd8e96 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21util/spd_tools: Add max ID check for auto-generated IDs to part_id_genReka Norman
Currently, the maximum part ID of 15 is enforced only for manually assigned IDs. Also enforce it for automatically assigned IDs. BUG=b:191776301 TEST=part_id_gen fails when the number of part IDs which would be assigned is greater than MaxMemoryId. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I802190a13b68439ccbcdb28300ccc5fd1b38a9c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20util/spd_tools: Implement a unified version of the part_id_gen toolReka Norman
Currently there are two versions of gen_part_id.go, one for LP4x and one DDR4. This change implements a unified version of this tool. The new part_id_gen.go is almost identical to the existing ddr4/gen_part_id.go. The new version was based on the ddr4 version and not the lp4x version, since the ddr4 version contains extra logic to support fixed IDs in the mem_parts_used files. The only non-trivial change from ddr4/gen_part_id.go is to include the full paths of SPD files in the generated Makefile.inc. E.g. instead of SPD_SOURCES += lp4x-spd-1.hex the full path relative to the coreboot root directory is included: SPD_SOURCES += spd/lp4x/set-0/spd-1.hex BUG=b:191776301 TEST=For each variant of brya/volteer/dedede/guybrush/zork, run part_id_gen and verify that the generated Makefile.inc and dram_id.generated.txt are identical to those currently in the src tree, except for the modified SPD file paths in Makefile.inc. Example: util/spd_tools/bin/part_id_gen \ spd/lp4x/set-0 \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: Ib33d09076f340f688519dae7956a2b27af090c0b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-17util/spd_tools: Implement a unified version of the spd_gen toolReka Norman
Currently there are two versions of spd_tools: one for LP4x and one for DDR4. This change is the first step in unifying these into a single tool. This change implements a unified version of the spd_gen tool, by combining the functionality currently in lp4x/gen_spd.go and ddr4/gen_spd.go. The unified version takes the memory technology as an argument, and generates SPD files for all platforms supporting that technology. BUG=b:191776301 TEST=Compare the SPDs generated by the old and new versions of the tool for all supported platforms. For reference, the test script used is here: https://review.coreboot.org/c/coreboot/+/57511 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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