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Finally all boards use a GCC compiled bootblock!
Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia9f0f1f527476900e6c54c60508600e16bea786f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This makes it easier to check the output against a reference output.
Change-Id: I9c7ae538b708399a5cadd18e498618d7480d240f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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