| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-14 | riscv: add trampoline in MBR block to support boot mode 1 | Philipp Hug |
| 2018-04-26 | src/sifive: Add the SiFive Freedom Unleashed 540 SoC | Jonathan Neuschäfer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |