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2020-02-01util/inteltool: Add GPIO dumping capabilites for Ice Lake U systemsJohanna Schander
This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-05inteltool: add Lewisburg C62x GPIOs supportMaxim Polyakov
These changes are in accordance with the documentation: [*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-31inteltool: Add GPIO support for Skylake-H chipsetsFelix Singer
PCH IDs: - H170, Z170, Q170, Q150, C232, QM170, HM170 Used documents: - Intel 332690-005EN Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-29util/inteltool: Add H110 GPIO supportPavel Sayekat
Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15util/inteltool: Add Kabylake E3-1200 SupportChristian Walter
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06inteltool: Add Sunrise Point-LP Skylake PCH IDsFelix Singer
Sunrise Point-LP is used on Skylake and KabyLake platforms, but the PCH IDs differ. This commit adds the PCH IDs for Skylake mobile platforms and renames the Kabylake macros to distinguish them. Used Intel documents: - 332995-001EN (I/O datasheet vol. 1) - 332996-002EN (I/O datasheet vol. 2) Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-15inteltool: add 300 and C240 Series PCHThomas Heijligen
Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05util/inteltool: Add Apollo Lake GPIO groups and namesNico Huber
Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-21util/inteltool: Add support for DenvertonThomas Heijligen
Used documents: - C3000 Product Family Datasheet Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Co-authored-by: Felix Singer <migy@darmstadt.ccc.de> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/30887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-28util/inteltool: Add support for Sunrise Point LPMatthew Garrett
Used documents: 334658 (Sunrise Point-LP I/O datasheet vol. 1) 334659 (Sunrise Point-LP I/O datasheet vol. 2) 332690 (Sunrise Point I/O datasheet vol. 1) Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/28623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-03-27inteltool: Add some Skylake desktop idsNico Huber
Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/25144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15inteltool: Dump Sunrise Point PCH-H GPIO groupsNico Huber
Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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