coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-08-28	util/inteltool: Don't use old style function definition	Elyes Haouas
	Use "int foo(void)" instead of old-style "int foo()". Change-Id: I609c0332132389c07b03db40dc48dc94ca836a56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10	utils/inteltool: Add support to print Key Locker status	Pratikkumar Prajapati
	Add command-line option "-k" to print status. Sample output: $ inteltool -k ============= Dumping INTEL Key Locker status ============= Key Locker supported : YES AESKL instructions enabled : NO =========================================================== Change-Id: Icb1b08619b1dbc535640127f7ab5f6b49d70a6fe Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2021-08-17	inteltool: Allow to set cores range for MSRs dump	Maxim Polyakov
	Adds the ability to output MSRs dump for the specified range of CPU cores. This makes it easier to reverse engineer server multicore processors using the inteltool utility. The range is set using --cpu-range <start>[-<end>] command line option: $ sudo ./inteltool -M --cpu-range 0-7 $ sudo ./inteltool -M --cpu-range 7-15 $ sudo ./inteltool -M --cpu-range 32 $ sudo ./inteltool -M will print a register dump for all cores, just as before. Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35919 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30	inteltool: Add support to print TME/MKTME status	Pratik Prajapati
	Print whether the SOC supports TME/MKTME. If the SOC supports the feature, print the status of enable and lock bit from TME_ACTIVATE MSR. -t option prints this status. Sample output: If TME/MKTME is supported: ============= Dumping INTEL TME/MKTME status ============= TME supported : YES TME locked : YES TME enabled : YES ==================================================== If TME/MKTME is not supported: ============= Dumping INTEL TME status ============= TME supported : NO ==================================================== Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I584ac4b045ba80998d454283e02d3f28ef45692d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-05-09	util/: Replace GPLv2 boiler plate with SPDX header	Patrick Georgi
	Used commands: perl -i -p0e 's\|\/\[\s].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-2.0-only /\|' $(cat filelist) perl -i -p0e 's\|This[\s]program[\s]is[\s]free[\s]software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]either[\s]version[\s]2[\s]of[\s]the[\s]License,[\s]or[\s].at[\s]your[\s]option.[\s]any[\s]later[\s]version.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-2.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|\/\[\s].This[\s#]program[\s#]is[\s#]free[\s#]software[;:,][\s#]you[\s#]can[\s#]redistribute[\s#]it[\s#]and/or[\s#]modify[\s#]it[\s#]under[\s#]the[\s#]terms[\s#]of[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]as[\s#]published[\s#]by[\s#]the[\s#]Free[\s#]Software[\s#]Foundation[;:,][\s#]either[\s#]version[\s#]3[\s#]of[\s#]the[\s#]License[;:,][\s#]or[\s#].at[\s#]your[\s#]option.[\s#]any[\s#]later[\s#]version.[\s#]This[\s#]program[\s#]is[\s#]distributed[\s#]in[\s#]the[\s#]hope[\s#]that[\s#]it[\s#]will[\s#]be[\s#]useful[;:,][\s#]but[\s#]WITHOUT[\s#]ANY[\s#]WARRANTY[;:,][\s#]without[\s#]even[\s#]the[\s#]implied[\s#]warranty[\s#]of[\s#]MERCHANTABILITY[\s#]or[\s#]FITNESS[\s#]FOR[\s#]A[\s#]PARTICULAR[\s#]PURPOSE.[\s#]See[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]for[\s#]more[\s#]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-3.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\#\s]you[\#\s]can[\#\s]redistribute[\#\s]it[\#\s]and\/or[\#\s]modify[\#\s]it[\s\#]under[\s \#]the[\s\#]terms[\s\#]of[\s\#]the[\s\#]GNU[\s\#]General[\s\#]Public[\s\#]License[\s\#]as[\s\#]published[\s\#]by[\s\#]the[\s\#]Free[\s\#]Software[\s\#]Foundation[;,][\s\#]version[\s\#]2[\s\#]of[\s\#]the[\s\#]License.[\s\#]This[\s\#]program[\s\#]is[\s\#]distributed[\s\#]in[\s\#]the[\s\#]hope[\s\#]that[\s\#]it[\s\#]will[\#\s]be[\#\s]useful,[\#\s]but[\#\s]WITHOUT[\#\s]ANY[\#\s]WARRANTY;[\#\s]without[\#\s]even[\#\s]the[\#\s]implied[\#\s]warranty[\#\s]of[\#\s]MERCHANTABILITY[\#\s]or[\#\s]FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.[\#\s]See[\#\s]the[\#\s]GNU[\#\s]General[\#\s]Public[\#\s]License[\#\s]for[\#\s]more[\#\s]details.\s(# \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.\s(#* \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) Change-Id: I1008a63b804f355a916221ac994701d7584f60ff Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09	AUTHORS, util/: Drop individual copyright notices	Patrick Georgi
	We have the git history which is a more reliable librarian. Change-Id: Idbcc5ceeb33804204e56d62491cb58146f7c9f37 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-10-22	util/inteltool: Add server 5065x CPU model support	Maxim Polyakov
	Adds the MSR table for server family 6 model 85 (5065x) processors (Sky Lake, Cascade Lake, Cooper Lake). The cores number for these processors exceeds the limit of 8 cores (it is hardcoded in cpu.c). For this reason, the patch also adds code that determines the number of processor cores at run time. These changes are in accordance with the documentation: [*] pages: 2-265 ... 2-286, 2-297 ... 2-308. Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2019-10-12	util/inteltool: remove unsupported MSRs for 06_9EH	Maxim Polyakov
	Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12	util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH	Maxim Polyakov
	Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12	util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr	Maxim Polyakov
	According to the documentation [1], IA32_PLATFORM_ID MSR register address should be 17H. [1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s Manual. Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12	util/inteltool: remove duplicate MSR for 06_9EH	Maxim Polyakov
	Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-16	util/inteltool: Shrink buffer size	Jacob Garber
	512 bytes is much too big for this buffer, which only needs to hold a path that will have a length of at most 20. The large buffer size also triggers a -Wformat-truncation warning with GCC since it is later printed into the smaller temp_string array, so shrink it down to something reasonable. Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07	util/inteltool: Make internal functions static	Jacob Garber
	None of these functions are used outside of the files they are defined in, so they can all be static. Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-15	util/inteltool: Add Kabylake E3-1200 Support	Christian Walter
	Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-04	util/inteltool: Add Pentium 4 model f6x	Elyes HAOUAS
	Tested on Pentium 4, CPUID = 0F65 board: NEC 945G-M4. Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-22	util/inteltool: Remove duplicated error message, switch to snprintf	Maciej Suminski
	Passing a string containing output from strerror() to perror() causes double error message display. It is also causing segfaults when the error message is longer than temp_string capacity. To fix the problems, sterror() call has been removed so the error message is printed only once. This could be enough to avoid segfaults, but it is a good practice to limit output size with snprintf(). Change-Id: I5ccc37e404f278cafae0a451c5acaa27d7907cce Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch> Reviewed-on: https://review.coreboot.org/21025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-07-28	util/inteltool: Add support for SGX status	Pratik Prajapati
	Add support for dumping Intel Software Guard Extension (SGX) status. --sgx or -x is the command line switch to get SGX status. The code iterates through all cores and reads MSRs to check if SGX is supported, enabled and the feature is locked. Change-Id: I1f5046c1f6703f5429c8717053ffe9c981cedf6f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20758 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-20	util/inteltool: Use tabs for indents	Elyes HAOUAS
	Change-Id: I9d27c276053c51021166f4b22d150060e415d08f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17025 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-08-01	Remove non-ascii & unprintable characters	Martin Roth
	These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28	util: Correct typo in MSR_EBC_SOFT_POWERON	Elyes HAOUAS
	Change-Id: Iba5fc92d8740d0bb7d41f8a83513ba7fb97be592 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15900 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
	It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
	As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA[, ]02110-1301[, ]USA:Foundation, Inc.:" {} + $ find -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]Suite 330, Boston, MA 02111-1307[, ]USA:Foundation, Inc.:" {} + $ find -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \.patch \ -a \! -name \_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-12-16	inteltool: Start adding Bay Trail	Martin Roth
	- Add silvermont (Bay Trail core) MSRs - these are shared with rangeley/avoton. - Add GPIO values and GPIO muxing information. - Add Bay Trail to the PM list. Still to do: - Northbridge functionality (RCBA, Memory timings, etc.) - Add Graphics registers Change-Id: I9fe0c0f1efe5f4344aeb3bad3f13037555109060 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-27	util/inteltool: Add support for mobile 5 chipset	Vladimir Serbinenko
	Dump registers on mobile 5. Successfully tested on X201. Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/2993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-04-05	inteltool: cpu.c: Use conversion specifier `u` for unsigned integers	Paul Menzel
	Cppcheck [1], a static code analysis tool, warns about the following. $ cppcheck --version Cppcheck 1.59 $ cppcheck --enable=all . […] Checking cpu.c... [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list. [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list. […] And indeed, `core` is an unsigned integer and `man 3 printf` tells the following about conversion specifiers. d, i The int argument is converted to signed decimal notation. […] o, u, x, X The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or unsigned hexadecimal (x and X) notation. So use `u` and Cppcheck does not complain anymore. [1] http://cppcheck.sourceforge.net/ Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3026 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-25	inteltool: Add support for Atom N455 (0x106c0) in CPU MSRs dump	Olivier Langlois
	reference for Atom MSRs are from Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3C: System Programming Guide, Part 3 Order Number 326019, January 2013, Table 35-4, 35-5 Has been successfully tested on the targeted cpu. Change-Id: If94279caeab27121c63ec43c258dc962c167ad51 Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2192 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30	Fix warnings in coreboot utilities.	Stefan Reinauer
	- Fix some poor programming practice (breaks of strict aliasing as well as not checking the return value of read) - Use PRIx64 instead of %llx to prevent compilation warnings with both 32bit and 64bit compilers - Use same compiler command options when linking inteltool and when detecting libpci for inteltool Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/752 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-09-14	inteltool: fixed 64 bit build	Mathias Krause
	The inline assembly for cpuid() was 32 bit specific. Additionally a format string referencing a size_t argument wasn't using the %z length modifier. Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301 Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Reviewed-on: http://review.coreboot.org/211 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14	inteltool: Fixed building of position independent executables	Mathias Krause
	When building a position independent executable (PIE) EBX is used internally by the compiler to generate position independent address references so it cannot be used in the clobber list. Use the already existing code for the Darwin plattform for that case, too -- it'll preserve the EBX value. Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Reviewed-on: http://review.coreboot.org/209 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2010-12-17	inteltool: Model 0xf2x, ICH5, i865 support.	Idwer Vollering
	Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM registers on ICH5. Add ICH5 and i865 to the supported chips list. Enable the dumping of BAR6 on i865. Sample output: Disabling memory access: $ sudo setpci -s 6.0 0x04.b=0x0 $ sudo ./inteltool -m \| head -n 9 Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7 Intel Northbridge: 8086:2570 (i865) Intel Southbridge: 8086:24d0 (ICH5) ============= MCHBAR ============ Access to BAR6 is currently disabled, attempting to enable. Enabled successfully. BAR6 = 0xfecf0000 (MEM) Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-27	- Add support for Intel Pentium III MSRs	Tobias Diedrich
	- pmbase is on southbridge function 3 on I82371XX Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-01	inteltool: basic poulsbo sch support.	Stefan Reinauer
	Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-30	whitespace cleanup inteltool cpu.c	Stefan Reinauer
	Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27	Since some people disapprove of white space cleanups mixed in regular commits	Stefan Reinauer
	while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-21	This patch adds:	Pat Erley
	ICH6 Southbridge, 82915 Series Northbridge, P4 6xx Series CPU to inteltool Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630 installed. Signed-off-by: Pat Erley <pat-lkml@erley.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-21	drop dead code.	Stefan Reinauer
	Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22	Inteltool: Add i830/Tolapai/Ich4 support	Stefan Reinauer
	Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-01	Clean up Mac OS X support of inteltool	Stefan Reinauer
	Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Some minor modifications to allow 64bit/32bit compilation on Darwin git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22	mini fix to reliably compile inteltool on darwin, and on Linux both on ↵	Stefan Reinauer
	x86/x86_64. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04	Patch to util/inteltool:	Stefan Reinauer
	* PMBASE dumping now knows the registers. * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20	split the one file, as the several printing functions will continue to grow	Stefan Reinauer
	immensly when they know more systems / cpus / chipsets Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1