summaryrefslogtreecommitdiff
path: root/util/ifdtool/ifdtool.h
AgeCommit message (Collapse)Author
2019-10-03ifdtool: Add validate option to ifdtoolMathew King
Add an option to ifdtool which validates that the flash regions defined in the descriptor match the coresponding areas in the FMAP. BUG=chromium:992215 TEST=Ran 'ifdtool -t' with a good bios image and verify no issues run 'ifdtool -t' with a bad bios image and verify expected issues Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-07ifdtool: Enable GbE/PDR/EC region access only if they existDuncan Laurie
Instead of assuming GbE/PDR/EC regions may exist or not, check if there is a valid region defined in the descriptor and set the region access permissions based on that. The net effect change is to enable the use of the PDR region on the sarien platform, which also uses the GbE and EC regions. This results in the following example changes: mb/google/sarien (GbE, PDR, EC) . DESC BIOS ME GbE PDR EC -BIOS r rw rw r ------------------------------- +BIOS r rw rw rw r mb/google/eve: (no GbE, no PDR, no EC) . DESC BIOS ME GbE PDR EC -BIOS r rw rw r -ME r rw r -GbE r rw -EC r rw ------------------------------- +BIOS r rw +ME r rw +GbE +EC BUG=b:134703987 Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-21util/ifdtool: Add IceLake platform support under IFDv2Aamir Bohra
Change-Id: Ib69a2cbc3d8ab9f35c940e95b0edb4b04b50b716 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1162995 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/c/29696 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14ifdtool: port the feature to set AltMeDisable/HAP bit hereBill XIE
Port the newest feature of me_cleaner to ifdtool (https://github.com/corna/me_cleaner/ , Discussed in https://github.com/corna/me_cleaner/issues/53 ) to set AltMeDisable (or HAP for skylake/ME11) bit to the IFD to disable ME. In this commit I use (ifd_version >= IFD_VERSION_2) to judge whether HAP instead AltMeDisable should be set, since this condition is only fulfilled on skylake or newer platforms. This feature needs to guess ich revision, which needs guess_ich_chipset() from flashrom to be ported here. Routines to dump those bits are also added. Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-07ifdtool: fix flumap handling in chipsets prior ibex peak/5 seriesStefan Tauner
The Upper Map section in the descriptor contains a database of flash chips (VSCC Table). Its offset is located at a fixed offset from the beginning of the image. ifdtool falsely calculates the offset from the descriptor signature which has moved by 16 bytes with step b of the Ibex Peak (5 series) chipset. This produces bogus output for all chipsets older than that. This patch corrects the behavior by calculating the offset of flumap by adding 4096 - 256 - 4 to the start of the image. Change-Id: I14f029fe702c129dfd8069a58fbd41113700f7ef Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-04ifdtool: Add a list of known platforms that support IFD_VERSION_2Furquan Shaikh
ifdtool has relied on one of the fields within FCBA(read_freq) to determine whether a platform supports IFD_VERSION_1 or IFD_VERSION_2. However, newer platforms like GLK and CNL do not have read_freq field in FCBA and so the value of these bits cannot be used as an indicator to distinguish IFD versions. In the long run, we need to re-write ifdtool to have a better mapping of SoC to IFD fields. But until that is done, this change adds a list of platforms that we know do not support read_freq field but still use IFD_VERSION_2. This change also updates GLK and CNL to pass in platform parameter to ifdtool. BUG=b:79109029, b:69270831 Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-22util/ifdtool: Fix region access control for SKL/KBLFurquan Shaikh
The default values used by ifdtool for setting region access control do not match the expected values for SKL/KBL as per the SPI programming guide. This change adds platform "sklkbl" that sets region access control bits differently for SKL/KBL images. BUG=b:76098647 BRANCH=poppy TEST=Verified that the access control bits on KBL images is set correctly. Change-Id: I1328d8006c25be282b3223268d8f1fd0a64e2ed3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-17ifdtool: redesign some structuresBill XIE
Redesign some array-like structures as true arrays, and rewrite functions to dump them as loops. This commit is one separated from the original I6d05418c. Change-Id: I161c9a2ae83d26e658d67d0804e943fff95fe076 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-17ifdtool: merge region_filenames with region_name(s)Bill XIE
There is no reason to keep a separate region_filenames array, so I merge it into region_name(s). This commit is one separated from the original I6d05418c. Change-Id: I38489c6d3b3c161e9b0281188e6cdd0b62e38335 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21509 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-17ifdtool: Const-correct and redesign some functionsBill XIE
Const-correct some functions which do not write back, and use pointers to access existing region_t variables. The last changeset is dismantled this time. This commit is only focused on const-correctness. Change-Id: I6d05418c8b32fa31dcd038a3e56f9aefe13fa9c4 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21288 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2016-11-08ifdtool: Add option to specify platform (-p) quirksAndrey Petrov
Apollo Lake uses yet another descriptor format where only two masters are used: CPU/BIOS and CSE/TXE. CSE stores data in a region number 5 that has not been used previously and CPU must not write it. Add quirk (-p aplk) that locks descriptor according to recommended values. BUG=chrome-os-partner:58974 TEST=ifdtool -p aplk -l bios.bin; ifdtool -d bios.bin.new. Make sure FLMSTR1 and FLMSTR2 are set correctly. unlock with -l and make sure FLMSTRs are restored. Change-Id: I3f33372bef3ff75d0e34030694c79cd07d5540de Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17202 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-17ifdtool: Properly set + decode flmstr regs for IFD v2Shawn Nematbakhsh
flmstr register bits have slightly different meaning for IFD v2. BUG=chrome-os-partner:45091, chrome-os-partner:43461 TEST=Run `ifdtool -d image.bin` on IFD v1 locked squawks image: Found Master Section FLMSTR1: 0x0a0b0000 (Host CPU/BIOS) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x0c0d0000 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0x08080118 (GbE) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: disabled Requester ID: 0x0118 Then, run `ifdtool -l image.bin` and verify newly locked image is identical. Next, run `ifdtool -l image.bin` on unlocked glados image. Verify that locked and unlocked regions are identical to above. Finally, burn glados image, run `flashrom -V`, and verify ME regions is locked and descriptor region is RO. BRANCH=None Change-Id: I8a65bdc5edd0d888138b88c1189f8badd1404b64 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11c434835a66a50ab2c0c01a084edc96cbe052da Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I875dfce6f5cf57831714702872bfe636f8f953f4 Original-Reviewed-on: https://chromium-review.googlesource.com/298968 Original-Commit-Ready: Shawn N <shawnn@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-19ifdtool: Update to support Skylake+ descriptor formatDuncan Laurie
The descriptor format has changed with Skylake and some fields have moved or been expanded. This includes new SPI frequencies and chip densities, though unfortunately 30MHz in the new format conflicts with 50MHz in the old format... There are also new regions with a few reserved regions inserted before a new embedded controller region. Unfortunately there does not seem to be a documented version field so there does not seem to be an official way to determine if a specific descriptor is new or old. To work around this ifdtool checks the hardcoded "SPI Read Frequency" to see if it set for 20MHz (old descriptor) or 17MHz (new descriptor). BUG=chrome-os-partner:40635 BUG=chrome-os-partner:43461 BRANCH=none TEST=run ifdtool on skylake and broadwell images Original-Change-Id: I0561b3c65fcb3e77c0a24be58b01db9b3a36e5a9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281001 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: I9a08c26432e13c4000afc50de9d8473e6f911805 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293240 Reviewed-on: http://review.coreboot.org/11228 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-28util/ifdtool: add option to dump flashrom layoutChris Douglass
Dump the Intel Flash Descriptor map in the format expected by flashrom's "layout" option. Example usage: Given a 4MB flash image vpx7654.bin that was generated by Intel's FITC tool for a 6-Series chipset... ./ifdtool --layout l.txt vpx7654.bin cat l.txt 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me 00fff000:00000fff gbe 00fff000:00000fff pd Change-Id: Ib740178ed6935b5f6e1dba1be674303f9f980429 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5306 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12ifdtool: Dump more registers from FDStefan Reinauer
Only thing not decoded now are the PCH straps ifdtool -d path/to/image.bin File path/to/image.bin is 4096 bytes Found Flash Descriptor signature at 0x00000010 FLMAP0: 0x02040003 NR: 2 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x12100206 ISL: 0x12 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210120 PSL: 0x2101 FMSBA: 0x200 FLUMAP1: 0x000004df Intel ME VSCC Table Length (VTL): 4 Intel ME VSCC Table Base Address (VTBA): 0x000df0 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB JID1: 0x001720c2 SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x20 SPI Componend Vendor ID: 0xc2 VSCC1: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x07ff0180 Flash Region 1 (BIOS): 00180000 - 007fffff FLREG2: 0x017f0001 Flash Region 2 (Intel ME): 00001000 - 0017ffff FLREG3: 0x00001fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00001fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x64900024 Dual Output Fast Read Support: supported Read ID/Read Status Clock Frequency: 50MHz Write/Erase Clock Frequency: 50MHz Fast Read Clock Frequency: 50MHz Fast Read Support: supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x000060c7 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x60 Invalid Instruction 0: 0xc7 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x0820d602 PCHSTRP1: 0x0000010f PCHSTRP2: 0x00560000 PCHSTRP3: 0x00000000 PCHSTRP4: 0x00c8e000 PCHSTRP5: 0x00000000 PCHSTRP6: 0x00000000 PCHSTRP7: 0xc0001ae0 PCHSTRP8: 0x00000000 PCHSTRP9: 0x30000580 PCHSTRP10: 0x00410044 PCHSTRP11: 0x99000097 PCHSTRP12: 0x00000000 PCHSTRP13: 0x00000000 PCHSTRP14: 0x00000000 PCHSTRP15: 0x0000033e PCHSTRP16: 0x00000000 PCHSTRP17: 0x00000002 Found Master Section FLMSTR1: 0x0a0b0000 (Host CPU/BIOS) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x0c0d0000 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0x08080118 (GbE) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: disabled Requester ID: 0x0118 Found Processor Strap Section ????: 0x00000000 ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff Change-Id: I68a613df2fd80e097cdea46fbad104d7c73ac9ad Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1756 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09ifdtool: Add locking/unlocking and dumping of access permissionsStefan Reinauer
ifdtool will now dump access permissions of system comonents to certain IFD sections: Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x0c0d0000 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0x08080118 (GbE) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: disabled Requester ID: 0x0118 Also, ifdtool -u /path/to/image will unlock the host's access to the firmware descriptor and ME region. ifdtool -l /path/to/image will lock down the host's access to the firmware descriptor and ME region. Change-Id: I3e081b80a9bcb398772416f143b794bf307b1c36 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1755 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-05-24Add EM100 mode to Intel Firmware Descriptor toolStefan Reinauer
To avoid having two copies for every firmware descriptor (one for EM100 use and one for real SPI flash use), add an EM100 mode to ifdtool that allows to "dumb down" a fast image to the settings required for the EM100 to work. Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1039 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-10-22Add ifdtool, utility to read / modify Intel Firmware Descriptor imagesStefan Reinauer
Change-Id: Ie78b97bf573d238d0dff9a663e774deb1b7dea44 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 15:38:39 +0000