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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.
From July 2008.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This has been tested by Uwe Hermann on an RS690/SB600 board.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID
RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.
The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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which support all commands, but may not exist.
For controllers which support only a subset of commands, it will fail in
unexpected ways. Even if a command is supported by the controller, it
may be unavailable if the controller is locked down.
The new logic checks if RDID could be issued and its return values made
sense (not 0xff 0xff 0xff). In that case, RES probing is not performed.
Otherwise, we try RES.
There is one drawback: If RDID returned unexpected values, we don't
issue a RES probe. However, in that case we should try to match RDID
anyway.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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does not have a mechanism to signal command failure, the SPI host may be
unable to send a given command over the wire due to security or hardware
limitations. The current code ignores these mechanisms completely and
simply assumes almost every command succeeds. Complain if SPI command
execution fails.
Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.
Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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flashrom. Not all chips support all commands, so allow the implementer
to select the matching function.
Fix a layering violation in ICH SPI code to be less bad. Still not
perfect, but the new code is shorter, more generic and
architecturally
more sound.
TODO (in a separate patch):
- move the generic sector erase code to spi.c
- decide which erase command to use based on info about the chip
- create a generic spi_erase_all_sectors function which calls the
generic sector erase function
Thanks to Stefan for reviewing and commenting.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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using block erase d8 as discussed with Peter Stuge
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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While writing a new SPI driver I fixed some things in the SPI code:
All calls to spi_command() had unneccessary #define duplications, and in some
cases the read count define could theoretically become harmful because NULL was
passed for the read buffer. Avoid a crash, should someone change the #defines.
I also noticed that the only caller of spi_page_program() was the it87 driver,
and spi_page_program() could only call back into the it87 driver. Removed the
function for easier-to-follow code and made it8716f_spi_page_program() static.
The ichspi driver's static page functions are already static.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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construct: the flash bus.
At some point the flash bus will be part of struct flashchip.
Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.
Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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few documented exceptions to ICH7 SPI controller.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Preparation for a probe optimization patch. This patch does not change any
functionality. spi_probe_rdid was tested to still work on my M57SLI rev 2.
The idea is to have error checks return error immediately when something
fails, rather than having code inside an if block where the condition
tests for success.
This means: Less indentation, more clear what the code is checking.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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interface.
Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Powerdown) SPI command to flashrom to identify older SPI chips which
can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
shared among many different vendors and even different sizes, we want to
match RES as a last resort if RDID returns 0xff 0xff 0xff.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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detected by JEDEC probe routines all have vendor IDs with correct
parity. Use a parity check as additional hint whether a vendor ID makes
sense.
Note: Device IDs have no parity requirements whatsoever.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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file it87spi.c.
No behavioural changes, but greatly improved SPI abstraction.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This patch has no code changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ICH9 SPI support. In theory, this patch has no behaviour changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This paves the way to have a fully generic generic_spi_command without
knowledge about any SPI controller.
The third step would be calling SPI controller functions via a function
pointer.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is a very early step toward cleaning up SPI code in flashrom.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Programmable Micro Corp (PMC) need this.
Both the serial and parallel flash JEDEC detection routines would
benefit from a parity/sanity check of the vendor ID. Will do this later.
Add support for the PMC Pm25LV family of SPI flash chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard <chris@stockwith.co.uk>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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programming.
Minor formatting changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Super I/O performing LPC-to-SPI flash translation.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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unknown.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7). That way, you only have to
take a short look at the data sheet and choose the right function by
appending the opcode listed in the data sheet.
No functional changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Print status register before erase to help debugging block locks.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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them yet.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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status register instead.
This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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chip the code was tested and verified with is the Macronix MX25L4005,
but other chips should work as well.
Timeouts are still hardcoded to data sheet maxima, but the status
register checking code is already there.
Thanks to Harald Gutmann for the initial code on which this is loosely
based.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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applying abstraction and wrapping.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Move SPI code out of board_enable.c where it started its life. The SPI
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.
The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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