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path: root/util/flashrom/flash.h
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2009-04-24MAX may already be defined. Also, fix smaller cosmetics (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23flashrom: Support MX25L3235DStephan Guilloux
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21flashrom: Support Macronix MX2512805D flash chipStephan Guilloux
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06FreeBSD definitions of (read|write)[bwl] collide with our own. Before weCarl-Daniel Hailfinger
attempt trickery, we can simply rename the accessor functions. Patch created with the help of Coccinelle. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <idwer_v@hotmail.com> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-05flashrom: Use helper functions to access flash chips.Carl-Daniel Hailfinger
Right now we perform direct pointer manipulation without any abstraction to read from and write to memory mapped flash chips. That makes it impossible to drive any flasher which does not mmap the whole chip. Using helper functions readb() and writeb() allows a driver for external flash programmers like Paraflasher to replace readb and writeb with calls to its own chip access routines. This patch has the additional advantage of removing lots of unnecessary casts to volatile uint8_t * and now-superfluous parentheses which caused poor readability. I used the semantic patcher Coccinelle to create this patch. The semantic patch follows: @@ expression a; typedef uint8_t; volatile uint8_t *b; @@ - *(b) = (a); + writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + readb(b) @@ type T; T b; @@ ( readb | writeb ) (..., - (T) - (b) + b ) In contrast to a sed script, the semantic patch performs type checking before converting anything. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: FENG Yu Ning <fengyuning1984@gmail.com> Tested-by: Joe Julian git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: Driver for ST M29F002T/NT/B. T/NT TEST_OK_ PROBE READ ERASE WRITEPeter Stuge
Test report from Julia. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Julia Longtin <juri@solarnetone.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: SST25VF040B using 0x90 identification and AAI write.Peter Stuge
SST AAI is Auto Address Increment writing, a streamed write to the flash chip where the first write command sets a starting address and following commands simply append data. Unfortunately not supported by Winbond SPI masters. From July 2008. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: Winbond SuperIO SPI driver.Peter Stuge
Developed and tested to work on Intel D201GLY in July 2008. Tested by a helpful person on IRC whose name I've since forgotten. Sorry! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: Export Winbond SuperIO register access functions in board_enable.c.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: Darwin / Mac OS XStefan Reinauer
Through DirectIO from coresystems GmbH we now support Darwin/Mac OS X. DirectIO is available at http://www.coresystems.de/en/directio Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: Abstract mmap() in physmap.c and only open /dev/mem on the first ↵Stefan Reinauer
physmap() call. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: Change flashrom.c:map_flash_registers() from int to void.Peter Stuge
The function exit()s on failure, and no callers check the return value. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26flashrom: Change FreeBSD #ifdef into #if defined()Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-23flashrom: Check all mmap() calls and print helpful Linux error message.Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07Add SST49LF020 support.Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-15* add a generic preop-opcode-pair table.FENG yu ning
* rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-10Add 28 flash chips of the MX29 series to the flashrom ID table andCarl-Daniel Hailfinger
support the MX29LV040C. MX29LV040C probe and read support tested by khetzal on IRC. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPIFENG yu ning
configuration is locked down. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04Add RDID/REMS IDs for the following flash chips:Carl-Daniel Hailfinger
SST_25VF512A_REMS SST_25VF010_REMS SST_25VF020_REMS SST_25VF040_REMS SST_25VF040B_REMS SST_25VF080_REMS SST_25VF080B_REMS SST_25VF032B_REMS SST_26VF016 SST_26VF032 W_25X16 W_25X32 W_25X64 Straight from the data sheets. The REMS IDs help in case the RDID opcode is unavailable (due to opcode lockdown) or unsupported by the chip. Some day, we need to pair probe functions together with IDs. Multiple pairs can exist per chip and duplicating chip definitions does not really make sense. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03Replace #ifdefs for sc520 systems by run time probing.Stefan Reinauer
fixes #109 Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28If a chip has any TEST_BAD_* flag set, we don't even list theCarl-Daniel Hailfinger
unsupported functions, giving the user the impression that the unsupported functions are tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Add support for the AMD/ATI SB600 southbridge SPI functionality.Jason Wang
This has been tested by Uwe Hermann on an RS690/SB600 board. Signed-off-by: Jason Wang <Qingpei.Wang@amd.com> Reviewed-by: Joe Bao <zheng.bao@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28Flashrom already has the following probe functions:Carl-Daniel Hailfinger
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID - probe_spi_res with opcode 0xab, usually 1 byte ID We are missing the following probe function: - probe_spi_rems with opcode 0x90, usually 2 bytes ID RDID provides best specifity (manufacturer, device class and device) and RES is supported by quite a few old chips. However, RES only returns one byte and there are multiple flash chips with different sizes on the market and all of them have the same RES ID. REMS is from the same age as RES, but it provides a manufacturer and a device ID. It is therefore on par with the probing for parallel flash chips and specific enough. The order in which chips should be detected is as follows: 1. RDID 2. REMS 3. RES Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18Check for failed SPI command execution in flashrom. Although SPI itselfCarl-Daniel Hailfinger
does not have a mechanism to signal command failure, the SPI host may be unable to send a given command over the wire due to security or hardware limitations. The current code ignores these mechanisms completely and simply assumes almost every command succeeds. Complain if SPI command execution fails. Since locked down Intel chipsets (like the one we had problems with earlier) only allow a small subset of commands, find the common subset of commands between the chipset and the ROM in the chip erase case. That is accomplished by the new spi_chip_erase_60_c7() which can be used for chips supporting both 0x60 and 0xc7 chip erase commands. Both parts of the patch address problems seen in the real world. The increased verbosity for the error case will help us diagnose and address problems better. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-15The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.Carl-Daniel Hailfinger
The AT45 series SPI chips are DataFlash EEPROMs which means they have odd (non-power-of-two) sector sizes, but some of the DataFlash chips can be configured or ordered with power-of-two sector sizes. Add probe support for the following Atmel SPI chips: AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321A AT25DF641 AT25F512B AT25FS010 AT25FS040 AT26DF041 AT26DF081A AT26DF161 AT26DF161A AT26DF321 AT26F004 AT45CS1282 AT45DB011D AT45DB021D AT45DB041D AT45DB081D AT45DB161D AT45DB321C AT45DB321D AT45DB642D Add an explanation why the following chips can't be probed: AT45BR3214B AT45D011 AT45D021A AT45D041A AT45D081A AT45D161 AT45DB011 AT45DB011B AT45DB021A AT45DB021B AT45DB041A AT45DB081A AT45DB161 AT45DB161B AT45DB321 AT45DB321B AT45DB642 Add the ID, but no probing function for this chip: AT25F512A Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-04Add support for 8 new chips to flashrom and fix up 2 existing chipsCarl-Daniel Hailfinger
as well. Replace age-old TODO comments with real explanations. Fixed chips: Fujitsu MBM29F400TC (ID definition) Macronix MX29F002T (chip name) New chips: Fujitsu MBM29F004BC Fujitsu MBM29F004TC Fujitsu MBM29F400BC Macronix MX25L512 Macronix MX25L1005 Macronix MX25L2005 Macronix MX25L6405 Macronix MX29F002B Straight from the data sheets, compile tested only. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03Add additional SPI sector erase and chip erase command functions toCarl-Daniel Hailfinger
flashrom. Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Add support for the ST M50FW002 chip to flashrom. Identification only,Carl-Daniel Hailfinger
erase/write are not implemented. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested and Acked-by: Elia Yehuda <z4ziggy@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Flashrom support for some Numonyx parts (M25PE)Stefan Reinauer
using block erase d8 as discussed with Peter Stuge Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18Coding-style fixes for flashrom, partly indent-aided (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-07Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.Mats Erik Andersson
Probing, reading, and erasing use the Jedec-routines, whereas writing resort to the recent write_en29f002a(), since also these chips use a byte wise algorithm. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26Activate proper support for EN29F002(A)(N)[BT].Mats Erik Andersson
Fully tested for Probe/Read/Erase/Write on EN29F002NT. Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()' are still in use, but a tailored 'write_en29f002a()' is needed due to a byte wise writing mechanism for this chip. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21flashrom: Winbond W39V040C and MSI K8T Neo2-FPeter Stuge
W39V040C does standard JEDEC commands except chip erase so add a small driver. probe_w39v040c() prints the block lock pin status when a chip is found. The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs. Many thanks to Daniel McLellan for testing all of this on hardware! Build tested by Uwe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07flashrom: Trivial SPI cleanupsPeter Stuge
While writing a new SPI driver I fixed some things in the SPI code: All calls to spi_command() had unneccessary #define duplications, and in some cases the read count define could theoretically become harmful because NULL was passed for the read buffer. Avoid a crash, should someone change the #defines. I also noticed that the only caller of spi_page_program() was the it87 driver, and spi_page_program() could only call back into the it87 driver. Removed the function for easier-to-follow code and made it8716f_spi_page_program() static. The ichspi driver's static page functions are already static. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06r3415 removed symbolic constants for device IDs by accident.Carl-Daniel Hailfinger
flash.h is a database of known IDs, whereas flashchips.c is a database of chips for which support has been implemented. Keep it that way. Trivial. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06flashrom: Add AMIC A29002Andreas Thienemann
This patch adds support to the AMIC A29002 chip in its top and bottom configuration to flashrom. Additionally, the alphabetic order of the AMIC chips was fixed. The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>. A29002T PREW functionality was tested and works. This flash chip has asymmetric sector layout so it is important to use the mx29f002 driver, which does chip erase before writing, rather than am29f040b, which uses sector erase. Signed-off-by: Andreas Thienemann <andreas@bawue.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30First attempt to clean up SPI probing and create a commonStefan Reinauer
construct: the flash bus. At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30Mine AMIC flash chip needs 4 bytes RDID. Following patch adds support for that.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30This patch adds support for VIA SPI controller on VT8237S. It is similar withRudolf Marek
few documented exceptions to ICH7 SPI controller. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27* ICH7 SPI supportStefan Reinauer
* fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22flashrom: Remove dead M-Systems Disk on Chip codePeter Stuge
DOC support has been disabled by default for many years. The write function does nothing but print text. It has a call to write_page_md2802() commented out, but that function does not exist. This is dead code with ugly #ifdefs. Updates README to reflect that there was a time when there was code, but it didn't work. Removes M-Systems #defines and also includes svn rm msys_doc.* Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18flashrom: Add support for AMIC Technology A49LF040A and do not probe ↵Jens Kuehnel
W29EE011 anymore Jens sent the first patch that added A49LF040A to flash.h and flashchips.c using _jedec and _49lf040 functions. An issue was found with probe_w29ee011() for the Winbond W29EE011, which caused the A49LF040A to no longer respond to any commands. Ward made a patch to disable probing by default for the W29EE011 following some discussion. Using -c W29EE011 will make flashrom probe for the chip. Peter did some more datasheet diving and found that the Pm49FL00x functions suited this chip quite well because of the block locking registers in A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3. Ward confirmed that this works on alix.2c3 too. Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org> Signed-off-by: Ward Vandewege <ward@gnu.org> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18flashrom: Force read unknown flash chipsPeter Stuge
When flash chip detection fails, it is still useful and possible to read the flash chip contents. If no flash chip is found in normal probes and the -f -r -c CHIPNAME options are given, a successful probe for the specified chip is forced, and then flashrom reads the flash chip using either the read function for the specified chip, or if there is none, a simple memcpy(). The patch also moves the global variable int force in flashrom.c into main() and passes it as a parameter to layout.c:show_id(), which was the only other function that used the variable. This is needed to avoid confusion with the new parameter int force which is added to flashrom.c:probe_flash() and used to force probe success for the chip named in char *chip_to_probe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11flashrom: Add support for Amic Technology A29040B flash chip.Peter Stuge
PROBE READ tested by Lyos Gemini Norezel on BioStar P4M80-M4. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27Revert r3357 and fix it as intended to (forgotten header commit instead of typo)Mart Raudsepp
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22Add support for Amic A25L40P SPI flash.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22Changes to make flashrom compile (and work) on FreeBSD.Andriy Gapon
This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17flashrom: Support Pm49FL004/2 Block Locking RegistersNikolay Petukhov
The PMC chips understand both LPC and FWH flash commands. When in FWH mode (MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block Locking Registers by default lock the flash chip for write and erase - in addition to any chipset write protection. This patch adds unlock operations before Pm49FL004/2 write and erase, and it includes an svn mv pm49fl004.c pm49fl00x.c Thanks go to Nikolay for this patch. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16Add support for SPI chips on ICH9. This is done by using the generic SPIDominik Geyer
interface. Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Lots of new SST flash chip IDs. Only a subset has been added toCarl-Daniel Hailfinger
flashchips.c, but the IDs in flash.h will make lookups easier if anybody wants to add support for them. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15Add support for the JEDEC RES (Read Electronic Signature and Resume fromCarl-Daniel Hailfinger
Powerdown) SPI command to flashrom to identify older SPI chips which can't handle JEDEC RDID. Since RES gives a one-byte identifier which is shared among many different vendors and even different sizes, we want to match RES as a last resort if RDID returns 0xff 0xff 0xff. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> This is a heavily reworked version of a patch by Fredrik Tolf, which was Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add more infrastructure for flashrom ICH9 support.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Check the JEDEC vendor ID for correct parity. Flash chips which can beCarl-Daniel Hailfinger
detected by JEDEC probe routines all have vendor IDs with correct parity. Use a parity check as additional hint whether a vendor ID makes sense. Note: Device IDs have no parity requirements whatsoever. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add lots of ATMEL SPI flash chips to flash.h.Carl-Daniel Hailfinger
Add a few flashchips already mentioned in flash.h to flashchips.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13flashrom: Move all IT87xx specific SPI routines from spi.c to a separateCarl-Daniel Hailfinger
file it87spi.c. No behavioural changes, but greatly improved SPI abstraction. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OKCarl-Daniel Hailfinger
by Harald Gutmann. SST39VF040 has been confirmed to probe OK by misi e. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LFCarl-Daniel Hailfinger
series has the same IDs. Add short AMIC vendor ID to flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10flashrom: Rename generic_spi_*() functions to spi_*()Peter Stuge
This is a very early step toward cleaning up SPI code in flashrom. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-03flashrom: Add a tested bitmap field to the flash chip table.Peter Stuge
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE. 8 bits out of 32 are in use now. No bits set means nothing has been tested. For chips with at least one operation that is not tested or not working, the user is asked to email a report to a special email adress so that the table can be updated. All chips are TEST_UNTESTED for now. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28The generic jedec.c does not work for the ST M50FLW flashClaus Gindhart
devices, because they need an unlock command first. For this reason, ST M50FLW support is moved to a new HW support module, because any change in jedec.c would bear the risk to cause problems with the already supported devices. It's already tested with ST M50FLW080A; the other chips of this family i dont have available, so i couldnt test it. Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17Support for the Winbond W39V080FA series of chips.Stefan Reinauer
Support for flashing on the Kontron 986LCD-M board. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Re-add code erroneously removed in r3140.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14Revert the delete of 82802ab.c in r3137.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13Also print the chip vendor name in --list-supported output (trivial).Uwe Hermann
Cosmetic changes in some files, partly bending the 80-characters-per-line rule in this special case, as the 80-character-limited version looks equally crappy even in an 80x25 console/xterm, so let's make it at least look good in a high-resolution xterm. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12Add --list-supported option to flashrom which lists the supportedUwe Hermann
ROM chips, chipsets, and mainboards (Closes #90). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-06Handle JEDEC JEP106W continuation codes in SPI RDID. Some vendors likeCarl-Daniel Hailfinger
Programmable Micro Corp (PMC) need this. Both the serial and parallel flash JEDEC detection routines would benefit from a parity/sanity check of the vendor ID. Will do this later. Add support for the PMC Pm25LV family of SPI flash chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Chris Lingard <chris@stockwith.co.uk> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25Add ids and chip entry for Spansion S25FL016A to flashrom, tested,Peter Stuge
working. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19Support SPI flash chips bigger than 512 kByte sitting behind IT8716FRonald Hoogenboom
Super I/O performing LPC-to-SPI flash translation. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18for some reasons the externals did not get committed.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-04Print at least the vendor for SPI flash chips if the exact chip ID isCarl-Daniel Hailfinger
unknown. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all haveCarl-Daniel Hailfinger
exactly the same ID. Improve model number printing. Add EN29F002(A)(N)B support while I'm at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Markus Boas <bios@ryven.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31Add continuation ID support to jedec.cCarl-Daniel Hailfinger
The continuation ID code does not go further than checking for IDs of the type 0x7fXX, but does this for vendor and product ID. The current published JEDEC spec has a list where the largest vendor ID is 7 bytes long, but all leading bytes are 0x7f. The list will grow in the future, and using a 64bit variable will not be enough anymore. Besides that, it seems that the location of the ID byte after the first continuation ID byte is very vendor specific, so we may have to revisit that code some time in the future. (Suggestion for a new encoding: Use a two-byte data type for the ID, the lower byte contains the only non-0x7f byte, the upper byte contains the number of 0x7f bytes used as prefix, which is the bank number minus 1 the vendor ID appears in.) Add support for EON EN29F002AT. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31This fixes a few vendor IDs to conform with JEDEC publication 106WCarl-Daniel Hailfinger
(JEP106W), adds some device IDs and provides information about non-conforming IDs. The EON change is left to the patch adding EON chips. This patch should have no effect on code generation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32,Carl-Daniel Hailfinger
M25P64, M25P128 to flashrom. ST M25P80 support is already there. Not tested, but conforming to data sheets and double checked. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17To make it easier to add new SPI chips to flashchips.c, rename functionsCarl-Daniel Hailfinger
with multiple possible opcodes from linear numbering at the end (_1, _2) to include the opcode at the end (_60, _c7). That way, you only have to take a short look at the data sheet and choose the right function by appending the opcode listed in the data sheet. No functional changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-16Add support for ST M25P80 chips to flashrom. Detection was tested.Carl-Daniel Hailfinger
Print status register before erase to help debugging block locks. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-10Add support for more atmel chips:Frederico Silva
AT49F002 AT49F002N AT49F002T AT49F002NT Only tested the read function on AT49F002T. datasheet @ http://www.atmel.com/atmel/acrobat/doc1017.pdf Signed-off-by: Frederico Silva <frederico.silva@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-04Various coding style fixes, constification, fixed typos (trivial).Uwe Hermann
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30Add support for Intel 440MX systems.Uwe Hermann
Add support for the Fujitsu MBM29F400TC flash part. Detection and reading works, writing is not tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-25Added Am29LV040BPeter Lemenkov
Looking through the sources of Uniflash utility I found that this chip is no more no less than low-voltage variant of Am29F040B but with different ID. So I created a very quick patch (attached). Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22Flashrom: Add more Vendor IDs and ensure correct sorting in flash.h.Peter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22Introduce block and sector erase routines to flashrom, but do not useCarl-Daniel Hailfinger
them yet. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18Add generic SPI flash erase and write support to flashrom. The firstCarl-Daniel Hailfinger
chip the code was tested and verified with is the Macronix MX25L4005, but other chips should work as well. Timeouts are still hardcoded to data sheet maxima, but the status register checking code is already there. Thanks to Harald Gutmann for the initial code on which this is loosely based. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16Convert the existing it8716f_* functions to generic_spi_* functions byCarl-Daniel Hailfinger
applying abstraction and wrapping. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15Move SPI code out of board_enable.c where it started its life. The SPICarl-Daniel Hailfinger
chip finding and SPI chip accessor code is moved as well. This can be split later if we feel like it. The non-use of svn cp is intentional because the only history we'd have to preserve are a few commits which were early prototypes of chip identification code. For those who intend to look at that history, they can look at board_enable.c revision 2853. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-02This patch aims to restructure SPI flash support in a more reasonableCarl-Daniel Hailfinger
way. It introduces a generic SPI host driver for the IT8716F Super I/O which will enable easy SPI programming without having to care for the peculiarities of the SPI host. To activate probing for the IT8716F, you have to use the gigabyte:m57sli mainboard override. SPI support will then use the gathered SPI host data to access the SPI flash. This has been tested sucessfully by Ward Vandewege <ward@gnu.org> on the GA-M57SLI v2.0, which has a MX25L4005 SPI flash part. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09Remove useless 'extern' keywords (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09Add '(C)' where it's missing (for consistency reasons).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30Add support for the Winbond W29EE011.Markus Boas
Signed-off-by: Markus Boas <ryven@ryven.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30Add support for the Winbond W29C040P.Markus Boas
Signed-off-by: Markus Boas <ryven@ryven.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-29Change all flashrom license headers to use our standard format.Uwe Hermann
No changes in content of the files. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23Drop a bunch of useless header files, merge them into flash.h.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-25This patch adds support for the M50FLW040A, M50FLW040B, M50FLW080A,Carl-Daniel Hailfinger
M50FLW080B, M50FW080, M50FW016, M50LPW116, M29W010B flash chips made by ST to flashrom. The patch is based on the data sheets of the chips and has not been tested at all. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-24This patch adds support for ST M50FW040 and ST M29W040B to flashrom.Carl-Daniel Hailfinger
Only reading from the chips was tested; writing support is untested. Thanks to Gürkan Sengün <gurkan@linuks.mine.nu> for testing! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24factor out register mapping code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-23big cosmetic offensive on flashrom. (trivial)Stefan Reinauer
* Give decent names to virt_addr and virt_addr_2 * add some comments * move virtual addresses to the end of the struct, so they dont mess up the initializer. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21Add support for the Winbond W39V040FA chip.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09Fix coding style of flashrom by running indent on all files:Uwe Hermann
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch] Some minor fixups were required, and maybe a few more cosmetic changeѕ are needed. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-28Add initial support for the following flash chips:Uwe Hermann
- Atmel AT29C020 - STMicroelectronics M29F002B - STMicroelectronics M29F002T - STMicroelectronics M29F002NT Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Signed-off-by: Roger Zauner <roger@eskimo.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06Trivial (cosmetic) cleanup:Stefan Reinauer
* Only open /dev/mem once and do it early. * Drop extern for function prototypes. * Minimize ts5300 impact in probe_flash() This cleanup will making ICH7 SPI support quite some easier. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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