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This commit adds support for LP5X SDRAM.
BUG=b:242765117
TEST=Ran with LP5X SPDs and manually patched APCB
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I2d3cb9c9a1523cb4c5149ede1c96a16c3991a5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66840
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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APCB edit tool edits APCBs with LP4 specific SPDs. Introduce an option
to support different SPD magic so that the tool can be used to edit
APCBs with LP5 specific SPDs.
BUG=None
TEST=Build Skyrim board with LP5 specific SPDs. Build Guybrush board
with LP4 specific SPDs.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63598
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
up to 16 SPDs into an existing APCB. The APCB must have a magic number
at the top of each SPD slot.
BUG=b:209486191
BRANCH=None
TEST=Inject 4 SPDs into magic APCB, boot guybrush with modified APCB
Change-Id: I9148977c415df41210a3a13a1cd9b3bc1504a480
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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New util directories have been added with no description.md file.
The description file for supermicro was added at a secondary level,
which doesn't help a user find the util since no path was added. Move
it up to the top level.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
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Passing binary SPD files to apcb_edit can lead to an encoding error,
since the files were read in text mode. To fix this, read SPD files
always in binary mode and only decode them, when `--hex` is set.
Tested by comparing output files from the same SPDs in both, binary and
hex mode.
Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Strip manufacturer information from SPDs before injecting into APCB.
This allows more flexibility around changing DRAM modules in the future.
BUG=b:162098961
TEST=Boot, dump memory info
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Print adds a newline implicitly. Simply remove the extra newlines.
BUG=None
TEST=Build zork, observe build log
Change-Id: Idb150c12c90719ba1465e7e7fe45c26d456e2a1c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code was written on a workstation that has python
pointing to python3.
BUG=b:157140753
TEST=Built trembyle and was able to boot to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I181d87aad1ffb10e12f8ffd7513318f6d6bcbc3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41739
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On the Picasso architecture, the PSP is responsible for setting up DRAM
before releasing the x86. The APCB (AGESA PSP Configuration Block)
contains multiple SPDs and the GPIO numbers used to select the correct
SPD. Since the source to build the APCBs is not public, it can't be
built as part of the coreboot build. To work around this problem, we use
a template APCB and inject the relevant information.
BUG=b:147042464
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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