coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-05-27	util/apcb: Use python3 for apcb_edit.py	Raul E Rangel
	The code was written on a workstation that has python pointing to python3. BUG=b:157140753 TEST=Built trembyle and was able to boot to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I181d87aad1ffb10e12f8ffd7513318f6d6bcbc3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41739 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18	util/apcb: Add apcb_edit tool	Rob Barnes
	On the Picasso architecture, the PSP is responsible for setting up DRAM before releasing the x86. The APCB (AGESA PSP Configuration Block) contains multiple SPDs and the GPIO numbers used to select the correct SPD. Since the source to build the APCBs is not public, it can't be built as part of the coreboot build. To work around this problem, we use a template APCB and inject the relevant information. BUG=b:147042464 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I88a09743f8e8a184c47071ee5e417f5b6bdb7467 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2123799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com>