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2023-08-21util/amdfwtool: Add Genoa supportArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I83e3c383faec0fd7b2cf768b7a4c237edd986666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76469 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04util/amdfwtool: Introduce support for Hash Table v2Karthikeyan Ramasubramanian
Some stages in bootflow prefer to use 16 bytes UUID instead of traditional 2 bytes FWID to identify the firmware components they verify/validate. Hence add version 2 of hash table which identifies firmware components using UUID. Other than UUID and a reserved field for alignment reasons, the format of the hash table is very similar to hash table v1. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP Verstage enabled. Ensure that the hash table v2 is built and installed into BIOS image for the components that are configured in amdfw.cfg file. Ensure that the validation by PSP is successful for all the relevant components during the boot flow. Change-Id: I2899154086cf8e90c3327178157b07ead034b16e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76586 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04util/amdfwtool: Support multiple firmware identifier typesKarthikeyan Ramasubramanian
Currently this tool generates a hash table to verify signed binaries, with a 2 byte FWID as the only kind of identifier. Going forward some binaries are going to adopt 16 byte UUID identifiers and more binaries will follow in the future SoCs. Hence add support for handling multiple firmware identifier types. While at this remove the unused fwid from the PSP FW table. BUG=b:277292697 TEST=Build BIOS image and boot to OS in Myst & Skyrim. Change-Id: I5180dc0fe812b174b1d40fea9f00a85d6ef00f2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-01Revert "util/amdfwtool: Add some PSP entries to both levels"Matt DeVillier
This reverts commit 91f5da477677cc6a7a7d5cdc50f5d2bf71981e44. Commit breaks booting on MDN (and likely others). Boot hangs on: [NOTE ]  MRC: no data in 'RW_MRC_CACHE' Change-Id: Id8042690af2764d6e46fe01287be598091b1a239 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76718 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31util/amdfwtool: Add some PSP entries to both levelsArthur Heymans
Some SoC like Genoa require this. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I01ff792e8016b16f34bc69722469b63cae5a42ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/76468 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-07-24amdfwtool: Add early vga BIOS ID to enumArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ife8c166350030cb89d794ac42834d79ec933f278 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-06-02util/amdfwtool: Add ability to split hash tableKarthikeyan Ramasubramanian
Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-02amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenixFred Reitberger
BUG=285390041 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74971 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02amdfwtool: Add --output-manifest optionGrzegorz Bernacki
Passing this option tells amdfwtool to create a text file, containing the versions of the blobs below: - PSP bootloader (type 0x01), - SMU firmware (type 0x08), - AGESA bootloader 0 (type 0x30), - PSP bootloader AB (type 0x73). Created file can be embedded into CBFS which allows to read the version of blobs at runtime. This way version of blobs used to build the coreboot image can be verified at runtime and also from the binary file. Format of manifest file is following: $ cat build/amdfw_manifest type: 0x01 ver:00.35.00.13 type: 0x08 ver:00.5a.23.a6 type: 0x30 ver:2a.14.b0.10 type: 0x73 ver:00.35.00.13 BUG=b:224780134 TEST=Tested on Skyrim device Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-24amdfwtool: Set the minimum size of entry PSPL2 A/BZheng Bao
This is a PSP FW requirement. This is only for recovery A/B without ISH header. That means only Cezanne. Change-Id: I62616d5a866f66fc71e6c0b31a23c62dc11cf3c6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-08util/amdfwtool: Consolidate entry line regex patternKarthikeyan Ramasubramanian
There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-04-28amdfwtool: Increase MAX_PSP_ENTRIESFred Reitberger
The MAX_PSP_ENTRIES constant reserves space for the psp directory table entries. This table is aligned to 4K and the next binary is also aligned to 4K. The number of psp directory entries on Birman exceeds the previous limit, so increase it to the maximum that will fit in a 4K block. TEST=timeless builds for Birman unchanged Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I297edc9cccffde0ad1ce7461b375542f9f2f7c23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-24amdfwtool: Clean up table buffers before combo loopZheng Bao
Keep clean copies of PSP and BIOS table. Refresh the working tables before they are filled with file names and other information at each iteration. Change-Id: Ie8339a4d66c38e02180cbf99e13914bfff66dc0f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Add missing help information for --combo-config1Zheng Bao
Change-Id: I6b69965991daadaf8b4148b06d0715b087021c9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Call wrapper funtion to write fileZheng Bao
Don't call system call directly. Change-Id: I6da31723bc2bfc1197fc31962053671c84ccc397 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-24amdfwtool: Move some funtions to other categorized source filesZheng Bao
To reduce the size of amdfwtool.c which is already too big. Change-Id: Ib80eeb42f59a3dda04402b2feaadc1d178ed989e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-21util/amdfwtool: remove unused union from embedded_firmware structFelix Held
Since commit 2f6b7d557d97 ("amdfwtool: Move the filling of table headers into functions"), the combo_psp_directory union element in the embedded_firmware is unused and the new_psp_directory element is used in all places, so replace the union of new_psp_directory and combo_psp_directory with just the new_psp_directory struct element. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35d339b3084ec8f93210095c233f5e68296d0013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-16amdfwtool: Print which combo entry is being processedZheng Bao
Change-Id: I9e83a3ac56d5c42d8d6839cc4d961adf0b656fb5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73725 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16amdfwtool: Remove meaningless double parenthesesZheng Bao
Change-Id: I4a9192c55d63531621dd7bc49f1ead7f58dff893 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73648 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-16amdfwtool: Check combo_index before checking the combo_configZheng Bao
Otherwise Checking combo_config[++combo_index] causes Out-of-Bounds access. Change-Id: I50d466ee98edfb18c01fc7ba43e929640b33c7c1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73647 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-16amdfwtool: Add asserting before accessing array combo_configZheng Bao
Change-Id: Ia98fdbee4c4005562662313ebe2478d0aeb879bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73724 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-15util/amdfwtool: Update config parser to accept full pathsMartin Roth
This allows individual components to be placed in a location other than what is specified by the FIRMWARE_LOCATION line. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a83e52d081a5909d54eacc575dd2b40b09e4038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-15util/amdfwtool: Support not passing recovery/backup APCBKarthikeyan Ramasubramanian
If Recovery/Backup APCB is not passed, then AMD_BIOS_APCB_BK entry is not populated. But PSP expects that bios directory entry to be populated. Also on mainboards where both APCB and recovery APCB are same (eg. Skyrim), 2 copies of the same APCB are added to amdfw*.rom. Update amdfwtool to support not passing recovery/backup APCB. If the recovery APCB is not passed, then populate AMD_BIOS_APCB_BK entry and make it point to the same offset as AMD_BIOS_APCB entry. BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Ensure that the device can enter recovery mode. Perform multiple suspend/resume cycles. Change-Id: I031ba817573cd35160f5e219b1b373ddce69aa6b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73661 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15amdfwtool: Remove the initial alignment on newer SoCsKarthikeyan Ramasubramanian
On newer SoCs the initial alignment is not required. So skip initial alignment. This saves 64 KiB flash space on each firmware slots. This also saves ~5 ms while loading amdfw.rom BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Change-Id: I27cbfde2d7d58b62a4c0039c60babc3fb3bd95fa Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73654 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10amdfwtool: Remove the option --list which nobody usesZheng Bao
It was used for printing the dependencies which is now taken by macro DEP_FILES in soc/amd/common/Makefile.inc. TEST=binary identical test on google/guybrush amd/chausie Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10amdfwtool: Move PSP FWs padding into a loop for comboZheng Bao
Move main body of PSP padding into a loop which can add a new combo entry. In the loop, get the FW files from each fw.cfg, create new pack of PSP, and fill the combo header. Currently Feature COMBO is still not fully functional. But the non-combo case will not be affected for sure. The real changes are 1. Add a do-while loop. 2. Remove a "TODO" comment. All other changes are re-indenting and re-filling. Change-Id: I351192a4bc5ed9ec0bfa3f2073c9633b8b44246d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58554 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10amdfwtool: Add combo index and combo config tableZheng Bao
For now, combo index is 0, and only the first entry in config table is used. The index will grow when there are more combo entries. Add a command parameter to give fw.cfg for combo index 1. Process the combo config in the future loop. Change-Id: I00609d91defc08e17f937ac8339575f84b1bd37c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10amdfwtool: Add a wrapper function to open and process config fileZheng Bao
And move the additional processing to this new function. Change-Id: Id101d63e4d30a6e57ac1aa79665a4ba22b2956f1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73509 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09util/amdfwtool: Add option to indicate uncompressed BIOS binaryKarthikeyan Ramasubramanian
amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS directory entry) is always compressed. On boards using vboot, sometimes PSP BIOS binary is uncompressed - specifically when CBFS verification is enabled and verified boot starts in bootblock. Add an option to indicate PSP BIOS binary is uncompressed. BUG=b:261792282 TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled. Boot to OS. Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-09amdfwtool: move FW_MPIO to PSP Dir Level 2 where it belongsNikolai Vyssotski
Type 0x5d (MPIO Firmware) was mistakenly placed to PSP Level 1 directory. It should be in Level 2 PSP directory instead. Change-Id: Ic5ea00859f1055e0c91600c5f941c5d3acca36e2 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09amdfwtool: Support multiple inst entriesFred Reitberger
Use the inst field when adding entries to the psp tables. Otherwise, entries that differ by the inst field will appear as duplicates with an inst of 0. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4a84a0730976f4c65902b5c24ed13e21e95b03bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-08amdfwtool: combo: Add combo feature for BIOS tableZheng Bao
It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08amdfwtool: Separate two cases of combo and non-combo clearlyZheng Bao
If combo is used, fill the EFS header with address of COMBO header. If not, fill with address of PSP header. The old code fills with PSP headers all the time. Change-Id: I0057165aea553d9dc8e4e719e2804557229a0002 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66855 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08amdfwtool: combo: Create the combo header earlierZheng Bao
There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08amdfwtool: Move the filling of table headers into functionsZheng Bao
It is easier to understand what these statements are about. Change-Id: Ib02c68c9f2ea84020b12682c41fb1a6f8f93d725 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66852 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02amdfwtool: Remove the limit of spliting EFS and bodyZheng Bao
To support 32M flash, the non-vboot also need to split amdfw. Just as the deleted comment says, we need this feature now. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-02amdfwtool: Change .rom.efs to .rom and .rom to .rom.bodyZheng Bao
To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-01amdfwtool:combo: Move the filling of field "lookup" into functionZheng Bao
This filling does not need to be done separately. Change-Id: I53051349923dce40f4fc3f747ab41a93a3798823 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-01amdfwtool: Remove the hints of flag --combo-capableZheng Bao
A few references to "--combo-capable" were left after commit 4bfb36ed68154d8ee6fc77a6b2bf79938cae9e8a Change-Id: I6f425db2a8b86d7ad928baee6bc7b07e5190ba37 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73281 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-01amdfwtool: Clean up the logic sequence of pointer growingZheng Bao
When the EFS data is being packed, the pointer should be at EFS header. After that, it should be at body location. TEST=binary identical test on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: Ia81e2bdf9feb02971723f39e7f223b5055807cd8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-28amdfwtool: Check the validation of EFS & body relative addressZheng Bao
We need to considering the case the EFS header is given as a relative address and the other, body location, is given as an absolute one. So we convert both of them to relative and check the validation. For relative address case, the location should be between 0 and data size. Change-Id: I7898bfbca02f5eb1c0fb7c456dc1935bddf685b1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-28amdfwtool: Fill the address in EFS header as "relative to BIOS"Zheng Bao
If ctx.address_mode is "physical", it will keep as "physical". If ctx.address_mode is "relative to table", it will be changed as "relative to BIOS". Because the "current table" is the whole flash, the code worked well. TEST=Binary identical test on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I9acb54cc5de149d8a705bb05bf351c44b7d3ced1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-27amdfwtool: Add universal cleanup functionZheng Bao
Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24amdfwtool: Add missing parentheses in macro definitionZheng Bao
Change-Id: I1b43dbb8cdc748960f25d7b0629aa81528a2a476 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24amdfwtool: Change the growing pointer with cautionsZheng Bao
Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-24amdfwtool: Remove the useless variable "rom"Zheng Bao
Now we use ctx.rom. Remove the wrong statement releasing null pointer. Change-Id: I134335ed741dc067e232621106f2057e50ba6a1a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-14amdfwtool: use SoC ID info instead of misleading comboable flagZheng Bao
Since it actually depends on the SoC type whether the old PSP directory table pointer or the new comboable PSP directory table pointer is used in EFS, get this information from the SoC ID instead of passing the comboable flag for the SoCs that need to use the new comboable PSP directory table pointer. TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-13amdfwtool: Remove command line option soc-nameZheng Bao
5/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Iba2ebd5d0310538e04c07493d28039509ad02321 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-11amdfwtool: Put soc name setting to fw.cfg from command lineZheng Bao
The fw.cfg should combine the SOC name. This is for future combo feature. Each entry in combo has its own fw.cfg. The soc_id in struct cb_config can only be available after the fw.cfg is processed. Some functions which take soc_id as a parameter can be simplified. 3/5 (and the key one with same change ID) of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-10amdfwtool: Move soc_id to cb_configZheng Bao
Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09util/amdfwtool: Add UMSMU blob supportFred Reitberger
Add PSP blob Type 0xA2 uMsmu support. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib38ec03bf20f46774f7438b21d18704cc1ec57fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-09amdfwtool: Parse the line with SOC_NAMEZheng Bao
We need to put soc name to fw.cfg for future combo feature. We skip for now when SOC_NAME is found. 1/5 of split changes https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: I2b8d7154d22db13675ff57b6abe61c747604c524 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09amdfwtool: Add SOC family definition for CarrizoZheng Bao
For Carrizo, the soc name was set as UNKNOWN. The change is supposed to be binary unmodified, except the SPI settings. According to the spec, the Stoneyridge and Carrizo have the same definition of SPI setting in EFS. Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09amdfwtool: Allow the location to be a relative addressZheng Bao
When the BIOS size is more than 32M, the physical address of EFS header will be complicated, like 0xfe020000 or 0xfc020000. So we make it simpler to allow to use relative address. This CL works with https://review.coreboot.org/c/coreboot/+/69852 TEST=Result image is binary same on amd/birman amd/majolica amd/gardina amd/mandolin Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08amdfwtool: Report the address of EFS header and bodyZheng Bao
The address mode is an internal mode which AMD FWs use. Regular developers don't have to know that. Just report the relative address every time. For the cases head and body are split, the address of body is also reported. Change-Id: I77d9aac0b3d996363341c1d2dae049ec344b39aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-06amdfwtool: Add phoenix and glinda in get_psp_fw_typeZheng Bao
Change-Id: If80cc5396703cef41cc615008c9f0dac0b7bbb09 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-02-05amdfwtool: Remove useless printing outZheng Bao
Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72724 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-05amdfwtool: Add a function to make the calling stack less deepZheng Bao
And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04util/amdfwtool: add comment about reused PSP firmware type 0x5fFelix Held
On family 15h and 16h processors with PSP, the PSP firmware type 0x5f corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to clarify this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04amdfwtool: Add entry RIB whose subprog equals 1Zheng Bao
For the PHX, it uses subprog 0. For the PHX2, it uses subprog 1. Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-02amdfwtool: Set the level of RIB file as level 2Zheng Bao
It is about AB recovery layout which only has level 2. Change-Id: I836f11ca0bf5ad37e5093419465244a5c83318cb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-01amdfwtool: Remove the duplicated entry RIBZheng Bao
It should be PSP_RIB_FILE which is already there. Change-Id: Ie7471489bd34554e357510b04473102d002f9988 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72506 Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-27amdfwtool: Update and extend PSP header format descriptionZheng Bao
The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-25amdfwtool: Remove comment "fallthrough"Zheng Bao
Fix the comment as "checkpatch" says. Change-Id: Ifa5d7de037aa7024779f3aa4a5d2f5033eed264a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71648 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-22amdfwtool: Change the variable name to body_locationZheng Bao
The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-22amdfwtool: Add instance = 0 for bios imageZheng Bao
For future BIOS image entry whose instance = 1. Change-Id: Iaa40872b270cf9ff289794c8c51c4d8b448d862d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-22amdfwtool: Add missing code for checking new family phoenix & glindaZheng Bao
Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22amdfwtool: Add entry types required to support glinda & phoenix SOCZheng Bao
Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24util/amdfwtool: Write EFS and AMDFW body in separate filesKarthikeyan Ramasubramanian
Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12amdfwtool: Add definition of instance for PSP entryZheng Bao
Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12util/amdfwtool/amdfwtool: Don't rewrite macrosElyes Haouas
Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-11util/amdfwtool: Add more instances some types in BDTArthur Heymans
Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11util/amdfwtool: Add new typesArthur Heymans
These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-26util/amdfwtool: Add build rules for amdfwreadKarthikeyan Ramasubramanian
Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: List AMDFW RO binary entriesKarthikeyan Ramasubramanian
Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories and list the entries present in them. Accommodate both recovery A/B layout and normal layout. This is required to identify the location and size of each entries in the finally built amdfw.rom. This in turn can be used to perform any platform specific verification on the relevant components. BUG=None TEST=Build and list the contents of AMDFW binary. /usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin Table: FW Offset Size PSPL1: Dir 0x00d97000 +-->PSPL1: 0x48 0x00d98000 0x00001000 +-->PSPL2: Dir 0x00c30000 +-->PSPL2: 0x00 0x00c31000 0x00000440 +-->PSPL2: 0x01 0x00c31500 0x00007580 +-->PSPL2: 0x02 0x00c38b00 0x00019470 +-->PSPL2: 0x08 0x00c52000 0x0001f560 +-->PSPL2: 0x09 0x00c71600 0x00000440 +-->PSPL2: 0x0b 0x430000041(Soft-fuse) +-->PSPL2: 0x0c 0x00c71b00 0x00023100 +-->PSPL2: 0x12 0x00c94c00 0x00015890 +-->PSPL2: 0x13 0x00caa500 0x000021c0 +-->PSPL2: 0x20 0x00cac700 0x00000640 +-->PSPL2: 0x21 0x00cace00 0x00000030 +-->PSPL2: 0x22 0x00cad000 0x00001000 +-->PSPL2: 0x24 0x00cae000 0x00003b60 +-->PSPL2: 0x28 0x00cb1c00 0x00022890 +-->PSPL2: 0x2d 0x00cd4500 0x00003100 +-->PSPL2: 0x30 0x00cd7600 0x0006b550 +-->PSPL2: 0x3a 0x00d42c00 0x000006d0 +-->PSPL2: 0x3c 0x00d43300 0x000018c0 +-->PSPL2: 0x44 0x00d44c00 0x00006610 +-->PSPL2: 0x45 0x00d4b300 0x00001c70 +-->PSPL2: 0x50 0x00d4d000 0x00001a00 +-->PSPL2: 0x51 0x00d4ea00 0x00001020 +-->PSPL2: 0x52 0x00d4fb00 0x00010180 +-->PSPL2: 0x55 0x00d5fd00 0x00000600 +-->PSPL2: 0x5a 0x00d60300 0x00000570 +-->PSPL2: 0x5c 0x00d60900 0x00000b20 +-->PSPL2: 0x71 0x00d61500 0x00024710 +-->PSPL2: 0x73 0x00d85d00 0x00010640 +-->PSPL2: 0x8d 0x00d96400 0x00000030 +-->PSPL2: 0x49 0x00d99000 0x00001000 +-->BIOSL2: Dir 0x00d99000 +-->BIOSL2: 0x60 0x00d9a000 0x00009924 +-->BIOSL2: 0x68 0x00da4000 0x00009924 +-->BIOSL2: 0x61 0x2001000(DRAM-Address) +-->BIOSL2: 0x62 0x00dada00 0x00010000 +-->BIOSL2: 0x63 0x00000000 0x0001e000 +-->BIOSL2: 0x64 0x00db4200 0x00006310 +-->BIOSL2: 0x65 0x00dba600 0x000004e0 +-->BIOSL2: 0x64 0x00dbab00 0x00006180 +-->BIOSL2: 0x65 0x00dc0d00 0x00000250 +-->BIOSL2: 0x6b 0x201f000(DRAM-Address) +-->PSPL1: 0x4a 0x00d98000 0x00001000 Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Handle recovery A/B layoutKarthikeyan Ramasubramanian
Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to handle it. Also add a generic read_header function to read different header types. BUG=None TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to dump the Softfuse entry. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit maskKarthikeyan Ramasubramanian
Optional arguments that involve printing information from the firmware image is mapped to bit fields with bit 31 set. But instead of just setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26util/amdfwtool/amdfwread: Update relative_offset functionKarthikeyan Ramasubramanian
* AMD_ADDR_PHYSICAL refers to physical address in the memory map * AMD_ADDR_REL_BIOS is relative to the start of the BIOS image * AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS tables Update the relative_offset implementation accordingly. Though AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify the relative_offset implementation so that it can be used for both PSP and BIOS firmware tables. Hence update the relative_offset function signature as well. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-21util/amdfwutil: Fix adding microcode binariesArthur Heymans
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-11util/amdfwread: Fix cookie error messageArthur Heymans
Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-11util/amdfwutil: Order enum and use hex consistentlyArthur Heymans
This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-10-10util/amdfwtool: Add Mendocino to usageFred Reitberger
Add missing Mendocino soc to usage print. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10util/amdfwtool: Add preliminary code for morgana & glinda SOCsMartin Roth
This allows amdfwtool to recognize the names for the upcoming morgana and glinda SoCs. It does not yet do anything for those SoCs, but this allows the morgana SoC to build. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Generate hashes for signed AMDFW componentsKangheui Won
Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Add options to separate signed firmwaresKangheui Won
Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02util/amdfwtool: Include the header with __packed definitionKarthikeyan Ramasubramanian
Checkpatch script recommends to use __packed instead of __attribute__((packed)). Currently the build rule for amdfwtool does not include the required header file with __packed definition. Update the compiler flag to include the required header file. BUG=None TEST=Build amdfwtool. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30util/amdfwtool/data_parse: fix PMU subprogram/instance ID handlingFelix Held
The parsing of the PMU binary subprogram and instance numbers only worked correctly for the cases where the ID in the name in the fw.cfg file was between 0 and 9, but returned wrong results if it was between a and f. Switch to using strtol with a base of 16 instead of subtracting the char '0' from the char in the filename in find_register_fw_filename_bios_dir to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-22util/amdfwtool: Add support for PSP NVRAM base addr and sizeRitul Guru
Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04util/amdfwtool/amdfwread: Fix incorrect option indexKarthikeyan Ramasubramanian
index I/O argument to getopt_long is not the index to argv. Instead it is an index into the optlong array corresponding to the parsed option. Also getopt() uses a global variable optind to track the index of the next argument to be processed. Use the optindex variable as an index to extract the filename from argv. BUG=None TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush BIOS image. Observed no changes before and after the changes. Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29amdfwtool: Fix indentationZheng Bao
Change-Id: I4c57c9bade318d54315f9692cd37edb694e33aa9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26util/amdfwtool: Add changes to reserve BIOS SIGRitul Guru
changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-12amdfwtool/amdfwtool.h: Allow 16 additional PSP entries to be supportedAltamshali Hirani
Consolidate MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com> Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62911 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-11util/amdfwtool: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used. Update amdfwtool for consistency with the correct naming convention. BUG=b:239072117 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I673a9b99d207603b605756fc7d277c54c5d0f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66467 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-09util/amdfwtool: Fix ISH_B directory offsetKarthikeyan Ramasubramanian
On boards which use both PSP recovery A/B layout as well as VBOOT A/B layout, ISH_B directory entry is pointing directly to PSP Level2 directory. This is not correct and either ISH_B should be marked as not present or it should point to the ISH_A directory itself which in turn point to PSP L2 directory. Fix it by choosing the latter option. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-01util/amdfwtool: Support PSP whitelist file on recovery A/B layoutKarthikeyan Ramasubramanian
This is required to enable PSP verstage on SoCs with recovery A/B layout. BUG=b:217414563 TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2 directory. Build and boot to OS in Skyrim with both PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-26util/amdfwtool: Update the location of PSP verstage and signing keyKarthikeyan Ramasubramanian
On SoCs which use A/B recovery layout, PSP verstage and signing keys are expected to be present only in PSP L2 directory. Update amdfwtool to include the PSP verstage and signing key only in PSP L2 directory. BUG=b:239519603, b:238938623 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-30util/amdfwtool: Initalize all variables before useFred Reitberger
Not all of the fields of the amd_cb_config structure were properly initialized. Rather than initialize each field individually, initialize the entire structure to 0. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-05-13util/amdfwtool: Add amdfwread utilityRobert Zieba
Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>