summaryrefslogtreecommitdiff
path: root/util/amdfwtool/amdfwtool.c
AgeCommit message (Collapse)Author
2020-03-27amdfwtool: Allow for up to 16 APCB entriesRob Barnes
Increase the number of allowed APCB entries in amdfwtool. BUG=b:150455865 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238 Reviewed-on: https://chromium-review.googlesource.com/2084944 Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17util/amdfwtool: Fix file open error msgEric Peers
Print out the name of the file that failed to open. BUG=none TEST=rerun build-board.sh with missing files BRANCH=none Signed-off-by: Eric Peers <epeers@google.com> Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb Reviewed-on: https://chromium-review.googlesource.com/2090667 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-02util/amdfwtool: Clarify APOB NV requirementsMarshall Dawson
Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-18util/amdfwtool: Improve comment's grammarPatrick Georgi
Change-Id: I2daa57c1982346e48dbd91a94864baf2f11c2129 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17util: Fix typosElyes HAOUAS
Change-Id: Ia405384211aa53ac089a99ecd31acc25effdb71e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-20util/amdfwtool: guard typedef aliasesIdwer Vollering
Build tested on Ubuntu 18 LTS, FreeBSD. Change-Id: Ida2c1f36aba7469d69dbb12ee6afce4a181bd6b7 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-06util/amdfwtool: Add instances for APCB backupMarshall Dawson
Match each of the possible APCB items with a corresponding backup APCB. A missing backup copy can prevent the system from booting. Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20util/amdfwtool: Add holding locations for more APCBsMarshall Dawson
Increase the number of potential APCB images to 5 by adding to the amd_bios_table. New instance IDs are from 0 to 4. The backup APCB block (type 0x68) still supports only instance ID 0. Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-16util/amdfwtool: Grow the Embedded Firmware StructureMarshall Dawson
Ensure adequate space exists for all Embedded Firmware Structure fields. Field definitions are NDA only. See PID #55758 "AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors". BUG=b:141790457 TEST=run on Mandolin Change-Id: I098ffc7c05d27387a877e6b7c8628d98939bd9af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35667 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29util/amdfwtool: Correct fletcher32 algorithmMarshall Dawson
Change the fletcher32 checksum calculation to match PSP and AGESA implementations. The symptom of the failure has only been noted in Picasso's BIOS Directory Table, when a BIOS binary image of different sizes were passed to amdfwtool. The PSP halts the boot process with the bad BDT checksum, and if allowed to continue, AGESA asserts later due to a failed BDT verification. This version has been verified to produce the same result as found at https://en.wikipedia.org/wiki/Fletcher%27s_checksum. TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom is unchanged. Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-15util/amdfwtool: Add option to build verstage binary into the PSPMartin Roth
For AMD's Family17h processors, verstage needs to be run in the PSP, before memory is initialized. This adds that binary into the PSP directory. See the Family17h documentation in the coreboot documentation directory for more information. BUG=b:137338769 TEST=Build, add test binary to mandolin board, boot Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15util/amdfwtool: Do misc cleanupMartin Roth
- Correct command line argument for microcode patches from -u to -O - Add #if PSP_COMBO around new_combo_dir() as it's only called when that's enabled. - Remove unused variable in integrate_bios_firmwares() - Correct enum type from amd_fw_type to amd_bios_type in register_fw_addr() Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-10util/amdfwtool: Close file descriptor on errorJacob Garber
Prevents a resource leak. Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-19util/amdfwtool: Update for Family 17hMarshall Dawson
Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Add multilevel PSP directory tableMarshall Dawson
Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Align PSP NVRAMMarshall Dawson
Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Add argument for soft fuse overrideMarshall Dawson
Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-15util/amdfwtool: Allow 0-length blobsMarshall Dawson
A side effect of the change 8e0dca05 "util/amdfwtool: Add generic image copy function" was to treat a read operation of zero bytes as a failure. Some implementations exist that use zero length files as a means of removing functionality. This causes amdfwtool to exit with an error. Put the zero length capability back in, and generate the requested table entry with a length field of 0x0. TEST=Boot google/grunt, inspect PSP directory table BUG=b:128507639 Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Remove fanless SMU optionsMarshall Dawson
Complete the removal of the fanless command line options. The only soc using them has been converted to use the subprogram option instead. TEST=Verify amdfw.rom is unchanged before and after the conversion BUG=b:126691068 Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Split type field for PSP entriesMarshall Dawson
Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Streamline functions with contextMarshall Dawson
Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Add generic image copy functionMarshall Dawson
Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Combine table header populationMarshall Dawson
Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Remove duplicate PSP2 supportMarshall Dawson
There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Introduce combo-capable optionMarshall Dawson
There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 1 of 2 to reduce the number of command-line options to amdfwtool. Create a new option that is used as an indicator for which Embedded Firmware offset to use. Part 2 will be added once makefiles no longer use the duplicated options. This patch also adds two new options for fanless SMU firmware to be used instead of the ones that will be removed in part 2. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied BUG=b:126691068 Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Clarify call to fletcher32Marshall Dawson
The fletcher32 algorithm generates a sum over a range of 16-bit WORDs. Change the function's interface to be more generic, accepting a more intuitive size in BYTEs. Don't require the caller to understand the nature of the algorithm and convert to WORDs prior to calling. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Clarify calculations with structuresMarshall Dawson
Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Fix iteration of PSP firmwaresMarshall Dawson
Correct an oversight in the utility that attempts to match up eligible PSP directory table entries with blob names passed on the command line. A 1:1 matchup of items shouldn't be assumed, so the i iterator shouldn't be used to walk both lists. This change has no effect on google/grunt (Family 15h Models 70h-7Fh), but eliminates blank entries of all FF's on builds of amd/bettong (F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries also affects the checksum accordingly. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22util/amdfwtool/amdfwtool.c: Check fstat returnRichard Spiegel
Funtion fstat will return -1 if there's any error, 0 if successful. Check that fstat return is equal to 0, print error message and exit if not 0. This fixes CIDs 1353018 and 1353020 BUG=b:72062481 TEST=Build no errors Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24util/amdfwtool/amdfwtool.c: Verify it actually read bytesRichard Spiegel
The function read() returns the number of bytes actually read. Program is assuming it actually read the required number of bytes without checking. This is wrong. This fixes CIDs 1353019 and 1353021 BUG=b:72062481 TEST=Build no errors Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23util/amdfwtool/amdfwtool.c: Check for negative returnRichard Spiegel
File open function <open()> will return -1 if there's any error. Check that the return is greater or equal to 0 before using fstat(). Print error message and exit if there's an error. This fixes CIDs 1353018, 1353020, 1353027 and 1353028 BUG=b:72062481 TEST=Build no errors Change-Id: I77d6973d1ad1eadb93922866e618038045be5937 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05util/amdfwtool: Add option for directory locationMartin Roth
The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-27amdfwtool: Move normal firmware 2 after fanless firmware2sMarc Jones
Move the images around in the image stitching. This addresses an issue found with PSP firmware loading on the Google Kahlee mainboard. Note firmware1 must come before firmware2 in the image or the PSP will not allow APU to execute. Change-Id: I85963fa93d6efd707cedfbc04b92d302ad5de3b1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-28util/amdfwtool: Add fanless SMU firmware optionsMarshall Dawson
The Stoney Ridge program has OPNs that are considered fanless. These APUs are strapped to search for unique SMU firmware, indicated by Type[8]=1 in the directory table entry. Add new options to amdfwtool and include the blobs in the build with the appropriate bit set in the Type encoding. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da) Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18991 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-21util/amdfwtool: Wrap long lines, excluding commentsMartin Roth
Change-Id: I35c4340cf14ca1609ce3bfcac78cc4e286eff34a Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17326 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-21util/amdfwtool: Fix whitespaceMartin Roth
Change-Id: I33e41b745e7ec55ed39d7125fc74b1619d28bb54 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17325 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10util/amdfwtool: unify return values, verify the file openMartin Roth
- Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10util/amdfwtool: add usage textMartin Roth
Change-Id: I0ddb4516c03b0240d9134b35753ad901932d3f53 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17323 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10util/amdfwtool: fix clang warningsMartin Roth
Various fixes for clang warnings: warning: arithmetic on a pointer to void is a GNU extension - change *rom from void* to char* and cast back to void* as needed warning: implicit conversion changes signedness - In ALIGN macro, pass in value as unsigned warning: no previous prototype for function - Change functions to static warning: no previous extern declaration for non-static variable - Change global variables to static warning: comparison of integers of different signs - Make loop variable 'i' unsigned warning: variable 'output' may be uninitialized - Make sure an output filename was specified warning: implicit conversion loses integer precision - cast fd_stat.st_size to the appropriate type Change-Id: I0134a79c00938e121e63b52fd63bd502f4cb9e99 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17322 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10util/amdfwtool: Update with ROM size command line parameterMartin Roth
Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-02util/amdfwtool: Increase space used for structuresMarc Jones
Double the space for psp2dir to 0x200. Based on advice from AMD, increase the region containing the signature to 4K. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639) Change-Id: If60132f913928bab0c2fe4aacedf342080929599 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17148 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02util/amdfwtool: Add PSP2 options to optstringMarc Jones
Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de) Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17147 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-11-02util/amdfwtool: Fix duplicate long option nameMarshall Dawson
Make the PSP2 smufirmware2 name unique so the command-line option gets picked up. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: <marcj303@gmail.com> (cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624) Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17146 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03amdfwtool: Fix some PSP2 issueszbao
1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20amdfwtool: Postpone the usage of PSP combo directoryzbao
If we only need to "combo" two PSP directories into one image, we can put first address in romsig 0x10 and second one in romsig 0x14. If we really need to put three, the 0x14 is the combo directory which points to multiple level-2 PSP directories. I guess that two PSP can also use combo directory, with only one level-2 directory. But nobody seems to do that. Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-20amdfwtool: Fix some fields in PSP level-2 directoryzbao
Change-Id: Ib2da7f2210a823fce7f05824e2a2b73d3c0490e9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08amdfwtool: Fill the first 3 romsig entries as 0zbao
I didn't go back through the development guide for this. But based on test, if the empty entry is filled as 0xFFFFFFFF, instead of 0, the USB3 port can not be used. Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant with the case before the amdfwtool is used. Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12665 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26amdfwtool: Correct the PSP2 directory layoutZheng Bao
PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-19amdfwtool: Add amdfwtool to combine AMD firmwaresZheng Bao
Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 06:30:56 +0000