Age | Commit message (Collapse) | Author |
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All devices work, no irq storms. Enjoy.
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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becomes meaningful. The linker puts help texts on stderr.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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./s2912_fam10/Options.lb:default FALLBACK_SIZE=ROM_SIZE-0x01000
Please, someone with the board test this and fix it accordingly.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Thanks Arne. Good job.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This works fine in Linux if you use the 'irqpoll' kernel command
line option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This also contains various improvements of the CN700 code in svn.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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buildrom and this bit was forgotten during r3092.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The FAM10 code takes up more space in the uncompressed "ROMCC" portion
of coreboot. Also, It is still growing as features are added.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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is based on amd-lx800/cs5536.
Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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needs 172 more bytes, give it 512 and hope that's enough for a while.
Trivial.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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a bit less awkward (pun intended).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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checking for --build-id, if the user has specified one by setting CC
in the environment; there's no point in checking the native linker in
this case.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Kenji Noguchi <tokyo246@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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mainboard, aka "Mt. Arvon".
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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properly. Everybody knows this by now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(Thus the patch is trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The problem is explained here: http://www.coreboot.org/pipermail/coreboot/2008-March/032185.html
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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tyan s2881 board, in preparation of supporting it in buildrom. Corresponding
changes for the other buildrom-supported boards were committed in r3092.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Tested on real hardware.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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breaks buildrom.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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them to coreboot.rom
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The patch was followed by these svn commands:
svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force src/mainboard/emulation/qemu-i386/
src/mainboard/emulation/qemu-x86
svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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architectures supported by buildrom.
Myles
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I think that since the directory specifies the architecture and the
board, it is redundant information to name it something else, and it
makes it more difficult to automate the build process (buildrom).
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Tested on actual hardware by Sergei Antonov <saproj@gmail.com>.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Sergei Antonov <saproj@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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(unlike 5 lines later where make syntax is emitted into a file)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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That fixes a compilation failure.
Signed-off-by: Marc Karasek <marc.karasek@sun.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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image. Even if the rom image size is not changed, it can make the linking fail.
It's almost a heisen-bug, only there if you don't watch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the impression that the cheetah on fam10 is broken just because we're using a
too new compiler for abuild. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It's easier to tell users "copy your payload to /tmp/filo.elf" than have
them guess paths or modify Config.lb files etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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using the default from src/mainboard/*/Options.lb (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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It never worked in v2 (the v1 port did work AFAIK, though), and it's
not really useful as reference for other boards anymore (as we now
have a dozen or so 440BX boards which work in v2).
This is a specialized, custom board (not sold on the "public market"),
so it's probably not useful for pretty much everyone out there anyway.
We can easily re-add it later (based on one of the other 440BX boards)
should there be interest and/or someone with the hardware to test.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the other supported 440BX boards.
Fix up totally b0rked static device tree in Config.lb.
Drop useless and duplicated failover.c, use global one.
Make CPU init actually work (result: massive speed-up).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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PIRQ table to make most devices work. Random small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Fix IRQ tables (Thanks to Marc Jones)
Fix IRQ SLOT #
Comment out ram test in early startup.
make the debug print in lx/raminit.c a debug print, not emerg print
Set the default console log level to 3, but leave in the possibility of
running with more info (leave maximum at 11)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in
src/include/device/pci_ids.h
4. Trim trailing spaces for all files
Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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of all the other boards in this patch series.
Add missing PIRQ table to make most devices work.
Enable VGA support. Add flashrom flashing protection code.
Make CPU init actually work (result: massive speed-up).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is not yet enough to actually successfully build the board, but
now abuild at least _attempts_ to build it.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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mainboard/ path. Also add a Config.lb for abuild. It's required for the
three images variant as abuild doesnt detect this automatically.
Trivial patch - it does not even fix the build yet. Patches welcome.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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southbridge now:
From: Morgan Tsai <my_tsai@sis.com>
It supports SiS761GX / SiS966 chipset, only for AMD K8 platform so far.
Due to integrated VGA sharing system memory, some code in southbridge
folder have to init northbridge.
Copyright (C) 2007 Morgan Tsai <my_tsai@sis.com>
Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
Change Log:
Newly support GIGABYTE GA-2761GXDK
CPU type: AMD AM2 socket
Northbridge: SiS 761GX
Southbridge: SiS 966
SuperIO: ITE8716F
Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This board uses nearly the same devices as the BCOM Winnet100, so most of
the new code here is from the BCOM Winnet100. They differ in the IRQ routing
table only.
BTW: The AXUS board uses standard DIMM memory and can be run at 100MHz SDRAM
clock speed (it runs reliably here since month).
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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since it is still our most wide-spread codebase.
The patch is pretty trivial, and nobody except Torsten even looked at
it in a week, so....
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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replacing it with a minimal, but working, framework which will be expanded.
Drop a bunch of useless and duplicated files, add missing license headers.
I'm self-acking it this time, the diff is a huge unreadable mess and the old
code is broken anyway...
This code is tested to build fine, and can boot a Linux kernel up to a
login-prompt via FILO (IDE). This is verified on actual hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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See http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial for hardware
description and build tutorials.
Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This is a geode LX board. There are timing settings that are not right
yet, we are still trying to get our board to boot Linux :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Now uses CAR.
New code for SPD-less memory implementation.
Updated IRQ routing.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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southbridges, along with the Asus MEW-VM. With this, my machine attempts to
boot linux, but does so very slowly and fails during the boot process, probably
because of the irq tables.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The DB800 is the AMD LX Reference Design Kit platform.
For details see: http://www.amd.com/geodelxdb800
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Both are very similar, thus both use the JUKI-511P target.
Linux with patches from Juergen Beisert
(http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html)
boots and work fine (ide, usb, ethernet, serial, keyboard and sound
work normally).
Problems:
- Filo loads a bzImage only from ide0 (ide1 doesn't work yet).
- Video doesn't work, yet.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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bigger payloads (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's
available on all boards, regardless of what DIMMs you use.
Tested on the Tyan S1846, works fine.
- Properly set the PAM registers to allow the region from 768 KB - 1 MB
to be used as normal RAM (required for the above).
- Document all of this properly. Add/improve other documentation, too.
- Simplify and document code in northbridge.c.
- Cosmetics and coding style.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used
for timer calibration, which takes about one second.
All EPIA-M boards have timer2 so we use it to boot faster.
Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO
calibration but add the TSC options so that they can be set in Config.lb.
src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we
set HAVE_HARD_RESET=0 for both boards.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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