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2020-12-11soc/amd/picasso: Add data fabric read helper functionJason Glenesk
Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/picasso: move chipset_handle_reset to commonFelix Held
The FSP integration code needs this function to be present. It's not supposed to be called, but if it is, it'll print an error and call the SoC's cold reset function. Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11mb/google/volteer: Clean up romstage and ramstage UPDsTim Wawrzynczak
Move the manual calls to fw_config_probe() into the devicetree; the AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are already guarded with probe statements in the baseboard devicetree, so the code in romstage.c was redundant. The variants seem to have their USB4 probe statements correct as well, so the manual UPD setting in mainboard.c was also unnecessary. BUG=none TEST=abuild google/volteer Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11mb/google/volteer: Make use of fw_config_is_provisioned()Tim Wawrzynczak
In cases when a volteer device is unprovisioned, the safest thing to do for GPIOs that will normally be used for audio codec buses is to leave them disabled (configured as PAD_CFG_NC). This patch adds support for that. BUG=none TEST=add debug print to new if branch; remove fw_config from CBI and see print on console Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47972 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11fw_config: Use UNDEFINED_FW_CONFIG to mean unprovisionedTim Wawrzynczak
A mainboard might want to configure some things differently when a device is in an unprovisioned state. In the case when fw_config comes from the Chromium EC, an unprovisioned device will not have a FW_CONFIG tag in its CBI. This patch will set the fw_config value to UNDEFINED_FW_CONFIG in the case of an error retrieving the value, as well as adding a function, `fw_config_is_provisioned()` to indicate the provisioning status. BUG=none TEST=remove fw_config from chromium EC CBI, add code to mainboard to print return value of fw_config_is_provisioned() (`0`), add fw_config back to CBI, run same test and see `1`. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib3046233667e97a5f78961fabacbeb3099b3d442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47956 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/intel/common/block/acpi: Skip UART debug table if not usedMarc Jones
Skip the ACPI UART debug table if common block UART isn't selected. Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48247 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11Kconfig: Show console debug options if loglevel override is setMarc Jones
Show console debug options that would only be available if console SPEW was selected when the override loglevel option is selected. Change-Id: I2fb22562688d6b0bc9235c9ebe5d427dc2a67767 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-11soc/intel/common/block/lpc: Move southbridge_write_acpi_tables declarationMarc Jones
Move the southbridge_write_acpi_tables declaration from acpi.h to common lpc_lib.h, as common LPC is always the caller. This removes a duplicate declaration since all soc/intel devices use common LPC, but not all use common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c with the other acpi functions. Note that this would have the reverse problem if there is ever a non-common LPC device. Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11sb/intel/x/smbus.c: Factor out common codeAngel Pons
Since common smbus.c gets built for romstage as well, create a new file to hold this common code. Account for ICH7 not having a memory BAR, too. Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11sb/intel/bd82x6x: Drop invalid SATA registersAngel Pons
Code was copy-pasted from older chips and has no effect on bd82x6x. Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47099 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11mb/ocp/deltalake: Update GPIO configurations according to schematicsJingle Hsu
On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH (C621A) by util/inteltool and generate the header file by util/intelp2m. The DVT and EVT GPIO configurations are the same. The initial value of GPP_B20 (POST complete) should be high, otherwise BIC would get incorrect sensor readings and see events like PCH prochot. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229 Reviewed-by: Tim Chu <Tim.Chu@quantatw.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11device/Makefile.inc: Do not require hda_verb.cAngel Pons
A mainboard-level hda_verb.c may not exist for variant setups. Change-Id: If2c92d9498cba7c084ef4c7065bc4ae83c7da761 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-11sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm`Angel Pons
There's no need to compare the vendor ID. Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45258 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11Drop many cases of .previous directive useKyösti Mälkki
Since most assembly files are no longer concatenated together but built separately, section changes with .previous at the end of the files have become spurious. TEST=BUILD_TIMELESS Change-Id: I2970eed2b114a53475ba385eec4e97bb7ae7095c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-11mb/google/volteer/variant/lindar: Correct IOM port configurationKevin Chang
Correct IOM setting and TCSS AUX setting to fix type C C0 port display can't output after flip. BUG=b:173093980 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbinFrankChu
In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_tableAlex Levin
BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset bluetooth on reset. BUG=b:171085081 TEST=volteer2 boots; scope shows assertion of the signal Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-12-11soc/amd/picasso: factor out write_resume_eip to common codeFelix Held
Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: move UART console code to common folderFelix Held
Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: move UART Kconfig options to common folderFelix Held
The actual UART initialization code will be factored out in follow-up commits. Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UARTFelix Held
This allows factoring out the common initialization for the integrated UARTs. Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/piasso,cezanne: add warning about using all-y in Makefile.incFelix Held
all-y will also add a compilation unit to the verstage on PSP build that runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't have verstage on PSP support yet, but since it'll eventually land it doesn't hurt to already add the comment now. Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11soc/amd/picasso: use all-y for aoac targetFelix Held
Since aoac gets also linked into verstage on PSP, all-y can be used here. Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48506 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if usedFelix Held
FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in this case. Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48485 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10lib/edid_fill_fb: Support multiple framebuffersPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel and Aspeed on server platforms or Intel and Nvidia on consumer notebooks. The goals are to remove duplicated fill_fb_framebuffer(), to advertise multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Add an implementation in edid_fill_fb that supports registering multiple framebuffers, each with its own configuration. As the current code is only compiled for a single graphics driver there's no change in functionality. Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPMDuncan Laurie
Configure the CFG2 register to set the latency to <64us in order to ensure the L1 exit latency is consistent across devices and that L1 ASPM is always enabled. This moves the setup code from device init to device enable so it executes before coreboot does ASPM configuration, and removes the call to pci_dev_init() as that is just for VGA Option ROMs. BUG=b:173207454 TEST=Verify the device and link capability and control for L1: DevCap: Latency L1 <64us LnkCap: Latency L1 <64us LnkCtl: ASPM L1 Enabled Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10drivers/intel/fsp1_1/cache_as_ram.S: Correct commentFrans Hendriks
Stack is set up for bootblock. Tested on Facebook FBG1701. Change-Id: I0dd3fc91c90bf76e0d93925da35dc197d68d3e88 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47802 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/google/zork: Remove unsused codeMathew King
Remove unused code that appears to be left over from grunt. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48505 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/google/volteer: Fix a few devicetree device refsTim Wawrzynczak
Commit b0e169ac85 included a few small omissions and typos when converting 'device pci xx.y' to 'device ref blah' after adding the new chipset.cb file for TGL. This patch fixes these errors: 1) MIPI camera support requires I2C2 & I2C3 enabled 2) Malefor SAR sensor is on I2C2, not I2C3 BUG=b:175165653 TEST=abuild -p none -t google/volteer -x -a -c max Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-10soc/intel/tigerlake: Check TBT & TCSS ports for wake eventsTim Wawrzynczak
Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes, so add checks for wakes from these devices in pch_log_pme_internal_wake_source. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/common: Adapt XHCI elog driver for reuseTim Wawrzynczak
Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS or North XHCI block has a similar enough PCI MMIO structure to make this code mostly reusable. 1) Rename everything to drop the `pch_` prefix 2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI controller 3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI controller BUG=b:172279037 TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via EC; type on keyboard, verify it wakes up, eventlog contains: 39 | 2020-12-10 09:40:21 | S0ix Enter 40 | 2020-12-10 09:40:42 | S0ix Exit 41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1 42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109 which verifies it still functions for the PCH XHCI controller Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/intel/xeon_sp/nvs: Use common global NVSMarc Jones
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there isn't anything uncommon with the soc NVS, use the Intel common NVS. This covers the NVS cases of common code used by xeon_sp. Update the mainboards for this change. Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-10sb/intel/bd82x6x: Make me_common.c a compilation unitAngel Pons
We need to make most things non-static so that the code builds. Also, we need to update ibexpeak as well, because it borrows files from bd82x6x. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42019 Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.hFelix Held
The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10sb/intel/x/smbus.c: Add block read/write supportAngel Pons
Copy and paste the i82801gx code onto all newer southbridges. This will be factored out into common code in a follow-up. Change-Id: Ic4b7d657865f61703e4310423c565786badf6f40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10sb/intel/x/smbus.c: Rename parameterAngel Pons
This is for consistency among the various southbridges. Change-Id: Id0dcfeef6e220861212ce665201ce8cd31f3b054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10soc/mediatek/mt8192: Init SSPMTingHan.Shen
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. Signed-off-by: TingHan.Shen <tinghan.shen@mediatek.com> Change-Id: Ia834852af50e9e7e1b1222ed1e2be20e43139c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47786 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/mediatek/mt8192: Init DPMHuayang Duan
DPM is a hardware module for DRAM power management and for better power saving in low power mode. BUG=none TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Add EHL CRB memory initialization supportTan, Lean Sheng
Update memory parameters based on memory type supported by Elkhart Lake CRB: 1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Update ehl_crb device treeTan, Lean Sheng
Update Elkhartlake CRB devicetree devices based on EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I88097ced03f4376f309487b9d5207473f77742ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Remove JSL sku id info in SMBIOSTan, Lean Sheng
Remove JSL specific SMBIOS sku id info as it is not required by EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48123 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRBTan, Lean Sheng
THis patch removes IPU & MIPI related support from EHL CRB as they are not supported in EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10mb/intel/ehlcrb: Remove board ID detection via ECTan, Lean Sheng
Since there is no EC support on EHL CRB, this patch removes board ID detection via EC (board_id.c & board_id.h) and its related files. Temporarily removes variant_memcfg_config function in romstage_fsp_param.c, will be added back when updating memory configs later. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I40d96285dc05ec5faabc123950b6b3728299e99a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48121 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Remove ChromeOS EC related headersTan, Lean Sheng
Since EHL CRB does not support ChromeOS, this patch removes ChromeOS EC related headers (ec.h & gpio.h) and #includes. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9c0c3722065c041769081f3d564646ce6a565a9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10mb/intel/ehlcrb: Remove ChromeOS EC support from smihandlerTan, Lean Sheng
Since there is no ChromeOS support for EHL CRB, drop smihandler.c which just deals with ChromeOS support. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Id474c3b04a82c03dda6514cc4565b58fb790b9c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10mb/intel/ehlcrb: Remove ChromeOS support from mainboardTan, Lean Sheng
Since ChromeOS is not officially supported for EHL CRB, removing ChromeOS related codes. Here are the change details: - Remove ChromeOS related kconfig switches, including SOC_INTEL_CSE_LITE_SKU which has dependency on ChromeOS flag - Remove chromeos.c file - Remove ChromeOS dsdt related codes from dsdt.asl & mainboard.c - Remove ChromeOS GPIO related codes from variants.h & gpio.c Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Add missing 'include <console/console.h>'Tan, Lean Sheng
"Die()" needs <console/console.h>, as per this patch: https://review.coreboot.org/c/coreboot/+/45540 Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I0f9fae4a1e43477ca8e78ebbebd8c0729f8b7668 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48116 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Add initial mainboard codeTan, Lean Sheng
This is a initial mainboard code cloned entirely from jasperlake_rvp aimed to serve as base for further mainboard check-ins. This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/37868 List of changes on top off initial jasperlake_rvp clone: 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jslrvp" with "ehlcrb" 4. Remove unwanted SPD file, add empty SPD as placeholder 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config 7. Empty GPIO configurations, to be filled as per board 8. Empty memory.c configurations, to be filled as per board 9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB 10. Replace jslrvp variant with ehlcrb variant Changes to follow on top of this: 1. Add correct memory parameters, add SPDs 2. Clean up devicetree as per tigerlake SOC 3. Add GPIO support 4. Update ehl fmd file to replace 32MB chromeos.fmd Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I2cbe9f12468318680b148739edec5222582e42a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10soc/intel/elkhartlake: Fix EHL mainboard build fail errorsTan, Lean Sheng
When EHL initial mainboard patch is uploaded, there are some build errors caused by EHL soc codes. Here are the fixes: 1. include gpio_op.asl to resolve undefined variables in scs.asl 2. remove unused variables in fsp_params.c 3. rearrage sequences of #includes to fix build dependency of soc/gpio_defs.h in intelblocks/gpio.h 4. add the __weak to mainboard_memory_init_params function 5. add the missing _len as per this patch changes https://review.coreboot.org/c/coreboot/+/45873 Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10cpu/x86/64bit/exit32.inc: Don't invalidate cache in CARPatrick Rudolph
Change-Id: I4a4e988d38b548e1c88ffcc5f5ada2e91ff6ba91 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-10arch/x86/smbios.c: Fix compilation on x86_64Patrick Rudolph
Change-Id: I07780f9a6fa577d7b6bb63884071a7e1ce1bdbfa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-10drivers/crb/tpm: Fix compilation on x86_64Patrick Rudolph
Change-Id: I19cce90f44b54e4eb6dd8517793ae887f0bd1e22 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-10soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPMYidi Lin
MCUPM is the MediaTek proprietary firmware for MCU power management. TEST=1. emerge-asurada coreboot chromeos-bootimage; 2. See following log during booting. load_blob_file: Load mcupm.bin in 35 msecs, size 115668 bytes 3. Test suspend/resume by: a. suspend (on DUT): powerd_dbus_suspend b. resume (on host): dut-control power_state:on Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46392 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/mediatek/mt8192: add spmfw loaderRoger Lu
This patch adds support for loading spm firmware from cbfs to spm sram. Spm needs its own firmware to enable spm suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. BUG=b:159079649 TEST=suspend with command `powerd_dbus_suspend` and wake up the DUT by powerkey Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/mt8183: Use mtk_init_mcu to init SSPMYidi Lin
Use mtk_init_mcu API to load and run sspm firmware. TEST=emerge-kukui coreboot Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/mt8183: Add DRAM_DMA sectionYidi Lin
mtk_init_mcu uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtk_init_mcu. On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer, so it is not necessary to be marked as non-cacheable resource. Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/common: Add common API for loading firmwaresYidi Lin
Add mtk_init_mcu to load the firmware to the specified memory address and run the firmware. This function also measures the load time and the blob size. For example: mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (14004 bytes) Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: enable AER for PCIe root portsMichael Niewöhner
Follow vendor and enable Advanced Error Reporting for PCIe root ports. This enabled the Linux AER driver, which handles PCIe error conditions. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devicesMichael Niewöhner
Add the subsystem ids to PCI ports and devices, which were dumped on vendor firmware using `lspci`. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: enable LTR for all root portsMichael Niewöhner
Follow vendor and enable LTR on all root ports to optimize for devices' latency requirements and also optimize power management while preventing failure due to wrongly guessing idle states, which happens without LTR. Tested successfully. No errors show up in dmesg. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUMEMichael Niewöhner
All X11 boards currently supported have Intel SPS without support for S3/S5. Thus, drop it from Kconfig. Note: not all X11 boards are server boards. When a X11 desktop or workstation board should be added, this can be selected by the boards, where S3/S5 work. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure unconnected padsMichael Niewöhner
Correct unconnected pads that are configured different currently by copying vendor configuration while porting the board. Add internal pull resistors to all unconnected pads, that do not have an external pull resistor, to prevent floating. The pads have been determined by dissecting a dead board. This commit only changes pads, that are not connected at all and don't have any via, so we can be absolutely sure there is no other connection. Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure and document various padsMichael Niewöhner
(Re)configure various pads found by dissecting a dead board and vendor firmware, as well as the BMC firmware: - GPP_B14: input connected to jumper JBR1 - could be used to implement "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up - GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify the BMC about a thermal throttling event. Not implemented in vendor firmware. - GPP_C23: input connected to the CPU's CATERR# output; external pull-up Not actively used by vendor firmware. - GPP_D1: output connected to on-board and front panel power LEDs - GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will be used later in CB:48096 and CB:48097; external pull-up - GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not useful, since the IGD is not connected to any ports on this board. External pulls ensure correct function of a dGPU even without driving the gpios. Not used by vendor firmware. - GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls - GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not used by vendor firmware. Also add comments for documentation. While at it, mark ME-owned pads as reserved. Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-10soc/amd/picasso/reset: use port and bit defines from cf9_reset.hFelix Held
The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/amd/picasso/reset: remove leftover PCI includesFelix Held
On Stoneyridge some PCI registers were accessed in this compilation unit, but on Picasso this is no longer the case. Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/volteer/variant/volta: add Synaptics touchpad.Sheng-Liang Pan
add new Synaptics touchpad for volta. BUG=b:174802144 TEST=emerge-volteer coreboot and check touchpad function work. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd/cezanne: print APU family and model in bootblock_soc_initFelix Held
Change-Id: I457188c905167affc1ebcea835a36df822ecb23c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/cezanne: add basic early FCH initialization to bootblockFelix Held
Change-Id: I1c6d32a5498a7adcee3c8c3145f85e9dba26bf7e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/cezanne: add common SMBus code to buildFelix Held
Since the IOAPIC in the FCH gets set up in the SMBus code, also select IOAPIC in Kconfig. Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09cbfs: Allow mcache to be found after the first lookupJulius Werner
This patch addresses the same problem as CB:48429, but hopefully this time correctly. Since the mcache is not guaranteed to be available on the first CBFS lookup for some special cases, we can no longer treat it as a one-time fire-and-forget initialization. Instead, we test cbd->mcache_size to check if the mcache has been initialized yet, and keep trying on every lookup if we don't find it the first time. Since the mcache is a hard requirement for TOCTOU safety, also make it more clear in Kconfig that configurations known to do CBFS accesses before CBMEM init are incompatbile with that, and make sure we die() rather than do something unsafe if there's a case that Kconfig didn't catch. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I4e01e9a9905f7dcba14eaf05168495201ed5de60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-09Revert "cbfs: Skip mcache in post-RAM stages before CBMEM is online"Julius Werner
This reverts commit b652aaef990cc3eb481dea7f8d4cc3eecd92ffa1. It was dumb and didn't actually fix anything. Change-Id: I074135dd12face1226105e0706c78ae8ecba18e0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-09soc/amd/cezanne: call bootblock_main_with_basetime in bootblock_c_entryFelix Held
Change-Id: Iaac661fcb7581236ace4b5bf057b3e70289f1c8b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/picasso,stoneyridge: drop unused BIOSRAM offset definesFelix Held
The two Socs don't use this functionality and biosram.c in the common code is the only place where those defines are used, but it doesn't include soc/iomap.h and has its own definitions instead. Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104Raul E Rangel
The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x data width, sampled on each clock edge = 104 MiB/s. According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth & clock frequency for various MMC bus speed modes are (at x8 bus width): MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR) MMC_HS: 52 MB/s at 52 MHz SDR MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR) MMC_HS200: 200 MB/s at 200 MHz SDR MMC_HS400: 400 MB/s at 200 MHz DDR BUG=b:159823235 BRANCH=zork TEST=build zork Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd: Remove Kconfig BOOTBLOCK_ADDRKyösti Mälkki
Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR. Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09soc/amd: Remove Kconfig X86_RESET_VECTORKyösti Mälkki
The architectural requirement is for the address to be located at the end of bootblock -0x10 bytes, so the definition was redundant with other Kconfig variables. Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09soc/intel/common/dmi: Add support for locking down SRLSrinidhi N Kaushik
This change adds support to lock down the DMI configuration in dmi_lockdown_cfg() by setting Secure Register Lock (SRL) bit in DMI control register. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/intel/common/dmi: Move DMI defines into DMI driver headerSrinidhi N Kaushik
Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/volteer: Reorganize FMAPFurquan Shaikh
This change reorganizes FMAP for volteer to make use of the lower 16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to RW_LEGACY. This is now possible because TGL supports memory mapping of BIOS region greater than 16MiB. Following changes are made in chromeos.fmd as part of this: 1. Move RW_SECTION_A and RW_MISC to lower 16MiB. 2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as a placeholder in the lower half of the SPI flash. 3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a larger region for ELOG. 4. Increase WP_RO to 8MiB to allow larger space for firmware screens. GBB size is thus increased to 448KiB. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-09soc/intel/tigerlake: Enable support for extended BIOS windowFurquan Shaikh
This change enables support for extended BIOS window by selecting FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW and providing base and size of the extended window in host address space. BUG=b:171534504 Cq-Depend: chromium:2566231 Change-Id: I039155506380310cf867f5f8c5542278be40838a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-12-09mb/google/dedede: Update Boten GPIO setting for PEN detection.Stanley Wu
AP_PEN_DET_ODL isolated by a diode and need to pull up internally. BUG=b:160752604 BRANCH=dedede TEST=Build and confirm waveform by google EE parter. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/zork/var/vilboz: Update telemetry settingsJohn Su
Update telemetry settings. VDD Slope : 32643 -> 26939 VDD Offset: 208 -> 125 SOC Slope : 22742 -> 20001 SOC Offset: -83 -> 168 BUG=b:171668654 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE test report Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48288 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2V Sowmya
This patch adds the PMC MUX and CONx devices for adlrvp for conn2. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpadTim Chen
Add Elan and Synaptics touchpad settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-09mb/google/dedede/var/metaknight: Add audio related settingsTim Chen
Add HDA,speaker codec and speaker amp settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-09soc/amd/picasso/southbridge: drop unused sb_enableFelix Held
Change-Id: I10a16c8f9db994ff33407619a7ab6e453b026b15 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/picasso: split southbridge into bootblock and ramstage codeFelix Held
The ramstage parts gets renamed to fch.c and the bootblock one to early_fch.c. No functionality from the old southbridge file is used in romstage, so don't link it there. Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/cezanne: select common ACPIMMIO blockFelix Held
Change-Id: I7f7d11d84733a43500b0135e565d91fe5c493279 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out functionality to print last reset sourceFelix Held
Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/common/block/acpimmio: use all-y for mmio_util targetFelix Held
Since mmio_util gets also linked into verstage on PSP, all-y can be used here. Change-Id: I03572d760b485938f0d00b6cead00746eda6ca09 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48436 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd: factor out legacy I/O and cf9 decode enable functionsFelix Held
Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmio_util file to have them all in one place. Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd/common/block/smbus: refactor fch_smbus_initFelix Held
Move the setup of the base address to a separate function and explicitly set the SMBUS and ASF I/O port decode even though it is expected to already be set after reset. Change-Id: I8072ab78985021d19b6528100c674ecdd777e62e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out PM_DECODE_EN register definitionsFelix Held
Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: remove unused PM_ISA_CONTROL definitionsFelix Held
ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO code block that actually gets used. Also fix the indentation of the ACPIMMIO register decode defines in the common code. Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd/stoneyridge/southbridge: make sb_disable_4dw_burst staticFelix Held
sb_disable_4dw_burst is only used in the same compilation unit, so no need to make it externally visible. Change-Id: I6c7c96f67b98fb8ed808f45a7685c4d72a10d32c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-08mb/google/deltaur: Restrict RW_DIAG to lower 16MiBFurquan Shaikh
This change restricts RW_DIAG region to lower 16MiB to ensure that the extended BIOS checker for FMAP does not complain about 16MiB boundary crossing. I haven't updated any other regions to occupy the newly freed space but it is fine since this board is dead and should be dropped from coreboot soon. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-08mb/intel/tglrvp: Restrict SI_ME region to lower 16MiBFurquan Shaikh
This change restricts SI_ME region to live below the 16MiB boundary to ensure that no regions cross the 16MiB boundary as the extended BIOS window checker for FMAP complains about it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-08soc/intel/common/fast_spi: Add Lockdown of extended BIOS regionSrinidhi N Kaushik
This change adds support to Lock down the configuration of extended BIOS region. This is done as part of fast_spi_lockdown_cfg() so that it is consistent with the other lockdown. Change includes: 1. New helper function fast_spi_lock_ext_bios_cfg() added that will basically set EXT_BIOS_LOCK. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I730fc12a9c5ca8bb4a1f946cad45944dda8e0518 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/common/fast_spi: Add support for configuring MTRRsSrinidhi N Kaushik
This change enables caching for extended BIOS region. Currently, caching is enabled for the standard BIOS region upto a maximum of 16MiB using fast_spi_cache_bios_region, used the same function to add the support for caching for extended BIOS region as well. Changes include: 1. Add a new helper function fast_spi_cache_ext_bios_window() which calls fast_spi_ext_bios_cache_range() which calls fast_spi_get_ext_bios_window() to get details about the extended BIOS window from the boot media map and checks for allignment and set mtrr. 2. Make a call to fast_spi_cache_ext_bios_region() from fast_spi_cache_bios_region (). 3. Add new helper function fast_spi_cache_ext_bios_postcar() which does caching ext BIOS region in postcar similar to 1. 4. If the extended window is used, then it enables caching for this window similar to how it is done for the standard window. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9711f110a35a167efe3a4c912cf46c63c0812779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47991 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 04:41:00 +0000