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2024-07-03mb/asrock: Add Fatal1ty Z87 Professional (Haswell)Jan Philipp Groß
This port was done via autoport and subsequent manual tweaking. Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM! The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - both RJ-45 Gigabit LAN Ports - USB 2.0 Ports - USB 3.1 Gen1 Ports - both USB 3.1 Gen1 headers - HD Audio Jack (audio output) - all six SATA3 6.0 Gb/s connectors by Intel - all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061 - all three PCI Express 3.0 x16 slots - PCI Express 2.0 x1 slot - half mini-PCI Express slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection via jumper not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots not (yet) working: - Front panel audio connector - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03mb/google/geralt: Replace GERALT_USE_MAX98390 with FW_CONFIG for TAS2563Rui Zhou
Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG, we remove GERALT_USE_MAX98390 from Kconfig. BUG=b:345629159 BRANCH=none TEST=emerge-GERALT coreboot TEST=Verify beep function through deploy in depthcharge successfully. Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-03mb/google/ovis/variants/deku: Add K3KL9L90CM-MGCT to RAM ID tableTony Huang
Add RAM ID for K3KL9L90CM-MGCT 0 (0000) BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=Run part_id_gen tool without any errors Change-Id: Icb84838a6964b9318ded0573ad58a4fd1221867f Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83300 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03mb/google/brox/var/lotso: Tune I2C frequency for 400 kHzJing Tong
Before: I2C0 - 401kHz I2C4 - 405kHz After: I2C0 - 392kHz I2C4 - 395kHz HW: Change R8409/R8411 to 33ohm. BUG=b:349743464,b:349735055 TEST=emerge-brox sys-boot/coreboot Test pass by EE Change-Id: I985837b1b80e973f148529b446905580c0f95e98 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2024-07-03soc/intel/xeon_sp/gnr: Support fast bootGang Chen
Fast boot will used pre-saved hardware configuration data to accelerate the boot process, e.g. DDR training is skipped by using pre-saved training data. Enable fast boot on cold and warm resets by default. Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-03security/vboot: Set VBOOT_ALWAYS_ENABLE_DISPLAY if BMP_LOGOYu-Ping Wu
If BMP_LOGO is set, currently display_init_required() will always return 1, so that platform code will always initialize display. However, that information isn't passed to vboot, which may result in unnecessary extra reboots, for example when the payload needs to request display init (by vb2api_need_reboot_for_display()). Since there is already a Kconfig option VBOOT_ALWAYS_ENABLE_DISPLAY to tell vboot that "display is available on this boot", enable it by default if BMP_LOGO is set. BUG=b:345085042 TEST=none BRANCH=none Change-Id: I20113ec464aa036d0498dedb50f0e82cb677ae93 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-07-03mb/gigabyte/ga-h61m-series: Initial GA-H61M-S2P-R3 bringupPugzAreCute
Working: - Both DIMM slots - All Rear USB 2.0 ports - Integrated graphics (libgfxinit) - Realtek RTL8111F GbE - Flashing internally with flashrom (Note: Works from stock too due to Gigabyte not following Intel recommendations, confusing ME) - SeaBIOS (1.16.3) to boot Arch Linux Installer - EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer - Audio output (green jack, rear) - S3 suspend/resume - VBT Untested for now (i.e. should work, will eventually test): - EHCI debug - Front USB 2.0 ports - The other audio jacks - PCIe ports - Non-Linux OSes Untestable (i.e. cannot test due to unavailable hardware): - PS/2 port - Serial port - SATA ports Not working: - USB 3.0 ports: The on-board VLI VL805 does not have a flash chip, so its firmware needs to be loaded on each boot. However, documentation about the (chip-specific) firmware loading procedure is nowhere to be found. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. Change-Id: I106c195c890823f07227739c6b30133b996f6510 Signed-off-by: PugzAreCute <me@pugzarecute.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-03soc/intel/common: Skip ME version log for Lite SKUSubrata Banik
This change skips the ME firmware version logging in print_me_fw_version() if the ME firmware SKU is detected as Lite SKU. The reasoning is that the RO (BP1) and RW (BP2) versions are already logged by the cse_print_boot_partition_info() function for Lite SKUs, making the additional log redundant. The check for the Lite SKU has been moved to print_me_fw_version(), where the decision to print the version is made, instead of in get_me_fw_version(), where the version information is retrieved. TEST=Able to build and boot google/rex. w/o this patch: [DEBUG] ME: Version: Unavailable w/ this patch: Unable to see such debug msg. Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-07-03soc/intel/cmn/cse: Make ME firmware version query function staticSubrata Banik
This change modifies the get_me_fw_version() function to be statically scoped within src/soc/intel/common/block/cse/cse.c, as it is only used by the print_me_fw_version() function in the same file. The function declaration is also removed from intelblocks/cse.h. The order of the function definitions in cse.c was also changed to be more logical, with the now static helper function get_me_fw_version() defined first, before it is used. TEST=Able to build google/rex. Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Conditionally disable ME status reportingSubrata Banik
This patch disables the ME status reporting functionality (dump_me_status, print_me_fw_version) in the CSE driver when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined. This is likely intended for platforms or configurations where the CSE communication is only limited to payload. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5e360408a7847968117df475ff244d79ceafa23f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03drivers/intel/ish: Skip ISH version call if CSE sync is done by payloadSubrata Banik
This patch skips the ISH firmware version print when CSE sync is done by payload. The payload is responsible to dump the ISH version as ISH version resides into the CSE boot partition table. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Skip CSE version call if sync is done by payloadSubrata Banik
This patch skips the CSE firmware version print when CSE sync is done by payload. The payload is responsible to dump the CSE version. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE EOP configsSubrata Banik
Refactor CSE lite End-of-Post (EOP) configs to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot will skip initiating CSE EOP operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_SEND_EOP_EARLY - SOC_INTEL_CSE_SEND_EOP_LATE - SOC_INTEL_CSE_SEND_EOP_ASYNC - SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD BUG=b:305898363 TEST=Able to build google/rex. Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03soc/intel/cmn/cse: Modify dependency on CSE lite configsSubrata Banik
Refactor CSE lite configs (specifically CSE sync related) to support the alternative of sending CSE communication from the payload. When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot will skip initiating CSE sync operations and rely on the payload CSE driver implementation. The following configs are modified to ensure coreboot skips CSE communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled: - SOC_INTEL_CSE_LITE_PSR - SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY - SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE - SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-07-03tree: Use <console/console.h> only when usedElyes Haouas
Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-07-02mb/asrock: Add Z87M OC Formula (Haswell)Jan Philipp Groß
This port was done via autoport and subsequent manual tweaking. Special thanks to Nicholas Chin! This port would have never succeeded without his help. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection switch and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - USB 2.0 Ports - Vertical Type A USB 2.0 - USB 3.1 Gen1 Ports - HD Audio Jack (audio output) - Front panel audio connector (audio output) - RJ-45 Gigabit LAN Port - SATA3 6.0 Gb/s connectors - mSATA/mini-PCI Express slot - half mini-PCI Express slot - PCI Express 3.0 x16 slots (both) - PCI Express 2.0 x4 slot - PCI Express 2.0 x1 slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection Switch - Slow Mode Switch (locks the CPU at 800MHz) not (yet) tested: - IR header - COM Port header - Power LED header - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - Optical SPDIF Out Port not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. - Post Status Checker (PSC) Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-023rdparty/fsp: Update submodule to upstream masterFelix Singer
The filename of the Elkhart Lake FSP binary changed in the FSP repository. It's unlikely that it will be renamed to the original name soon. Thus, update the filename in the coreboot repository. Updating from commit id cc6399e: 2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP) to commit id 800c857: 2024-06-25 15:47:28 +0800 - (Update Fsp.fd) This brings in 23 new commits: 800c857 Update Fsp.fd 41e4590 NEX AZB IPU24.4 (5254_00) FSP 0efd8a3 IoT RPL-PS PV (5045_47) FSP 196e3fe Update README.md 380afd8 Update README.md 5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP 22762e9 Merge branch 'master' of https://github.com/intel/FSP 8134dbd Elkhart Lake IPU2024.3 FSP 3819544 add required SECURITY.md file for OSSF Scorecard compliance a6ee963 Delete AlderLakeFspBinPkg.dec 9d819ea Deprecate Client/AlderLakeFspBinPkg f963690 Raptor Lake FSP C.1.C8.50 f67f9ef Raptor Lake FSP C.0.C8.50 68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP 6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP 8cf0372 IoT ADL-N MR4 (5061_00) e5ceb0b Merge branch 'master' of https://github.com/intel/FSP aada6a5 Elkhart Lake IPU2024.2 FSP 90d1d3b Update README.md 1a5a3ee Testing 61c069a NEX RPL-S MR3 (4445_03) FSP Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83294 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01nb/intel/sandybridge/chipset.cb: Add alias for `cpu_cluster`Angel Pons
Define a devicetree alias for `cpu_cluster` so that it can be referenced in C code as `DEV_PTR(cpu_bus)`. Change-Id: Id6ead3d98d8fc17cab44ecf0b2af60a23187e036 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-01commonlib/bsd/lz4_wrapper.c: Fix misaligned accessMaximilian Brune
Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8 The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM. Make the compiler generate code that adheres to natural alignment by fixing the LZ4_readLE16() function and creating LZ4_readLE32(). Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01drivers/spi/acpi: Add generic property listKun Liu
The touchscreen vendor (Goodix) needs to use this value (hid-report-addr) in the touch driver, and this value needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table. BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01soc/nvidia: Remove unneeded white spacesElyes Haouas
Change-Id: Ifd19cdcfbdf0b01984e0db0aa880fdcb256663b4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-01mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panelYang Wu
Add LCE_LMFBX101117480 MIPI panel for Wugtrio. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-01drivers/mipi: Add support for LCE_LMFBX101117480 panelYang Wu
Add STA panel LCE_LMFBX101117480 serializable data to CBFS. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf About the init code, we communicated with the vendor through the datasheet to confirm the writing method of each register value. BUG=b:331870701 TEST=build and check the CBFS includes the panel BRANCH=None Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-07-01mb/intel/tglrvp/dt: Remove superfluous USB2_PORT_EMPTY settingsFelix Singer
Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove it to clean up a bit. Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-29tgl mainboards: Move audio related settings into hda device scopeFelix Singer
Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-29tgl mainboards: Move genx_dec settings into eSPI device scopeFelix Singer
Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-29tgl mainboards: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-28tgl mainboards: Drop disabled audio settings from dtFelix Singer
Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28tgl mainboards: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28mb/google/volteer/baseboard: Drop disabled SATA settings from dtFelix Singer
Configuring them to 0 is equal to not configuring them at all. So remove them to clean up a bit. Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/intel/tglrvp/dt: Make use of device alias namesFelix Singer
Also, remove superfluous comments from devices which repeat their name. Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-28include/device_tree.h: Fix function name fdt_node_nameMaximilian Brune
Rename fdt_node_name to the actual function name and also rename the references. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I527146df26264a0c3af1ad01c21644d751b80236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83084 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28device/azalia_device.c: Always read-write GCAPAngel Pons
In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP register is RO (Read Only). However, it is known that in some Intel PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some of the bitfields in the GCAP register are R/WO (Read / Write Once). GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock bit for GCAP elsewhere. Lock GCAP by reading GCAP and writing back the same value. This has no effect on platforms that implement GCAP as a RO register or lock GCAP through a different mechanism. Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO for Gen1 SoCShuo Liu
For Gen1 SoCs, the range starting from the end of VTd BAR to the end of 32-bit domain MMIO resource window is reserved for unknown devices. Get them reserved. TEST=Build and boot on intel/archercity CRB Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-28soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamicallyShuo Liu
vtd_probe_bar_size is used to decide the BAR size. TEST=Build and boot on intel/archercity CRB Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28acpi: Add support for DRHD size reportingShuo Liu
VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD sizes larger than 4KB. If the value in the field is N, the size of the register set is 2^N 4 KB pages. Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying to use the beyond 4KB part of the DRHD BAR if they exist. They need the DRHD size field to set up page mapping before access those registers. Re-add acpi_create_dmar_drhd with a size parameter to support the needs. TEST=Build and boot on intel/archercity CRB Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/brox/variants/brox/fw_config.c: Remove unused macroElyes Haouas
Change-Id: I8ce94c8bc7ed137eaace12d6cb0befa6c0d39a37 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Disable CNVi Bluetooth based on fw_configPoornima Tom
When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned off, based on fw_config. Otherwise, when device boots without the cbi settings for wifi6, boot may fail with assertion error for line 817 & 819 of file 'src/soc/intel/alderlake/fsp_params.c'. BUG=b:345596420 BRANCH=NONE TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along with enumeration of corresponding BT device. Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable PCIe Wifi GPIOs based on fw_configPoornima Tom
PCIe based GPIOs of Wifi7 module are enabled based on firmware config. BUG=b:345596420 BRANCH=NONE TEST= Based on fw config configured, wifi6 or wifi7 along with bluetooth ports are detected. Change-Id: If0584e91b5143c6df742961657d242c046409b3a Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-28mb/google/nissa/var/nivviks: Enable Bluetooth for PCIEPoornima Tom
PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe based Wifi7 module. BUG=b:345596420 BRANCH=NONE TEST=With proper FW config enabled, BT gets detected on port8 Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Enable wifi7 on pcie root portPoornima Tom
Enable pcie based, discreete wifi7 on root port4. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi7 module detection based on cbi settings Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-28mb/google/nissa/var/nivviks: Add fw_config fields for wifi6 and wifi7Poornima Tom
Add a new fw config field for wifi category as WIFI_6, which is CNVi based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing CNVi based wifi port as well as bluetooth port. BUG=b:345596420 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-28mb/google/nissa/var/nivviks: Update config for CNViPoornima Tom
Add wake configuration and set 'add_acpi_dma_property'=true for CNVi. Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device. BUG=b:345596420 BRANCH=NONE TEST=SSDT dump showed below: Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-27arch/x86/mpspec: Use uintptr_t for mpc_apicaddrElyes Haouas
Change-Id: I6cc2b3947a2c79e8962985e035e7cc74c2deb307 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-27mb/google/brask/var/bujia: Configure Serial IO UARTs ModeShon Wang
This patch configures Serial IO UARTs mode as below. UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design. BUG=b:338917836 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-27mb/google/brox/var/lotso: GPP_B14 used for buzzerJing Tong
ALC257 does not supoort built-in digtal buzzer, So use external pwm to PCBEEP for beep sound. BUG=b:346956771 BRANCH=None TEST=emerge-brox coreboot sys-boot/chromeos-bootimage firmware-shell: devbeep -> can output beep normally. Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5 Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-27drivers/wifi: Support Wi-Fi 7 11be EnablementRavi Sarawadi
Add 802.11be (aka. Wi-Fi 7) enable/disable support based on document 559910 Intel Connectivity Platforms BIOS_Guidelines revision 8.3. There are countries where Wi-Fi 7 should be disabled by default. This adds capability for OEM to enable or disable by updating the board specific Specific Absorption Rate (SAR) binary. BUG=b:348345300 BRANCH=firmware-rex-15709.B TEST=SSDT dump shows that the _DSM method returns the value supplied by the SAR binary for function 12 Change-Id: Ifa1482d7511f48f5138d4c68566f07ce79f37a7a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-27lib/string: use size_t for local variable in strncmpFelix Held
Since the 'maxlen' parameter's type is changed to size_t, the type of the local variable 'i' which this is compared against should also be changed to size_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe35d3741bc6d8a16a3bad3ec27aafc30745d931 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83224 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-06-27lib/string: change return types to match C standardFelix Held
The return type of strspn and strcspn is supposed to be a size_t and not a signed integer. TEST=Now the openSIL code can be built with the coreboot headers without needing to add '-Wno-builtin-declaration-mismatch' or '-Wno-incompatible-library-redeclaration' to the cflags. Before the build would error out with various 'mismatch in return type of built-in function' errors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0ff612e2eee4f556f5c572b02cbc600ca411ae20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83223 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-27lib/string: change parameter types to match C standardFelix Held
The third parameter of strncpy and strncmp is supposed to be a size_t and not a signed int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83222 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-27device/azalia_device.c: Use `azalia_enter_reset()`Angel Pons
Use the existing `azalia_enter_reset()` function instead of explicitly clearing the bit (and having to explain in a comment what this means). Change-Id: I04924e68420a93a1ad46f5a7ab359e38c0f7e210 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83217 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-27commonlib/device_tree: Improve node and property allocation speedJulius Werner
Now that the device tree code has been made available in libpayload, we should reintroduce the node and property allocation optimization for libpayload's memory allocator that was originally dropped when porting this code from depthcharge to coreboot. On a Qualcomm SC7180 unflattening a normal ChromeOS kernel device tree, this saves roughly ~145ms. The total scratch space used is about ~1350 nodes and ~5200 properties, so we leave a little room to grow with the constants hardcoded here. Change-Id: I0f4d80a8b750febfb069b32ef47304ccecdc35af Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2024-06-26mb/google/fatcat: Add minimal code support for fatcatSubrata Banik
This patch adds initial code block required to build google/fatcat board with Intel Meteor Lake Silicon. Later after the initial board power-on is successful, we shall switch to Panther Lake silicon to build the google/fatcat reference design. BUG=b:347669091 TEST=Able to build the google/fatcat and able to hit power-on reset using Intel Meteor Lake SoC platform. Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-06-26acpi: Rename acpi_create_dmar_drhdShuo Liu
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-26mb/google/trulo/var/orisa: Add STORAGE_NVME in fw_config storage fieldAmanda Huang
Follow nissa baseboard setting for storage field. option STORAGE_EMMC 0 option STORAGE_NVME 1 option STORAGE_UFS 2 BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-26mb/google/brox/lotso: Add Fn key scancodeWen Zhang
The Fn key on Lotso emits a scancode of 94 (0x5e). BUG=b:322721490 TEST=Flash Lotso, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Signed-off-by: Wen Zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83204 Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-26mb/google/brox: Disable Touchscreen for hardware board version 1Karthikeyan Ramasubramanian
On board version 1 and later, touchscreen is not stuffed. Hence configure the relevant GPIOs as not connected, disable the concerned I2C bus in the devicetree as well as SoC chip config for board version 1. BUG=b:347333500 TEST=Build Brox BIOS image and boot to OS. Ensure that there are no peripherals detected in I2C 1 bus through i2cdetect tool. Ensure that no touchscreen devices are exported through ACPI SSDT table. Ensure that other I2C peripherals - eg. Trackpad and Ti50 are functional. Ensure that the device is able to suspend and resume for 25 cycles. Change-Id: Ia0578b90b0e8158ae28bcc51add637844ba6acf6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83199 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26mb/google/brox: Add default ACPI brightness levelsKarthikeyan Ramasubramanian
Kernel need the default brightness steps. Otherwise following error messages are observed in the kernel: [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS ACPI BIOS Error (bug): Could not resolve symbol [^^XBCL], AE_NOT_FOUND ACPI Error: Aborting method \_SB.PCI0.GFX0.LCD0._BCL due to previous error (AE_NOT_FOUND) BUG=b:346807006 TEST=Build Brox BIOS image and boot to OS. Ensure that the concerned error messages are resolved. Ensure that the backlight controls are functional. Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-06-26skl mainboards/dt: Move SsicPortEnable setting into XHCI device scopeFelix Singer
Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move serirq setting into LPC device scopeFelix Singer
Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83188 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-06-26skl mainboards/dt: Move SATA related settings into SATA device scopeFelix Singer
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move genx_dec settings into LPC device scopeFelix Singer
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-26skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scopeFelix Singer
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2024-06-25soc/intel/common: Extend WAIT_FOR_DP_MODE_ENTRY_TIMEOUT_MS to 1500msTony Huang
Some dongles require more time to be ready, this CL extedns the DP mode entry timeout from 0.5s to 1.5s and make sure the tested dongle display works. Before: [WARN ] DP not ready after 500ms. Abort. After: [INFO ] DP ready after 1211 ms BUG=b:348309582 TEST=emerge coreboot verify tested dongles and monitors display works Change-Id: I22d7800b50f6f7de9f147ae6998a5015d0dc0be9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83206 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-06-25device/azalia: Separate codec checking and initializationNicholas Sudsgaard
This also changes how debug messages will be printed. I focused on reducing clutter on the screen and made the style of the messages consistent. Before: azalia_audio: Initializing codec #5 codec not ready. azalia_audio: Initializing codec #4 codec not valid. azalia_audio: Initializing codec #3 azalia_audio: viddid: ffffffff azalia_audio: verb_size: 4 azalia_audio: verb loaded. After: azalia_audio: codec #5 not ready azalia_audio: codec #4 not valid azalia_audio: initializing codec #3... azalia_audio: - vendor/device id: 0xffffffff azalia_audio: - verb size: 4 azalia_audio: - verb loaded Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80332 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-25lotso: Update board type to BOARD_TYPE_ULT_ULXKun Liu
Update board type to BOARD_TYPE_ULT_ULX BUG=b:348147663 BRANCH=none TEST=Built and compare the results of command 'dmidecode --type 17 | grep Speed' [Before] Speed: 8400 MT/s Configured Memory Speed: 6400 MT/s [After] Speed: 8400 MT/s Configured Memory Speed: 5200 MT/s Change-Id: I049d7c19424f41e83480f4b80bafd6ef8b9e30f6 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
2024-06-25mb/google/dedede/var/kracko: Add LTE only daughterboard supportRobert Chen
Add FW_CONFIG for no port LTE skus, and probe LTE port in devicetree. BUG=b:339534479 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage flash and check boot log on DUT. Change-Id: I5235df33a36f3b9472ee8b615e4622f6ee3fb1a4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-25Kconfig: Update FW_CONFIG Kconfig optionsMartin Roth
If a board supports FW_CONFIG or ChromeEC CBI, the options should be selected by the mainboard. These are not something that need to be a choice to enable or disable in Kconfig. The defaults are pointless, so remove them. The symbols default to no. Correct the descriptions of FW_CONFIG_SOURCE_CBFS and FW_CONFIG_SOURCE_VPD. They come after CBI and do not override any other options. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Icf170dc2ef790d6f5a897a9c7c2ea64033bf1dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83118 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-25mb/google/trulo/var/orisa: Fill in ec.hAmanda Huang
Fill in ec.h according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83154 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-25mb/google/trulo/var/orisa: Fill in gpio.hAmanda Huang
Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-06-24acpi/acpi: Fix Qemu's XSDT patching codePatrick Rudolph
Since Qemu doesn't provide an XSDT, coreboot adds one as separate ACPI table. Qemu only provides the smaller ACPI 1.0 RSDP, but the XSDT can only fit into the bigger ACPI 2.0 RSDP. Currently the exsting RSDP is being reused, without a size check, which works fine on the first boot. However after reboot the XSDT pointer seems to be valid, even though the checksum isn't. Since the XSDT then isn't reserved again on reboot, the memory it's pointing to is reused by other tables, causing the payload/OS to see an invalid XSDT. Instead of corrupting the smaller existing RSDP, allocate a new RSDP structure and properly fill it with both, existing RSDT and XSDT. In addition return the correct length of allocated ACPI tables to the calling code. It was ommiting the size of the allocated XSDT and SSDT. TEST: Run "qemu-system-x86_64 -M q35" and reboot the virtual machine. With this patch applied XSDT is always valid from the OS point of view. Change-Id: Ie4972230c3654714f3dcbaab46a3f70152e75163 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83116 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-24mb/google/brox: Add support for batteryless bootingShelley Chen
Set PsysPL2 and PsysPL3 in addition to making adjustments to PL2 and PL4 in order to prevent brownouts when we don't have a battery or have an empty battery at boot time. BUG=b:335046538,b:329722827 BRANCH=None TEST=flash Able to successfully boot on a SKU1 with 45W, 60W+ adapters and SKU2 with a 60W or higher type C adapter. 30W is still being worked on. Change-Id: Ie36f16b2c938dce29cd2130a86fc8c08f5ba0902 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-24acpigen_ps2_keybd: Support a Do Not Disturb keyAseda Aboagye
This commit simply adds support for a Do Not Disturb key. HUTRR94 added support for a new usage titled "System Do Not Disturb" which toggles a system-wide Do Not Disturb setting. BUG=b:342467600 TEST=Build and flash a board that generates a scancode for a Do Not Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux kernel with patches[0] that add this new event code using `evtest`. [0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2024-06-24acpigen_ps2_keybd: Support an Accessibility keyAseda Aboagye
Add support for an Accessibility key. HUTRR116 added support for a new usage titled "System Accessibility Binding" which toggles a system-wide bound accessibility UI or command. BUG=b:333095388 TEST=Build and flash a board that contains an accessibility key. Verify that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0] that add this new event code using `evtest`. ``` Testing ... (interrupt to exit) Event: time 1718924048.882841, -------------- SYN_REPORT ------------ Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1 Event: time 1718924054.062428, -------------- SYN_REPORT ------------ Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0 Event: time 1718924054.195904, -------------- SYN_REPORT ------------ ``` [0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2024-06-24mb/google/brya: Create tereid variantSowmya V
This patch creates a new tereid variant, which is a Twin Lake platform. This variant uses Nereid board mounted with the Twin Lake SOC and hence the plan is to reuse the existing nereid variant code. BUG=b:346442939 TEST=Generate the Tereid firmware builds and verify with boot check. Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83145 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-24acer/aspire_vn7_572g: Drop superfluous SATA AHCI mode configurationFelix Singer
The SATA controller is configured to AHCI mode by default. Drop the setting from the devicetree. Change-Id: I027b393300e2cbad827e176afddc197007314f10 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop SataPortsDevSlp[x] setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24skl mainboards/dt: Drop SataPortsEnable[x] setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83176 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop SataSalpSupport setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83175 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
2024-06-24skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83174 Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24skl mainboards/dt: Drop SsicPortEnable setting if disabledFelix Singer
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-24mb/google/trulo/var/orisa: Configure SEN_MODE_EC_PCH_INT_ODL as inputAmanda Huang
Configure GPP_R2 as input, no pull according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-23skl mainboards: Move cpu_cluster device to chipset devicetreeFelix Singer
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-22mb/emulation/qemu-riscv/cbmem.c: Fix device_tree.h includeElyes Haouas
Change-Id: I0b49ff8b6275fdde326c79ec21c34faa03094f9e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-22treewide: Move device_tree to commonlibMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I990d74d9fff06b17ec8a6ee962955e4b0df8b907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77970 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21mb/google/brask/var/constitution: Generate SPD ID for supported partsMorris Hsu
Add supported memory part in mem_parts_used.txt, then generate. H54G56CYRBX247 BUG=b:199645942 TEST=run part_id_gen to generate SPD id Change-Id: I2169d71695d8d133d26cafe5c7be33b976dd8603 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83127 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hAseda Aboagye
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: d0771e49e7 MKBP: Increase key matrix size The original include/ec_cmd_api.h version in the EC repo is: d0771e49e7 MKBP: Increase key matrix size Change-Id: I4f3dfc3f145e50e6114894352cdc118ad5a9565b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82995 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Forest Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21include/input-event-codes.h: Update to latest HID treeAseda Aboagye
This commit simply updates the input-event-codes.h to the HID maintainers' tree at SHA c412e40267dd4ac020c5f8dc8c1cccc04e796ff4. Change-Id: Ic1fb9b18ced37866b84230929cd5c785d0dde9ba Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82993 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-06-21mb/emulation/qemu: Configure TSEG sizePatrick Rudolph
Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage. The remaining Qemu code can already handle the bigger TSEG region. TEST: Increased TSEG to 8MiB. Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-06-21commonlib/fsp_relocate: Add PE32+ supportPatrick Rudolph
Add support for PE32+ binaries which can be found on X64 UEFI builds. TEST: Able to relocate and boot a X64 FSP. Change-Id: I22586834d7c9f3ab3a5e31bba957584587ec14e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82680 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE infoKapil Porwal
Currently, the payload cannot create new CBMEM entries as there is no such infrastructure available. The Intel CSE driver in the payload needs below CBMEM entries - 1. CBMEM_ID_CSE_INFO to - a. Avoid reading ISH firmware version on consecutive boots. b. Track state of PSR data during CSE downgrade operation. 2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition information on consecutive boots. The idea here is to create required CBMEM entries in coreboot so that later they can be consumed by the payload. BUG=b:305898363 TEST=Store CSE version info in CBMEM area in depthcharge on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiBSubrata Banik
This change updates the Northbridge ASL to conditionally include a QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS` is above 4 GiB. If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the PCH reserved range, the existing handling of `SM01` remains unchanged (as a DWordMemory resource). TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB, verified ASL output. Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21soc/mediatek/mt8188: Respect ARM64_BL31_OPTEE_WITH_SMC optionYu-Ping Wu
Since BL31_MAKEARGS is already handled in arm64/Makefile.mk, remove the duplication from mt8188/Makefile.mk. In addition, reserve the memory range for running OP-TEE only if ARM64_BL31_OPTEE_WITH_SMC is enabled. BUG=b:347851571 TEST=emerge-geralt coreboot BRANCH=geralt Change-Id: I88a9a07a685a6c9fe9739b6101ccb8a5ce23fd8b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-21arch/arm64: Add Kconfig option ARM64_BL31_OPTEE_WITH_SMCYu-Ping Wu
Add a new Kconfig option ARM64_BL31_OPTEE_WITH_SMC to control whether to build the OP-TEE dispatcher for BL31. This config also enables the BL31 build option OPTEE_ALLOW_SMC_LOAD, which allows loading the OP-TEE image after boot via a Secure Monitor Call (SMC). For ChromeOS devices, CROS_WIDEVINE_SMC is also enabled to allow passing secrets from firmware to OP-TEE. BUG=b:347851571 TEST=emerge-geralt coreboot BRANCH=geralt Change-Id: I4dcf82d47b537146d71ce3cd2050ec597ed0734f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-20mb/google/nissa/var/sundance: Increase I2C1 hold time to 126nsRoger Wang
According to the vendor spec, I2C1 hold time needs > 100ns. System needs to adjust the I2C1 sda_hold value from 7 to 13, the system will change the I2C1 hold time from 70ns to 126ns. BUG=b:347157276 TEST=built bootleg and verified test result by EE team Change-Id: I722ec93177b6debf6b4c99de2df68c942560a3ff Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83080 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-20mb/google/brox/var/lotso: enable CNVi bluetoothJing Tong
Lotso's WIFI_BT is same design as brox, copy from brox. BUG=b:339612353 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I030e306dc5d9d3fcb6314bc491dbf5c9ae60bcb7 Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83126 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-06-19mb/google/brox/var/lotso: Update devicetree settingJian Tong
Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: Ic9a7a9062f5c6e45c5bd9617f3b2a0634b8dc1db Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83051 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-19mb/google/brox/var/lotso: Update verb table from ALC256 to ALC257Jing Tong
Update verb table provided by Realtek on 20240614. BUG=b:344471736 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Device list: cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name ALC257 cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name Realtek Headphone detection: Event: time 1718633617.056092, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1718633621.471708, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0 Event: time 1718633623.898046, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1 Event: time 1718633625.743663, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), value 1 Event: time 1718633625.743678, type 1 (EV_KEY), code 115 (KEY_VOLUMEUP), value 0 Change-Id: Idde8963de9302849f87b7c262f17d9c9d99b46dc Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83109 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18mb/google/nissa/var/riven: Disable unused GPIOs based on fw_configDavid Wu
Disable LTE, stylus and WFC related GPIOs based on fw_config. BUG=b:337169542 TEST=Local build successfully. Change-Id: I91adc4e70d0d23b737d4fa6725cd96e63108f874 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-18mb/google/nissa/var/sundance: disable pcie port7Roger Wang
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:328147465 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 01:09:59 +0000