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2020-09-06mb: remove duplicated Make code for spd.bin generationMichael Niewöhner
Drop duplicated code for spd.bin generation that is provided globally in lib/Makefile.inc. For all affected boards it has been verified that the output binary functionally matches the original one. The changed execution order of Make instructions influenced the cbfs file order. Hence, the rom images can't be compared directly. Thus, the output files of the two timeless abuild runs have been compared. Further, it was verified that the final files in cbfs stay identical, by comparing the extracted cbfs of each board. The boards (possibly) needing modification could be found with something like this (with false positives, though): find src/mainboard -name Makefile.inc | \ xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-06mb/system76/lemp9: Use absolute path for _GPEJeremy Soller
_GPE cannot be anywhere but at the root of the ACPI namespace. This change ensures that is always the case. Tested on lemp9, GPE still in correct location. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Ib31683b06e61da4b1859cd939c36879cebf4c03c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43630 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb/system76/lemp9: Drop DeepSx settingsJeremy Soller
The GPIOs required for DeepSx (e.g. SLP_SUS#) are not hooked up on the lemp9. Therefore, drop the DeepSx settings. Tested on lemp9, suspend works correctly. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: Iab179abd7adc3a65dcfc43ce1b5742d514b711fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/43629 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb/system76/lemp9: Enable SA thermal deviceJeremy Soller
Tested on lemp9, SA thermal device appears in lspci. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I527e586b1dae5f8087d2364c63c9db5bcb643214 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-06soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner
Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-05soc/intel/alderlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
List of changes: 1. Add required SoC programming till bootblock 2. Include only required headers into include/soc 3. Add CPU/PCH/SA EDS document number and chapter number 4. Include ADL-P related DID, BDF Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-05mb/system76/lemp9: Don't enable unused USB3 portFelix Singer
Don't configure USB3 port 4 since it's not used. Change-Id: I6919f5ec3a5be53373f2ab75063764287b53baf5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Michael Niewöhner
2020-09-04mb/*/Kconfig: Drop redundant 'select CPU_INTEL_HASWELL'Elyes HAOUAS
CPU_INTEL_HASWELL is already selected at nb/intel/haswell/Kconfig. Change-Id: I608286aae72bc740be642a72109472fb235f37bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-04soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select ↵Elyes HAOUAS
CPU_INTEL_COMMON_SMM' CPU_INTEL_COMMON_SMM is set to yes if CPU_INTEL_COMMON at cpu/intel/common/Kconfig. Change-Id: I7c8e1bb6b7c3199a24711b64a6cbba4de190c6d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-04soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the HECI3 controller. All corresponding mainboards were checked if the devicetree configuration matches the Heci3Enabled setting, and divergent devicetrees were adjusted. Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-04mb/google/volteer/variant/lindar: Update memory settingsRasheed Hsueh
Based on the Lindar's schematic, generate memory settings. util: rename lp4x spds to include "lp4x-" in name BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: Rasheed Hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I1ec35d62f8ed21356329b78a614114edad78c2bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Michael Niewöhner
2020-09-04soc/intel/tigerlake: Remove unused PID_SDX macroSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I177a146643f2196018182502fff8d82830e139dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/45019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-03soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment.Jason Glenesk
Previous CL (1916f8969b10e27fe06b3e0eb1caae632bd947f6) misinterpreted spec as requiring size alignment on all IVHD device entries. The correct requirement specifies only for 4-byte entries. The unneeded realignments result in gaps in the table. The kernel hangs in early boot due to the malformed table. Remove 8-byte entry alignment. BUG=b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Confirm IVRS contains no alignment gaps/corruption. Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-03soc/amd/picasso: Set max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts instead. This will result in SMBIOS type 17 displaying more accurate speed information. BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03memory_info: add max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is ambiguous and is interpreted differently in several places. Instead of renaming this field, this deprecates it and adds two new fields with unambiguous naming, max_speed_mts and configured_speed_mts. smbios.c falls back to using ddr_frequency when either of these fields are 0. The same value was being used for both configured memory speed and max memory speed in SMBIOS type 17, which is not accurate when configured speed is not the max speed. BUG=b:167218112 TEST=Boot ezkinil, no change to dmidecode -t17 Change-Id: Iaa75401f9fc33642dbdce6c69bd9b20f96d1cc25 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44549 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03soc/intel/cnl: Allow using the remaining Comet Lake FSPsFelix Singer
To allow using the 3 remaining Comet Lake SoCs, add a new Kconfig option for each of them and configure the paths to FSP header files and FSP binary. Change-Id: I4272a6ee08e19769a8a17c93bb3ce2421be0bbc9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Michael Niewöhner
2020-09-033rdparty/fsp: Update submodule pointer to current masterFelix Singer
Change-Id: I50bac5a70425495832649e0d6d6e91aad623f25c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03soc/intel/cnl: Add new Kconfig option which matches its FSPs nameFelix Singer
Since there are 4 different versions of FSPs for the Comet Lake platform, add a new Kconfig option for the currently used SoC being able to differ between the various SoCs and FSPs. The new Kconfig option selects the Comet Lake SoC as base for taking over its specific configuration and is only used for configuring the path to its specific FSP header files and FSP binary. Also, adjust all related mainboards so that their Kconfig selects the new option. For details, please see https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch and both images are equal. Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03mb/google/volteer/variants/volteer: route GPP_F14 via APICAlex Levin
GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162528549 TEST=verified on a volteer Change-Id: Ie262ceeaea1c07bcc99e1545f5eb99e0d0dee905 Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44948 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03soc/amd/picasso: Only build PSP bootloader & verstage into ROMartin Roth
The PSP bootloader and verstage are only used out of the RO region, so don't build them into the RW sections. BUG=None TEST=Build & Boot BRANCH=zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Add config for PSP verstage signing tokenMartin Roth
This allows a platform to specify the location of the signing token for the PSP verstage, and build it into the firmware image. BUG=b:166108929 TEST=Build file into PSP firmware, verify that it's present and has the correct ID. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Allow use of pre-built PSP verstageMartin Roth
To use a signed PSP verstage, we're going to need to build it first, then sign and store the binary. This patch allows the stored (signed) verstage binary to be used. BUG=b:166108929 TEST=Build with existing verstage binary instead of re-building it. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Move DRAM end to after transfer bufferJosie Nordrum
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below. BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03mb/google/zork: update DRAM table for berknipKevin Chiu
Add Dual DDR4 Samsung K4AAG165WA-BCTD 16Gb x 8 BUG=b:165956925 BRANCH=zork TEST=1. gen part id by gen_part_id 2. emerge-zork coreboot Change-Id: Ia21a561e9b89feeccb6509d9280eaf52cfc2f5a3 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-03trogdor: Assert EN_PP3300_HUBJulius Werner
Some Trogdor variants power their USB hub from a PMIC LDO that is already enabled by QcLib, and some have a discrete LDO that is controlled by GPIO_84. For the latter, let's make sure we assert that GPIO on boot. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I9d206cd7154ded3bf179e68c2b1421d0a8ee89f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: mturney mturney <mturney@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-03trogdor: Shuffle RAM and SKU ID pins (again)Julius Werner
We're moving a lot of pins around on Trogdor again. For firmware this only affects the RAM and SKU strapping ID pins. Since there are quite a few of the old devices in circulation this time and some people seem to care about mosys RAM information working, let's actually check the board revision and support both cases this time. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7728d8ea4b7f6e7ff6721ade90f975f6efd5ddd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-02mb/google/puff/var/noibat: Update DPTF parameters for noibatWisley Chen
1. Update paramerters form thermal team. 2. Update PL2 Max/Min to 51W/15W. BUG=b:167494420 BRANCH=puff TEST=build noibat and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: Id96e681e9a990a1a1eaeb22781b1c60a7369118b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45020 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/puff: Update DPTF parameters and TCC offset for faffyDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team. 3. Change PL2 min value from 25W to 15W. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-02mb/*/Kconfig: Drop redundant 'select DRIVERS_INTEL_WIFI'Elyes HAOUAS
DRIVERS_INTEL_WIFI is already set to yes. Change-Id: I09f628a9c1feb8992b6fe7c7ca93c75243ffc0f1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02Revert "mb/google/volteer/variant/lindar: Update memory settings."Patrick Georgi
This reverts commit 2ad859988b5243411393fdf3116eea281b92b1bb. Reason for revert: broke the build Change-Id: I7e7d917c2e8b698d5c7c3ce0b6d34e80696185f3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44993 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Iff28e4a29fab5c22c410cdc743d0402134c4ac56 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02mb/google/volteer/variant/lindar: Update memory settings.rasheed.hsueh
Based on the Lindar's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I75fb9254ec7aa40acc2e125f0c4fd31003d28be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-02mb/google/poppy/var/rammus: Update SPD table for RammusKane Chen
1. Add new SPD file, "samsung_dimm_K4E8E324ED-EGCG.spd.hex". 2. Add SPD support in Rammus memory table, as follows: SPD_SOURCES += samsung_dimm_K4E8E324ED-EGCG # 0b0110 SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b0111 BUG=b:166576463 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I82386507c4e996e0a59c26ce50de3bced45b1196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44854 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/sarien/Kconfig: Drop redundant 'select TPM2'Elyes HAOUAS
TPM2 set to yes by MAINBOARD_HAS_TPM2 at security/tpm/Kconfig file. Change-Id: I815d545618e2e734f8e9b65731bbb4bed0b2d93d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02mb/*/Kconfig: Drop redundant 'select GENERATE_SMBIOS_TABLES'Elyes HAOUAS
GENERATE_SMBIOS_TABLES is already set to yes at src/Kconfig Change-Id: I2845f4f329283360a49ea40dfee7d9a232ab4ea1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE'Elyes HAOUAS
POSTCAR_CONSOLE is already set to yes in console/Kconfig file. Change-Id: If520c33f5e36d569511b2441bf23aa90180591c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-02mb/google/kukui: Add LPDDR4X support for fennel/cerise/sternxuxinxiong
Modify the BOARD_SDRAM_TABLE_OFFSET as 0x10 BUG=b:162891673 BRANCH=kukui TEST=make Change-Id: I5a4794d6e899e35686c40a553b991643f9e35ea3 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianbo Zhang <zhangjianbo@huaqin.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-09-01mb/*/Kconfig: Drop redundant 'select CONSOLE_SERIAL'Elyes HAOUAS
'CONSOLE_SERIAL' is already set to 'y' at src/console/Kconfig. Change-Id: I350cf12a115c6ebe54a2b0821edc94c29db8d137 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-01mb/google/puff: Update DPTF parameters for kaisa and duffyDavid Wu
1. Apply the DPTF parameters receive from the thermal team. 2. Change PL2 min value from 25W to 15W. 3. Change PL2 max value from 64W to 51W. BUG=b:166696500 BRANCH=puff TEST=build and verify by thermal team Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-01mb/google/puff: Convert ASL file to new DPTF dt implEdward O'Callaghan
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check. Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31mb/google/zork: Fix SPD typo in trembyle makefileRob Barnes
Relative path to spd directory was wrong. BUG=b:167175547 TEST=Boot Trembyle SKU 2 Change-Id: I63ae4f39ba69d2d80c25ac7383b6eb953901f56d Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44946 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31device: Add method to configure bus mastering based on KconfigFelix Singer
The bus master bit is set at many places in coreboot's code, but the reason for that is not quite clear. We examined not setting the bus master bit whereever possible and tried booting without it, which worked fine for internal PCI devices but not for PCIe. As a PCIe device we used a Samsung M.2 NVMe SSD. For security reasons, we would like to disable bus mastering where possible. Depending on the device, bus mastering might get enabled by the operating system (e.g. for iGPU) and it might be required for some devices to work properly. However, the idea is to leave it disabled and configure the IOMMU first before enabling it. To have some sort of "backwards compatibility", add a method which configures bus mastering based on an additional config option. Since CB:42460 makes usage of this treewide, enable it by default to keep the current behaviour for now. Tested with Siemens/Chili, a Coffee Lake based platform. Change-Id: I876c48ea3fb4f9cf7b6a5c2dcaeda07ea36cbed3 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42459 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork: Fix active polarity of REPORT_EN pin in overridetreeFurquan Shaikh
GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means enable operation and 0 means stop operation. Override tree exposes this pin as stop GPIO. Thus, it needs to be configured as active low i.e. 0 = active (stop), 1 = inactive (enable report). Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31mb/google/zork: Fix active polarity of touchscreen reset GPIO in overridetreeFurquan Shaikh
v3.6+ of reference schematics have moved to using active low polarity for touchscreen GPIO. This change sets the default polarity in override tree accordingly to active low. To support boards from older builds, variant_touchscreen_update() already updates the polarity to active high. BUG=b:161937506 Change-Id: I370bdb27ea5d0601612d13b515113a6048018964 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/intel/elkhartlake/romstage: Do initial SoC commit till romstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 4. Clean up upd override in fsp_params.c, will be added later 5. Temporarily remove _weak attributes in fsp_param & romstage.c 6. Add required headers into include/soc/ from jasperlake directory Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-31soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblockTan, Lean Sheng
Clone entirely from Jasperlake This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/36550 List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 6. Add required headers into include/soc/ from JSL directory Elkhart Lake specific changes will follow in subsequent patches. 1. soc/intel/elkhartlake: Update Kconfig Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-31arch/x86/exit_car.S: Fix checking clflush supportArthur Heymans
The BT instruction stores its result in CF and not ZF so use the correct jump instruction. This fixes a hang in postcar on CPUs lacking support for this instruction. This concerns older pre-SSE2 hardware. Change-Id: I704e3c579150fb9b9a292ef0e83050e7bf7cb078 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-31mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVPShreesh Chhabbi
These changes are according to spd_binary_optimization_volteer_v0.4 sheet. Offset Current value Updated value Analysis 1 0x10 0x11 As per SPD spec rev 1.1 5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 2 ranks per ch, 16 bits device data width 18 0x05 0x04 4267MHz support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 4267MHz support BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/dedede/var/drawcia: Add elan USI touchscreenWisley Chen
BUG=b:155002684 TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I87d8575131e745dec818bc5864ca6b21ce0825af Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-31mb/amd/mandolin: move PCIe GPP clock setting to devicetreeFelix Held
Checked with the schematics that all PCIe clocks have a corresponding clock enable pin. BUG=b:149970243 BRANCH=zork Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork/dalboz: move PCIe GPP clock setting to devicetreeFelix Held
BUG=b:149970243 BRANCH=zork Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork/trembyle: add PCIe GPP clock setting to devicetreeFelix Held
BUG=b:149970243 BRANCH=zork Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31soc/amd/picasso/southbridge: make GPP clock outputs configurableFelix Held
Make the general purpose PCIe clock outputs configurable to be either permanently enabled, permanently disabled or dynamically enabled via their corresponding external #CLK_REQx pins in the board's devicetree. BUG=b:149970243 BRANCH=zork Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: rename GPP clock setting offsetsFelix Held
The _SHIFT postfix is a bit clearer than the _SHL one and more in line with the names used for this kind of defines in coreboot. The documentation on that register is currently wrong and will hopefully be fixed in the future; the defines should now match the hardware. BUG=b:149970243 BRANCH=zork Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31include/device/azalia_device: Fix typoPatrick Rudolph
The code using the macro was found not working after finally enabling the HDA PCI device on the hermes board. Fix a typo to generate the correct verbs. Tested on prodrive/hermes. Change-Id: I953c2e9fbebc1f02bdf71ce868a95f578300c3a1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44900 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork: update GPIO config for dirinbozKevin Chiu
dirinboz does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3. BUG=none BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/zork: update GPIO config for berknipKevin Chiu
berknip does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3. BUG=b:162376046 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I8d9b711ce1d7300181fe496d490dd33b38bc5983 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44893 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31soc/amd/picasso/southbridge.h: replace GPP_CLK_REQ_MAP_* with macrosFelix Held
Replacing the existing defines with macros makes them easier to use in a function that applies the setting for a certain GPP/GFX clock output. Also add macros for statically enabling or disabling the clock outputs and not only for configuring them as controlled by the #CLK_REQx pins. BUG=b:149970243 BRANCH=zork Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitionsFelix Held
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and this was probably just copied over from stoneyridge. BUG=b:149970243 BRANCH=zork Change-Id: I32f459026c4e8632672123681b20736245f198b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/volteer: Add probed fw_configs to SMBIOS OEM stringsTim Wawrzynczak
Some Linux kernel drivers bind to "DMI quirks." In this case, the audio fw_config is added as an OEM string, e.g., "AUDIO-MAX98357_ALC5682I_I2S" so the audio topology can be correctly discovered. But add all successfully probed fw_config items as well, because this makes it easier to view what is selected from userspace. BUG=b:161963281 TEST=With CBI FW_CONFIG field set to 0x201: localhost ~ # dmidecode -t 11 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7b7586b0ebfe7b2fd888f448a50ae086364fa718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-31fw_config: Add caching to successfully probed fieldsTim Wawrzynczak
Add a backing cache for all successfully probed fw_config fields that originated as `probe` statements in the devicetree. This allows recall of the `struct fw_config` which was probed. BUG=b:161963281 TEST=tested with follower patch Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0d014206a4ee6cc7592e12e704a7708652330eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/44782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-31{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' fileElyes HAOUAS
'drm_dp_helper.h' file is duplicated and not used. Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-31mb/pcengines/apu2/mainboard.c: Use 'PCI_BASE_ADDRESS_0' instead of magic numberElyes HAOUAS
Change-Id: I21378acd6408a4fae5600a54a41f695e54221dc2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44829 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/pcengines/apu1/mainboard.c: Use 'PCI_BASE_ADDRESS_2' instead of magic numberElyes HAOUAS
Change-Id: Ibc2446d7b8d4334e26ca6335179f50b7abe301cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44831 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/volteer: add GPP_F11 to baseboard gpio_tableNick Vaccaro
GPP_F11 was in the early gpio table, but the definition was missing from the main gpio_table. This change adds GPP_F11 to the gpio_table array. BUG=none TEST="emerge-volteer coreboot" and verify it builds correctly. Change-Id: I40f887300a9dfd4f8e790031b77bbee8a014f499 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-31mb/google/volteer: add generic DDR4 SPDs for EldridNick Vaccaro
Add Makefile.inc to include six generic DDR4 SPDs for the following parts for Eldrid: DRAM Part Name DRAM ID to assign H5AN8G6NDJR-XNC 0 (0000) MT40A512M16TB-062E:J 1 (0001) H5ANAG6NCMR-XNC 2 (0010) K4A8G165WC-BCWE 0 (0000) K4AAG165WA-BCWE 3 (0011) MT40A1G16KD-062E:E 3 (0011) Add mem_list_variant.txt as a manifest of eldrid's DRAM parts for use by gen_spd, the generic DD4 SPD generation tool. Add dram_id_generated.txt to specify DRAM ID strap settings. NOTE that Eldrid specified DRAM IDs for the first three parts to be 0 though 2 (i.e. no combined DRAM IDs for parts that use the same SPD). BUG=b:161772961 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds without error. Change-Id: Ica62e299ed40e60c2d5928b29ead5d2205b1af66 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44272 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/biostar: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4c7f23615bcfd9c2bda2cac8808544b98f8e25a2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-31mb/amd: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ib82689150689716bc9afdf8d4527a1dcd5deae56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31superio/winbond/wpcd376i: Resurrect the driverSamuel Holland
This SuperIO chip is used on the Intel DQ45EK mainboard. Restore the driver that was deleted in commit d3a1a4171ee9 ("src/superio: Remove unused superio chips"). Changes from the previous version include: - Replacing the early serial implementation with Winbond common code, - Replacing the license boilerplate with SPDX headers, and - Removing unnecessary header file references. Change-Id: I0ff1a63c47d5dff2599c83a1cebe1ac5ff2136b1 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31vendorcode/google: Add error handlingJohn Zhao
Coverity detects missing error handling after calling function tlcl_lib_init. This change checks the function tlcl_lib_init return value and handles error properly. Found-by: Coverity CID 1431994 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ib831646b6a231ad57e3bfef85b801b592d572e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-31nb/intel/sandybridge: Add ECC error injection register informationAngel Pons
Change-Id: I669a611e804d67bb6e87775d273dc24b03b06691 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/volteer/var/halvor: Update TBT2 setting for HalvorFrank Wu
Enable TBT2 setting in overridetree.cb based on schematic. BUG=b:165175296, b:166060548 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I23ecf76a3c2f631211b0ae2898707c68862b374b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-31mb/google/puff: Set TCC offset to 5 for kaisa and duffyDavid Wu
Set tcc offset to 5 degree celsius for kaisa and duffy BUG=b:166696500 BRANCH=puff TEST=Build, and verify test result by thermal team. Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: add a pull-down for MODEM_CLKREQ / CNVI_CLKREQMichael Niewöhner
MODEM_CLKREQ / CNVI_CLKREQ has no external pull-down resistor. When there is no M.2 card populated, the pin is floating. Thus enable an internal 20K PD. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I37e0a9d7e9e0a8c8a7ac198abfd3995b8b0f9e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-30mb/system76/lemp9: add wifi devicesMichael Niewöhner
Add CNVi and PCIe wifi devices to the devicetree and enable the wifi driver and SMBIOS tables in Kconfig. Test: both CNVi and PCIe wifi devices work fine Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I16e04dbbf5fc3a163ce5a2bb8de646877d5cbc0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43654 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: rework commentsMichael Niewöhner
Rework the comments: - fix wrong gpio / net names - convert all comments to <gpio> / <net name> - add more information where appropriate Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I51b552fd3255d5627dcc012e677bad51be517cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43650 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: convert PAD_CFG_TERM_GPO to PAD_CFG_GPOMichael Niewöhner
Convert PAD_CFG_TERM_GPO with pull "NONE" to its shorter equivalent PAD_CFG_GPO. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9ed4d97ba184fa3e72425d5d16042a142b0640b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43649 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: disable unused pad for INTP_OUTMichael Niewöhner
INTP_OUT can be used as Type-C VBUS sense input/interrupt but is currently unused in coreboot. It isn't a requirement for PD to work. Disable it for now. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I233fbb562969487dff095ba6589fb9da3301ae4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43647 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: disable internal SATAXPCIE pull-upsMichael Niewöhner
Disable internal pull-ups for SATAXPCIE pads since there are external ones at the M.2 slot's PEDET pins. Test: both, SATA and NVME devices work fine on both slots Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43645 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: gpio: configure unused padsMichael Niewöhner
There are pads being unused for various reasons: a) missing board support (DeepSx: SUSWARN#) b) unneeded feature ID pins - currently no known device models without keyboard backlight - currently no known device models without TPM c) BOARD_ID (L140CU/L140ZU) is fixed and known at build time d) DDR_TYPE_*: there is only one known ram model e) strap-only pads f) unconnected pads Configure them as NC with appropriate pull-up if no external pull exists. The latter was checked by schematics and looking at the board. When any of the unused ID pins is needed in the future, they can be reactivated easily (configure as GPI). Further, convert from use of legacy macro PAD_CFG_NC to PAD_NC. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43644 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/google/volteer: Update flashmap descriptor for CSE Lite FW updateJamie Ryu
To support CSE Lite firmware update, CSE RW partition is extracted from CSE blob binary and added to FW_MAIN_A and FW_MAIN_B. CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and FW_MAIN_B is increased to avoid an overflow. BUG=b:140448618 TEST=build with me_rw binary blob for volteer and boot to kernel. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/system76/lemp9: enable TPMMichael Niewöhner
L140CU has a TPM2 connected via SPI. Add the TPM device to the devicetree and enable it. According to Intel doc#615170-001, PIRQ is required for SPI TPM to work. Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as TPM interrupt in Kconfig. Note: The PCH maps either LPC TPM or SPI TPM to the same address and handles either LPC or SPI communication transparently. Thus we can use MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address. Tested, but only polling works currently, because there is some upstream issue with the tpm_tis module in current Linux kernels. [1] [1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30security/intel/txt/getsec.c: Do not check lock bitAngel Pons
This allows calling GETSEC[CAPABILITIES] during early init, when the MSR isn't locked yet. Change-Id: I2253b5f2c8401c9aed8e32671eef1727363d00cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-30security/intel/txt: Add missing definitionsAngel Pons
Change-Id: I3ca585429df318c31c2ffd484ec91a7971f18f27 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44882 Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize stepAngel Pons
This is a security lock and is required for TXT, among other things. Tested on Asrock B85M Pro4, still boots. Change-Id: I7b2e8a60ce92cbf523c520be0b365f28413b9624 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44884 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support for ↵Kevin Chiu
burnet/esche Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB BUG=b:165956924 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30cpu/x86/smm/smmhandler: Fix x86_64 assembly exitPatrick Rudolph
Fix an issue the assembler didn't warn about to fix a crash on real hardware. qemu didn't catch this issue either. The linker uses the same address for variables in BSS if they aren't initialized in the code. This results in %edx being set to the value of %eax, which causes an exception restoring IA32_EFER on real hardware. Tested on qemu with KVM enabled. Change-Id: Ie36a88a2a11a6d755f06eff9b119e5b9398c6dec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-29sb/intel/bd82x6x: Factor out common ME functionsAngel Pons
We can now factor out the essentially duplicated ME functions. We include a .c file to preserve reproducibility. This is needed because there are two different `mei_base_address` global variables, and we have to access the same variables in order for builds to be reproducible. The duplicate global in `me.c` and `me_8.x.c` will be completely gone once this new `me_common.c` file becomes a standalone compilation unit. We are wrapping some things in static inline functions, as they won't be directly accessible anymore after moving to a separate compilation unit. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I057809aa039d70c4b5fa9c24fbd26c8f52aca736 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-29PCI IDs: Add PCI ID for CML DPTF/DTT PCI deviceEdward O'Callaghan
This PCI ID is required in order for the CML devices to perform SSDT generation for DPTF. CML Processor, EDS, Vol 1, Table 9-5, Section 9.2. BUG=b:158986928 BRANCH=puff TEST=builds Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Andrew McRae <amcrae@google.com>
2020-08-28amd/picasso/psp_verstage: add vboot rsa functionKangheui Won
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa signature against digest using PSP svc. This function will be later used by vboot to accelerate rsa verification. BUG=b:163710320, b:161205813 TEST=build zork firmware with vboot modification, confirm it's booting and boot time is reduced by ~230ms. Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork: Modify USI_RESET_L GPIO 140 to be active to lowKane Chen
Modify USI_RESET_L GPIO_140 in touchscreen power on/off sequence to be active low. BUG=b:160126287 BRANCH=Zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I53dd872fdacb95cda43f297d2c3f9c6723b27bad Reviewed-on: https://review.coreboot.org/c/coreboot/+/44858 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/zork: Disable SATA device for all Zork platforms to save powerMatt Papageorge
SATA is currently turned on in the Dalboz and Trembyle base board variant devicetrees, even though no Google/Zork device uses SATA; for mass storage they either use eMMC or NVME PCIe SSDs. This patch disables both the SATA PCIe device and the bus where it was the only enabled device on. The next patch in this patch train sets a new FSP-M UPD setting BUG=b:162302027 Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068 Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabledMatt Papageorge
FSP has recently added support for a UPD switch to power gate SATA. This change adds the coreboot side of the feature. To avoid having two SATA enable options, the value of the sata_enable UPD is determined by the enable state of the AHCI controller in the platform devicetree. BUG=b:162302027 BRANCH=zork TEST=Verify AHCI controller can be hidden/disabled. Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28vc/amd/fsp/picasso: Add FSP-M UPD enable_sata to 0xC7 to match FSPNikolai Vyssotski
BUG=b:162302027 BRANCH=zork Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I4b5c3b351b6232f8b0418ead47d87aaddd350668 Cq-Depend: chrome-internal:3201648 Cq-Depend: chrome-internal:3202602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44863 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/ocp/deltalake: Configure FSP DCI via VPDJohnny Lin
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled. Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-28vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt socJonathan Zhang
Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 07:07:23 +0000