summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2014-09-29Remove stale char[] initialization causing unaligned memory accessMarcelo Povoa
This throws an alignment fault when run in ARMv8 Foundation model and seems unnecessary, so remove it. Change-Id: I2e3aa54502c292958ba44ff4e2e71c27653f2e1a Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186744 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 57510d553c56ca5dfb4765836ddb901744e29e20) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6974 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-29google/panther: Be safe about invalid thermal readingsStefan Reinauer
In case we get an invalid thermal reading, let's run the fan at full speed rather than at low speed. This might impact the user experiance slightly in cases where the bad reading does not happen while the system is hot, but it will increase stability in the cases where the system is actually overheating. Also, set the critical temperature below tjmax, because otherwise thermal shutdown by the OS will never be triggered. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Iab262f1f17a5dff875c596d9e8d50e4e50ee90f9 Reviewed-on: https://chromium-review.googlesource.com/188556 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 721fc2361ea9c6fea75409be57726294ce840f03) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6962 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-29google/chromeec: Notify DPTF charger participant on AC state changeDuncan Laurie
The DPTF charger particpant device needs to be notified when the AC state changes so it can re-evaluate the PPCC object and apply the proper charge rate limit if necessary. Change-Id: I6723754e2fe12862f50709875140fcadcddb18eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189029 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brad Geltz <brad.geltz@intel.com> (cherry picked from commit ed1ee577014421b021e8814edc91a1b696bf9eed) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-29arm: Fix up new cache flush algorithm and replace dcache_*_all() with itJulius Werner
This patch fixes the remaining few bugs in our shiny new cache iteration by set/way/level algorithm to actually make it work: It makes it start from cache level 0 (previously it would always start at LoC and be "done" instantly), fixes up the two shifts that isolate the set bits at the end (which didn't seem to account for the fact that the first shift affects the second), and throws an S bit on that last shift so that it actually affects the conditionals after it. In addition, also moves the next_level block to the top so that we can share (and thus eliminate) some code at initialization, and turns the whole thing into a thrice-instantiated macro to create functions that fit our existing interface. Change-Id: I1338a589cbb37d74ea6e7a3d4f67ff827e24edbe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183879 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 6d94f8330191c316fe093ddb5288329453da8a4b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6932 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-29arm: Import armv7_dcache_wbinv_all function from NetBSDJulius Werner
This patch pulls in NetBSD's full cache flushing algorithm for ARM, to replace our old, slow and slightly overzealous C-only implementation. It's a beautiful piece of code that manages to run on only caller-saved registers (meaning it doesn't need to write to memory) in a very tight loop, and it's BSD-licensed to boot (which we need for libpayload). Unfortunately it's also not quite correct, but I can fix that. Pulling the original in a separate commit to make it more obvious what changes are mine. Change-Id: I7a71c9e570866a6e25f756cb09ae2b6445048d83 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183878 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4698467320613d7ddc39714f40aacbc990af9399) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6931 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-25x86/mtrr: Enable MTRR's before enabling cachingIsaac Christensen
Fix up the following commit by enabling the MTRR's before enabling caching. 7756fe7 x86: Minimize work done with the caches disabled in mtrr functions. Also fix two typos in comments. Change-Id: If751b815f9dab781fc38c898cf692f0940c57695 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6969 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-09-25Peppy/Falco: always use native graphicsRonald G. Minnich
The products having shipped, and living in their own branch, we might as well enable native graphics since: 1. it works 2. it removes a blob and the only good blob is a dead blob 3. it's faster 4. when we have problems, we can diagnose them more easily 5. when we get to newer kernels the boot time will magically get faster as the driver realizes graphics is running. Where else do you get a 3-4 second speedup for free? Change-Id: Iad937320e7f46b1de7ab00dace04115a7f182ed1 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/181225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 7b567d87a9fcf6736e90e730bd052e4465d57bdf) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6912 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-25snow: Rename snow to daisy.Gabe Black
The name snow goes by in many places in chromeos is daisy. Snow is technically a variant of daisy and should really be called daisy_snow, but for historical reasons the daisy board with no variant was used instead. To make it easier to work with within chromeos, this change renames the snow board to daisy. Change-Id: I569b31bf417db55be91832f15271bea4bc30f163 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183553 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 13f24d967251c18dce2a00bcea915f448c4c6aa7) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6929 Tested-by: build bot (Jenkins)
2014-09-25soc/qualcomm: Add generic support skeleton for ipq806xFurquan Shaikh
Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2014-09-25peppy and falco: set panel power timings in northbridge, using devicetree, ↵Ronald G. Minnich
not mainboards Historically we had set panel timing in the mainboard gma code. This goes back to the replay-attack video startup. We can let the haswell gma code set these values from the device tree settings. Change-Id: If32150d2857241ca2d2c88880086f49d25815d76 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/180521 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 406eab3ca6a9bc59382866817786bf96bbb19d56) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6911 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-25pit: Rename pit to peach_pit.Gabe Black
The name pit goes by in many places in chromeos is peach_pit, where peach is the base name and pit is the name of this particular variant. To make it easier to work with within chromeos and to make the board names a little less ambiguous, this change renames the pit board to peach_pit, and from Pit to Peach Pit. Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183552 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cbbe1e9f04e34436a1bbae28628e0b5630d41054) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6928 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-24x86: Minimize work done with the caches disabled in mtrr functions.Gabe Black
The code in src/cpu/x86/mtrr/mtrr.c disables caching in a few places when changing mtrr settings. While I can't find anything that says that's actually required, I can believe it's necessary. With that said, other code around the wrmsr instructions which actually modify the settings should be able to run with caching enabled with no ill effects. This is particularly true for two calls to printk, one in the fixed mtrr code and one in the variable, which could result in an arbitrary amount of work being done without caching. When changing the implementation of the cbmem console, these two printks caused a significant regression in boot performance on link of about 70ms which is about 10% of total firmware boot time. When the window where the cache is disabled is minimized, both this and the new implementation were about 30ms faster than the original boot time. For the variable MTRRs, we now store what we want to set the MSRs to and then write them all at once at the end of commit_var_mtrrs(). This way we don't have some set and some not, but we still minimize the time we spend with the caches disabled. Change-Id: I5139b262bd2d13f79afd88e2e2c0f514fb3e27c9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/187811 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 31529d6d965676c6cedeb62137eabc26819956fc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6952 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-24baytrail: add 80c microcode for C0 partsAaron Durbin
Incoprorate 80c microcode version for C0 stepping parts. Change-Id: I2a76b4c92cac0aca5949313060f1d315ebd8e1a9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187842 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 318027a8853060e7223524dbd2ad7c3b6cc9b766) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-24big: Create a nyan_big mainboard which is a copy of nyan.Gabe Black
The nyan_big mainboard is very similar to nyan, but will be different in a few ways. For instance, the BCT will be different, and the GPIOs may need to be configured slightly differently. This change also adds prefixes to the kconfig variables in "choice" blocks for both boards since having multiple instances of choice blocks with the same options confuses kconfig even if all of the instances have mutually exclusive dependencies. Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/183532 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1a453fe1aa68b3d12936dd48cc6c94b54f81579) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6927 Tested-by: build bot (Jenkins)
2014-09-24arm: add missing gc-sections for ramstageIsaac Christensen
This is a fix up for recent patch: c505837 arm: Have the linker garbage-collect unused functions and variables I missed adding --gc-sections to a couple of the ramstage lines. Change-Id: I81178eb99fddbd99c603c79ba506db51af975b27 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6956 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-24northbridge/intel/i945/Kconfig: Select VGAPaul Menzel
Commit 0092c999 (i945: Support text mode gfx init) [1] broke building the Lenovo X60 with native graphics initialization by selecting `CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT`. CC northbridge/intel/i945/gma.ramstage.o src/northbridge/intel/i945/gma.c: In function 'intel_gma_init': src/northbridge/intel/i945/gma.c:398:2: error: implicit declaration of function 'vga_textmode_init' [-Werror=implicit-function-declaration] Selecting the Kconfig variable VGA makes the declaration of the function `vga_textmode_init()` to be included by the preprocessor. [1] http://review.coreboot.org/6723 Change-Id: Iecbb2898193078b8738425cea13cb7e6da508cab Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6947 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-09-23rmodule: Fix rmodule.ld for 64-bitFurquan Shaikh
Fix the alignment for 64-bit systems Change-Id: I7fcb1683d760b96307759b7d44d8770dd49a02e3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/214326 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6953 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-09-23coreboot arm64: Add support for arm64 into coreboot frameworkFurquan Shaikh
Add support for enabling different coreboot stages (bootblock, romstage and ramstage) to have arm64 architecture. Most of the files have been copied over from arm/ or arm64-generic work. Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/197397 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934) This patch is essentially a squash of aarch64 changes made by these patches: d955885 coreboot: Rename coreboot_ram stage to ramstage a492761 cbmem console: Locate the preram console with a symbol instead of a sect 96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3 3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage 25fd2e9 aarch64: Remove CAR definitions from early_variables.h 65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM 9484873 aarch64: Change default exception level to EL2 7a152c3 aarch64: Fix formatting of exception registers dump 6946464 aarch64: Implement basic exception handling c732a9d aarch64/foundation-armv8: Basic bootblock implementation 3bc412c aarch64: Comment out some parts of code to allow build ab5be71 Add initial aarch64 support The ramstage support is the only portion that has been tested on actual hardware. Bootblock and romstage support may require modifications to run on hardware. Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6915 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-09-22google/{falco,peppy}/gma.c: Do not include non-existent "hda.h"Paul Menzel
Commit 75c83870 (azalia: Shrink boilerplate) [1] removed the header file `hda_verb.h`. This header is still included in the mainboard’s `gma.c`, causing the following build error, when native graphics initialization is enabled. CC mainboard/google/falco/gma.ramstage.o src/mainboard/google/falco/gma.c:34:22: fatal error: hda_verb.h: No such file or directory This was not caught, as native graphics initialization is not enabled for the build tests. It turns out that the array `mainboard_cim_verb_data` is not used in `src/mainboard/intel/wtm2/hda_verb.h`, so fix the problem by removing the inclusion. [1] http://review.coreboot.org/6840 Change-Id: I91e4f00a3030bdef0278102df2783258389bca13 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6946 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-22google/link, intel/wtm2: Do not include non-existent "hda.h" in i915.cPaul Menzel
Commit 75c83870 (azalia: Shrink boilerplate) [1] removed the header file `hda_verb.h`. This header is still included in the mainboard’s `i915.c`, causing the following build error, when native graphics initialization is enabled. CC mainboard/intel/wtm2/i915.ramstage.o src/mainboard/intel/wtm2/i915.c:34:22: fatal error: hda_verb.h: No such file or directory This was not caught, as native graphics initialization is not enabled for the build tests. It turns out that the array `mainboard_cim_verb_data` is not used in `src/mainboard/intel/wtm2/hda_verb.h`, so fix the problem by removing the inclusion. [1] http://review.coreboot.org/6840 Change-Id: Ic902581c6809a1069e169cc874678146a24d75f3 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6945 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-22haswell: Move to per-device ACPIVladimir Serbinenko
Change-Id: Ic724dcf516d9cb78e89698da603151a32d24e978 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6814 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-22tegra124/nyan: memory and display updatesAndrew Bresticker
tegra124: use pll_c_out1 as sclk parent Reviewed-on: https://chromium-review.googlesource.com/180865 (cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f) tegra124: take LP cluster out of reset Reviewed-on: https://chromium-review.googlesource.com/180866 (cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3) tegra124: norrin: display code clean up Reviewed-on: https://chromium-review.googlesource.com/181003 (cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17) tegra124: Change the display hack to use window A Reviewed-on: https://chromium-review.googlesource.com/182001 (cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a) tegra124: norrin: Initialize frame buffer Reviewed-on: https://chromium-review.googlesource.com/182090 (cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167) nyan: do not enable pull-ups on SPI1 (EC) data pins Reviewed-on: https://chromium-review.googlesource.com/181063 (cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c) tegra124: Add source for the LP0 resume blob. Reviewed-on: https://chromium-review.googlesource.com/183152 (cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b) tegra124: Revise Memory Controller registers structure definition. Reviewed-on: https://chromium-review.googlesource.com/182992 (cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1) tegra124: Add more PMC register details. Reviewed-on: https://chromium-review.googlesource.com/183231 (cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829) tegra124: Add SDRAM configuration header file from cbootimage. Reviewed-on: https://chromium-review.googlesource.com/182613 (cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4) tegra124: Revise sdram_param.h for Coreboot. Reviewed-on: https://chromium-review.googlesource.com/182614 (cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8) tegra124: Fix EMC base address. Reviewed-on: https://chromium-review.googlesource.com/183602 (cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e) tegra124: Add EMC registers definition. Reviewed-on: https://chromium-review.googlesource.com/183622 (cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a) tegra124: Never touch MEM(MC)/EMC clocks in ramstage. Reviewed-on: https://chromium-review.googlesource.com/183623 (cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023) tegra124: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/183833 (cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d) tegra124: Allow setting PLLM (clock for SDRAM). Reviewed-on: https://chromium-review.googlesource.com/183621 (cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683) tegra124: SDRAM Initialization. Reviewed-on: https://chromium-review.googlesource.com/182615 (cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce) tegra124: Get RAM_CODE for SDRAM initialization. Reviewed-on: https://chromium-review.googlesource.com/183781 (cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8) Squashed 18 nyan/tegra commits for memory and display. Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6914 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-22arm: Update mem* functions to newer versionsJulius Werner
The memcpy/memset/memmove assembly implementations have been taken from U-Boot, which originally got them from Linux. I turns out that they are actually not that bad, but they could use an update. This patch pulls in the current Linux upstream versions of those files, removing some old U-Boot cruft such as checking whether the two pointers in a memcpy() are equal (really now?) or side-stepping the R8 register because it was used for special purposes. It also returns to the good old Linux ENTRY/ENDPROC macros since we have them now anyway, and straightens out the W() macro in preparation for unified thumb support. Change-Id: I138af269b423bef0a237759ac29f1ee58ca206a0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182179 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 777127997bde5785b21d422d0b6eb04c4328b478) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6918 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-22arm: Move libgcc assembly macros to arch/asm.hJulius Werner
libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182178 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-22Add check_member macro to allow clean and easy struct offset checkingJulius Werner
This patch adds a new static assertion macro that can be used to check the offsets in structures that overlay register sets at compile time. It uses the _Static_assert() declaration from the new ISO C11 standard, which is supported (even without -std=c11) by GCC after version 4.6. (There is supposedly also support in clang, although I haven't tried it... let's deal with compiler issues when/if they turn up.) I've added it to all structures for our current ARM SoCs for now, and I think every new register overlay we add going forward should use them (at least for the last member, but feel free to add more if you think it's useful). Change-Id: If32510e7049739ad05618d363a854dc372d64386 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6905 Tested-by: build bot (Jenkins)
2014-09-22arm: Have the linker garbage-collect unused functions and variablesJulius Werner
This patch activates -ffunction-sections and -fdata-sections for the compiler and --gc-sections for the linker. This will strip out all unused functions and static/global variables from the final binaries and reduce the amount of data we need to read over SPI. A quick test with ToT images shows a 2.5k (13%) / 10k (29%) / 12k (28%) reduction on Nyan and 3k (38%) / 23k (50%) / 13k (29%) on Pit, respectively for bootblock / romstage / ramstage. Change-Id: I052411d4ad190d0395921ac4d4677341fb91568a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177111 (cherry picked from commit 5635b138778dea67a5f179e13003132be07f7e59) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6904 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-22snow/pit: include chromeos.c in romstageIsaac Christensen
When CONFIG_CHROMEOS is enabled, both systems currently fail to build romstage due to undefined symbols. Change-Id: I0edcb141b9a79fad6b1a629bf77cae656c3d6319 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6873 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-19baytrail/rambi: spi, charger, and audio updatesAaron Durbin
baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-09-19chrome ec: Add support for limiting charger currentDuncan Laurie
Update the ec_commands header (direct from EC source) and add support for the new charger current limit interface which will be used by DPTF. Change-Id: Ia9a2a84b612a2982dbe996f07a856be6cd53ebdb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/185758 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1fcca2d75856ecefd3aeb1c551182aa76d649466) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6925 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-19exynos5250: remove unused ret variable in cpu.cIsaac Christensen
Showed up as an error when '--gc-sections' was added as a flag to the compiler. Change-Id: I214d3e16a72fca0becc677d7af66097464d64247 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6926 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-19mainboard/lenovo/t530: Make native VGA init 'user-friendly'Edward O'Callaghan
Default to do native VGA init since this machine is a laptop and the user would likely want to use it as such. Also, if you know what this is you know how to turn it off if you want to. Change-Id: I55f91a48affbd0ec93b0bb0c88c531d15c32ba21 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6903 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-09-18samus: Enable XHCI mode by defaultDuncan Laurie
- Enable xhci_default setting in devicetree - Enable usb_xhci_on_resume setting for PEI Change-Id: I2a3965a222ce571a2ad43f568fc2d0ecb94a77bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180673 (cherry picked from commit c5ef875f6d148964b8ad62a3fe79916c758dbc57) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6908 Tested-by: build bot (Jenkins)
2014-09-18lynxpoint: Don't enable SMI handling of TCODuncan Laurie
We have no good reason to be handling the TCO timeout as an SMI since we aren't doing anything special with it and clearing the status in the handler prevents the reboot from actually happening. Change-Id: I074ac0cfa7230606690e3f0e4c40ebc2a8713635 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180672 (cherry picked from commit 608a2c5768e9300c81b7c72fb8ab7a0c7c142bec) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6907 Tested-by: build bot (Jenkins)
2014-09-18rambi/baytrail: ACPI, GPIO, audio, misc updatesShawn Nematbakhsh
rambi: Change RAM_ID GPIOs to GPIO_INPUT Reviewed-on: https://chromium-review.googlesource.com/182934 (cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0) baytrail: initialize rtc device Reviewed-on: https://chromium-review.googlesource.com/183051 (cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821) baytrail: Set SOC power budget values for SdpProfile 2&3 Reviewed-on: https://chromium-review.googlesource.com/183101 (cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55) baytrail: Set PMC PTPS register correctly Reviewed-on: https://chromium-review.googlesource.com/183280 (cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad) baytrail: update to version 809 microcode for c0 Reviewed-on: https://chromium-review.googlesource.com/183256 (cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e) baytrail: Add a shared GNVS init function Reviewed-on: https://chromium-review.googlesource.com/183332 (cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c) baytrail: Add basic support for ACPI System Wake Source Reviewed-on: https://chromium-review.googlesource.com/183333 (cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619) baytrail: allow configuration of io hole size Reviewed-on: https://chromium-review.googlesource.com/183269 (cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919) baytrail: add in C0 stepping idenitification support. Reviewed-on: https://chromium-review.googlesource.com/183594 (cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4) baytrail: add option for enabling PS2 mode Reviewed-on: https://chromium-review.googlesource.com/183595 (cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f) rambi: enable PS2 mode for VNN and VCC Reviewed-on: https://chromium-review.googlesource.com/183596 (cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9) baytrail: add config option for disabling slp_x stretching Reviewed-on: https://chromium-review.googlesource.com/183587 (cherry picked from commit f99804c2649bef436644dd300be2a595659ceece) rambi: disable slp_x stretching after sus fail Reviewed-on: https://chromium-review.googlesource.com/183588 (cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880) baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI Reviewed-on: https://chromium-review.googlesource.com/183597 (cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906) rambi: fix trackpad and touchscreen wake sources Reviewed-on: https://chromium-review.googlesource.com/183598 (cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5) baytrail: Add support for LPE device in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184006 (cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f) rambi: Add LPE GPIOs for Jack/Mic detect Reviewed-on: https://chromium-review.googlesource.com/184007 (cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578) rambi: Set TSRx passive threshold to 60C Reviewed-on: https://chromium-review.googlesource.com/184008 (cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee) baytrail: DPTF: Add PPCC object for power limit information Reviewed-on: https://chromium-review.googlesource.com/184158 (cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b) baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant Reviewed-on: https://chromium-review.googlesource.com/184442 (cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd) rambi: Move the CPU passive/critical threshold config to DPTF Reviewed-on: https://chromium-review.googlesource.com/184443 (cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac) baytrail: Fix XHCI controller reset on resume Reviewed-on: https://chromium-review.googlesource.com/184500 (cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd) baytrail: update lpe audio firmware location Reviewed-on: https://chromium-review.googlesource.com/184481 (cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6) rambi: Put LPSS devices in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184530 (cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1) baytrail: initialize HDA device and HDMI codec Reviewed-on: https://chromium-review.googlesource.com/184710 (cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961) baytrail: provide GPIO_ACPI_WAKE configuration Reviewed-on: https://chromium-review.googlesource.com/184718 (cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b) rambi: configure wake pins as just wake sources Reviewed-on: https://chromium-review.googlesource.com/184719 (cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115) baytrail: I2C: Add config data to ACPI Device Reviewed-on: https://chromium-review.googlesource.com/184922 (cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8) Squashed 28 commits for rambi and baytrail. Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-18slippy: remove FUI supportRonald G. Minnich
There's no reason to keep maintaining support on this mainboard, since nobody has one. Change-Id: I5c7c8ea4640170ba231fec82a94a54ee1876b845 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/180503 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit e291d82acbc8bf0d1372e11ac100a7dd340a0040) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6913 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-17spi: add Kconfig variable for dual-output read enableDavid Hendricks
Add a Kconfig variable so that driver code knows whether or not to use dual-output reads. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5 Reviewed-on: https://chromium-review.googlesource.com/177834 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit de6869a3350041c6823427787971efc9fcf469b8) tegra124: implement x2 mode for SPI transfers on CBFS media This implements x2 mode when reading CBFS media over SPI. In theory this effectively doubles our throughput, though the initial results were almost negligibly better. Using a logic analyzer we see a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we want to see further gains here then we'll probably need to tune AHB arbitration and utilization to eliminate bubbles/stalls when copying from APB DMA. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e Reviewed-on: https://chromium-review.googlesource.com/177835 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 29289223362b12e84da5cbb130f285c6b9d314cc) nyan: turn on dual-output reads for SPI flash Nyan's SPI chip is capable of dual-output reads, so let's use it. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df Reviewed-on: https://chromium-review.googlesource.com/177836 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 62de0889a9cfc5686800645d05e21e272e4beb5c) Squashed three commits to enable dual output spi reads for nyan. Also fixed the spi_xfer interface that has been updated to use bytes instead of bits. Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6909 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-17pnp: Allow setting of misc register 0xf4 in device treeStefan Reinauer
Change-Id: I602f970e0ee2fd634a74fd4c25358c2e78ca58f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/179536 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 02b0583e632f1ba53557f8cfe4293ad4ed29ff4d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6910 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-15exynos5250: Fix PMU register address mapJulius Werner
Patch 12b121f3fef61d introduced an off-by-one error in the offsets of the PMU register struct, which put both the newly added register and the PSHOLD that comes after it in the wrong place. This patch corrects the offsets (5420 had already been correct). Change-Id: I1d9d31a6a73ee91890824e94fbd247d5feb4f6ae Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179411 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5fdc74bc18bcb1066a0ce3ba94829af1b175173b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-15arm: Remove CAR_MIGRATE Kconfig and associated cruftJulius Werner
This is essentially a revert of commit 10bd772d. The CAR_MIGRATE mechanism is only useful to migrate variables from a special region (e.g. cache as RAM) into DRAM-backed CBMEM between different parts of the romstage (it does not persist into ramstage). Since ARM devices use SRAM for which there is no reason to become inaccessible in later parts of the romstage, this mechanism isn't useful for them. Removing it makes the romstage.ld script much simpler, which has the nice side-effect of putting the BSS at the end of the memory image (so that cbfstool can actually figure out that it doesn't need to be part of the ROM image). Old-Change-Id: I50e91d8bd51b5deb19446d9da48699edecbef6ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176761 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ebfd698e57c902e2f39a0cfc1bc2b02665e47ec6) console: Make cbmem depend on x86. The cbmem implementation isn't supported on anything other than x86 right now and actually causes memory corruption on ARM machines. Until that's fixed, this will prevent people from turning it on and causing hard to track down errors. Old-Change-Id: I00e8aacf008acfe2f76d4eab82570f7c1cc89cab Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/191107 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e54f16e346a7f2c66d802fb78a6b24e53b732b83) Squashed two related commits for cbmem support on arm. Change-Id: I2be48cea348ee5dc8ca3632d743500aa111bab08 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6888 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-09-14payloads/external/SeaBIOS: Bump version to 1.7.5Edward O'Callaghan
Change-Id: Ie4b58b739ea411035b1801348e3e73e607299846 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6900 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-09-14cbmemc: Bump default to 128KVladimir Serbinenko
board_status shows that truncation of few KiB is pretty common. So bump this value. Change-Id: I78a16974846a59ee4eae782380e6d01d2fa324f2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6902 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.Vladimir Serbinenko
X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash but address map limits this to 16MiB. Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13intel/gma: consolidate vbt codeVladimir Serbinenko
Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6800 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13arm: Move exception_init() close to console_init()Julius Werner
This patch adds stub implementations of exception_init() to all archs so that it can be called from src/lib/hardwaremain.c. It also moves/adds all other invocations of exception_init() (which needs to be rerun in every stage) close to console_init(), in the hopes that it will be less likely overlooked when creating future boards. Also added (an ineffective) one to the armv4 bootblock implementations for consistency and in case we want to implement it later. Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176764 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2960623f4a59d841a13793ee906db8d1b1c16c5d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6884 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-09-13arm: Put exception_stack into BSSJulius Werner
"Hey guys, I have this awesome idea! How about we put a huge array filled with 0xa5 into the data segment of our uncompressed romstage for no particular reason? Give our SPI driver something to do so it doesn't get too bored, you know?" Guess it pays off to just hexdump our image and sanity-check it top to bottom every once in a while... Also reduces the size because 8K is crazy just to print a bunch of registers (256 bytes ought to be enough for anybody). Old-Change-Id: Icec0a711a1b5140d2ebcd98338ec638a4b6262fa Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176762 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 61c360a1c3f445535c9ff383a389e643cfe4527c) arm: Remove exception_test() The exception_test() mechanism might have been useful when exceptions were first implemented, but now that they are pretty stable it's really not necessary anymore (especially not on every single boot in production Chromebooks). It forces a simple unaligned access, and as we start having exceptions in stages that might not have paging turned on yet, it's better to remove that completely. Also removed the duplicated implementations of SCTLR-stuff and switched to the existing ones in cache.h. Old-Change-Id: I85e66269f5e2f2dfd3e8aaaa18441493514b62f8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177101 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d0706b848572fbea26e0e432ec5827503b9603c9) Squashed 2 exception related commits. Change-Id: Id2c115ee39a0732c375472afc0194436e2f5e069 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-13tegra124/nyan: display, clock, and other updatesJulius Werner
tegra124: Set Tx FIFO threshold value to recommended setting Reviewed-on: https://chromium-review.googlesource.com/175200 (cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad) tegra124: add CLK_X definitions Reviewed-on: https://chromium-review.googlesource.com/175220 (cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d) tegra124: fix incorrect struct member in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/175270 (cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c) tegra124: add the _x clocks to clock_enable_clear_reset Reviewed-on: https://chromium-review.googlesource.com/175539 (cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5) tegra124: add clock support code for graphics. Reviewed-on: https://chromium-review.googlesource.com/175162 (cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819) tegra124: Clean up some #defines for DMA Reviewed-on: https://chromium-review.googlesource.com/175631 (cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9) tegra124: enable flow control for APBDMA in SPI driver Reviewed-on: https://chromium-review.googlesource.com/175630 (cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d) nyan: move clock setup for the display out of dca_init Reviewed-on: https://chromium-review.googlesource.com/175656 (cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc) tegra124: more display PLL setup and clock hardcode removal. Reviewed-on: https://chromium-review.googlesource.com/175732 (cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f) tegra124: move dp.c from tegra to tegra124 Reviewed-on: https://chromium-review.googlesource.com/175830 (cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0) tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb Reviewed-on: https://chromium-review.googlesource.com/175889 (cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484) tegra: get rid of struct members that are not used Reviewed-on: https://chromium-review.googlesource.com/176023 (cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6) tegra124: Increase SCLK (AVP) to 300MHz Reviewed-on: https://chromium-review.googlesource.com/175489 (cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552) tegra124: Address old main CPU starting review feedback. Reviewed-on: https://chromium-review.googlesource.com/175933 (cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd) tegra124: Revise clock source configuration for irregular peripherals. Reviewed-on: https://chromium-review.googlesource.com/176109 (cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99) nyan: add timestamps in romstage Reviewed-on: https://chromium-review.googlesource.com/176172 (cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935) tegra124: Allow enabling clock output for external peripherals. Reviewed-on: https://chromium-review.googlesource.com/176108 (cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed) nyan: Enable and configure clocks for I2S and audio codec. Reviewed-on: https://chromium-review.googlesource.com/176104 (cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4) tegra124: Fix typo in pinmux name. Reviewed-on: https://chromium-review.googlesource.com/176215 (cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34) nyan: Add pinmux settings for audio peripherals. Reviewed-on: https://chromium-review.googlesource.com/176212 (cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c) nyan: De-array-ify the PMIC setup code. Reviewed-on: https://chromium-review.googlesource.com/176903 (cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247) nyan: Add a kconfig for building for the original nyans in pixel cases. Reviewed-on: https://chromium-review.googlesource.com/176904 (cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed) nyan: Set the CPU voltage differently depending on which PMIC is in use. Reviewed-on: https://chromium-review.googlesource.com/176905 (cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc) nyan: Increase the CPU voltage to 1.2V. Reviewed-on: https://chromium-review.googlesource.com/176906 (cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557) tegra124: Flesh out/tidy up the flow controller constants. Reviewed-on: https://chromium-review.googlesource.com/177085 (cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794) tegra124: When leaving the bootblock/AVP, really stop the AVP. Reviewed-on: https://chromium-review.googlesource.com/177086 (cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd) nyan: Set SPI4 speed to 33MHz Reviewed-on: https://chromium-review.googlesource.com/177038 (cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55) nyan: Do console_init() in romstage Reviewed-on: https://chromium-review.googlesource.com/176763 (cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03) nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option. Reviewed-on: https://chromium-review.googlesource.com/177486 (cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba) nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin. Reviewed-on: https://chromium-review.googlesource.com/177487 (cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f) tegra124: Bump up HCLK and PCLK Reviewed-on: https://chromium-review.googlesource.com/177563 (cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405) nyan: Add some code for reading the board ID. Reviewed-on: https://chromium-review.googlesource.com/177488 (cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f) nyan: Use the board ID to decide how to initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/177489 (cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c) nyan: Create kconfig variables for each SDRAM config. Reviewed-on: https://chromium-review.googlesource.com/177580 (cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377) tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line. Reviewed-on: https://chromium-review.googlesource.com/177637 (cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9) tegra124: Initialize the MCR when setting up the UART. Reviewed-on: https://chromium-review.googlesource.com/177638 (cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6) tegra124: fix SPI AHB burst length Reviewed-on: https://chromium-review.googlesource.com/177564 (cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315) tegra124: remove unneeded debug print in SPI code Reviewed-on: https://chromium-review.googlesource.com/177833 (cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06) nyan: Set up the SOC and TPM reset pin. Reviewed-on: https://chromium-review.googlesource.com/177965 (cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a) tegra124: Allow some time for packets to appear in Rx FIFO Reviewed-on: https://chromium-review.googlesource.com/177832 (cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84) nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722 Reviewed-on: https://chromium-review.googlesource.com/178226 (cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a) nyan: change devicetree for the new display settings. Reviewed-on: https://chromium-review.googlesource.com/177958 (cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d) nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs Reviewed-on: https://chromium-review.googlesource.com/178914 (cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242) Tegra124: nyan: Disable VPR Reviewed-on: https://chromium-review.googlesource.com/179327 (cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d) tegra124: norrin: fix display issue Reviewed-on: https://chromium-review.googlesource.com/179745 (cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb) tegra124: Add iRAM layout information. Reviewed-on: https://chromium-review.googlesource.com/179814 (cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa) tegra124: Run bootblock and ROM stage out of DRAM. Reviewed-on: https://chromium-review.googlesource.com/179822 (cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce) nyan: clean up a comment regarding video Reviewed-on: https://chromium-review.googlesource.com/180161 (cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447) tegra124: norrin: the first step to clean up display code Reviewed-on: https://chromium-review.googlesource.com/180135 (cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d) Squashed 49 commits for tegra124/nyan. Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-13azalia: Shrink boilerplateVladimir Serbinenko
Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-12mainboard/lenovo/t530: Enable PCIe Bridge for discrete graphicsEdward O'Callaghan
Change-Id: I80f1e27268d0be58514d110611fd3c18cbe81829 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6895 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins)
2014-09-12mainboard/lenovo/t530: Make cdrom drive work by fixing devicetreeEdward O'Callaghan
Change-Id: I804aff0fa53609e5fc70301053f075aa54b9bde5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6893 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-09-12payloads/external/SeaBIOS: Allow setting buffers below 0xC0000Martin Roth
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-12arm: Remove some pointless CFLAGSJulius Werner
This patch removes the -ffixed-r8 CFLAG from the coreboot and libpayload Makefiles. This seems to be a relic from U-Boot, which uses that register to keep it's global data structure pointer. There's no reason for us to throw away a perfectly fine register on this already pretty constrained architecture. Also removed a config.h inclusion from the Makefile because that should really be done inside the C files. Change-Id: Ia176c0f323c1be07cddf88fa5488788786a27cdf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177110 Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2a81112abde284ba09020db6afa363169911a7f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6880 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-12stack check: cosmeticsStefan Reinauer
Print a space after a full stop. Change-Id: Ic7d0522ae35079b64ce61956d06ea59843ef9d80 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/176756 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit c7ff63038b6888b17a96783b1169c5f335022b24) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6878 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-12lenovo/t530: Enable wake on LID and Fn keyEdward O'Callaghan
Change-Id: I09a8fe94b33c3cc1da62f7a5a527944638bd6f0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6877 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-09-12lenovo/t530: Apply ME workaround for S3 resumeEdward O'Callaghan
Upon S3 resume, the machine powers off due to the ME not being awake yet. Change-Id: I0255dd0fa6b4cb3b539e11a69a618c770c44f4b0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6876 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-09-12tegra124/nyan: various fixes and additionsHung-Te Lin
Tegra124: SDMMC: Configure base clock frequency. Reviewed-on: https://chromium-review.googlesource.com/173841 (cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6) Tegra124: SDMMC: Configure pinmux for MMC 3/4. Reviewed-on: https://chromium-review.googlesource.com/174011 (cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b) tegra124: Move DMA-related #defines and definitions to header Reviewed-on: https://chromium-review.googlesource.com/174444 (cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3) tegra124: Assign console address for kernel. Reviewed-on: https://chromium-review.googlesource.com/174486 (cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c) nyan: Fix up the gpio indices in chromeos.c. Reviewed-on: https://chromium-review.googlesource.com/174418 (cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61) Nyan: turn on the backlight. Reviewed-on: https://chromium-review.googlesource.com/174533 (cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215) tegra124: Fix the disp1 source field. Reviewed-on: https://chromium-review.googlesource.com/174701 (cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0) nyan: set up the aux channel i2c interface Reviewed-on: https://chromium-review.googlesource.com/174620 (cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e) tegra124: fix typos in the clock code. Reviewed-on: https://chromium-review.googlesource.com/174684 (cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02) tegra124: Revamp clock source/divisor configuration Reviewed-on: https://chromium-review.googlesource.com/174804 (cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809) tegra: Add gpio_output_open_drain() function Reviewed-on: https://chromium-review.googlesource.com/174650 (cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c) tegra124: add nvidia-generated files Reviewed-on: https://chromium-review.googlesource.com/174610 (cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652) nyan: Ignore the dev mode GPIO. Reviewed-on: https://chromium-review.googlesource.com/174837 (cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee) Tegra124: Add support for the ARM architectural timer. Reviewed-on: https://chromium-review.googlesource.com/174835 (cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c) nyan: Initialize the ARM architectural timer in the RAM stage. Reviewed-on: https://chromium-review.googlesource.com/174836 (cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8) tegra124: nyan: Move mainboard level clock stuff into the mainboard source. Reviewed-on: https://chromium-review.googlesource.com/174843 (cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a) tegra124: add some explanatory text about U7.1 computations. Reviewed-on: https://chromium-review.googlesource.com/173910 (cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413) Set the EC SPI clock source to PLLP and divide down to around 5MHz Reviewed-on: https://chromium-review.googlesource.com/173954 (cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74) nyan: Move non-essential configuration out of bootblock and into ram stage. Reviewed-on: https://chromium-review.googlesource.com/174844 (cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397) tegra124: clocks: Save some IOs in clock_enable_clear_reset. Reviewed-on: https://chromium-review.googlesource.com/174845 (cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4) tegra124: re-write SPI driver w/ full duplex support Reviewed-on: https://chromium-review.googlesource.com/174446 (cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54) tegra124: move SPI-related structures from .c to .h Reviewed-on: https://chromium-review.googlesource.com/174637 (cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058) tegra124: add frame header info to SPI channel struct Reviewed-on: https://chromium-review.googlesource.com/174638 (cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f) tegra124: re-factor tegra_spi_init() Reviewed-on: https://chromium-review.googlesource.com/174639 (cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e) nyan: Set CrOS EC frame header parameters for SPI Reviewed-on: https://chromium-review.googlesource.com/174710 (cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233) tegra124: Add Rx frame header support to SPI code Reviewed-on: https://chromium-review.googlesource.com/174711 (cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832) tegra124: add support for the Serial Output Resource (sor) Reviewed-on: https://chromium-review.googlesource.com/174612 (cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9) nyan: tegra124: Enable I, D and L2 caches in romstage. Reviewed-on: https://chromium-review.googlesource.com/173777 (cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007) tegra and tegra124: Bring up graphics Reviewed-on: https://chromium-review.googlesource.com/174613 (cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8) nyan: Move the DMA memory region. Reviewed-on: https://chromium-review.googlesource.com/174953 (cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb) tegra124: Increase CBFS cache buffer size Reviewed-on: https://chromium-review.googlesource.com/174950 (cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026) tegra124: Add USB PLL, PHY and EHCI setup code Reviewed-on: https://chromium-review.googlesource.com/174651 (cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea) tegra124: add in some undocument clock source and PLL registers Reviewed-on: https://chromium-review.googlesource.com/174948 (cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a) tegra124: small cleanups of the code Reviewed-on: https://chromium-review.googlesource.com/174995 (cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda) Squashed 34 commits for tegra124 / nyan support. Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6870 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-09-12panther: update chromeos.cIsaac Christensen
The google mainboards were updated to unconditionally include chromeos.c except for panther. Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6874 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-12cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct commentPaul Menzel
Currently there is no way to enable or disable VMX during runtime using CMOS/NVRAM. It is only possible to configure it during build time by setting the Kconfig option `CONFIG_ENABLE_VMX`. So update the comment accordingly. Change-Id: I4e3294cb39a40cf30d294fd566bc97420592262f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6228 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-12sch: make separate copy of nvs.hVladimir Serbinenko
Change-Id: Ie3a843a76ebf9f5d825e14c4359fb3ecaa052e38 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-12lenovo/t530: Use native LVDS gfx initEdward O'Callaghan
As introduced in: 1783a3c ivybridge: LVDS gfx init. The panel on the T530 is a AUO B156HW01 V.4, 40 pin LVDS (2 ch, 6-bit). Tx parameters derived from datasheet table. Change-Id: I2e3b56a2a3d1ede08a704b839cc11fe6d685cf5b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6395 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-09-12lenovo/t530: Use native raminit over MRC blobEdward O'Callaghan
We now have Native raminit for both sandy/ivybridge introduced in: 7686a56 sandy/ivybridge: Native raminit. Let us make good use of this support over using the Intel MRC blob to initialise memory. USB RCBA configuration data taken between base of 0x3500 up to 0x3600 from `inteltool -r`. Remark: Note the current port is poorly tested at the moment and I am the sole maintainer, however one less blob invites more interest for better support. More to come hopefully. Change-Id: I41d0ef8303dfd369c5565b823e68a6bee09c44f5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6394 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-09-12lenovo/t530: Remove empty mainboard.aslEdward O'Callaghan
Change-Id: Iaccaf5246e7ac5da2b51dd915c3f3ef807fc6467 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6875 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-09-12ec/lenovo/h8: return correctly typed package if battery is absentVladimir Serbinenko
Fixes "Discharge rate invalid message" and fwts error. Change-Id: I51f9d819f164552567d75f83c95ba7523e97343e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6793 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-11pnp: Allow setting of misc register 0xfa in device treeStefan Reinauer
Change-Id: I45885905f0adaa8f0ad9137d7034e6f7a0dc43de Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/175356 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 7fe642543a8de249e13c3d63c3302a20910c247d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6859 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-11tegra124/nyan: rougly stable code baseGabe Black
nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-11Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko
Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6802 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-09-11mainboard/google/parrot: fix ACPI interrupt storm on lid switch changeAndrew Litt
This fixes the ACPI interrupt storm on Parrot that happens when closing the lid or entering suspend by lid close (seen in /sys/firmware/acpi/interrupts/gpe1F). This patch inverts the interrupt trigger level every time the interrupt is received so that it doesn't fire until the next state change. http://askubuntu.com/questions/310196 is a good example of what this is trying to solve. Change-Id: I8b095914e9330c3217a4ceb058613fa952f4a234 Signed-off-by: Andrew Litt <ajlitt@splunge.net> Reviewed-on: http://review.coreboot.org/6858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-11Increase space for ACPI tables when using dynamic CBMEMStefan Reinauer
Unlike in old style CBMEM, dynamic CBMEM does not have a hand-calculated, hard-coded size, so allow up to 144K of space for ACPI tables. Change-Id: Id9dd7447c46d5fe7ed581be753d70e59add05320 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/6795 Tested-by: build bot (Jenkins) Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-11roda/rk886ex: Move dummy DCC ON# to finalize stageStefan Reinauer
During Vladimir's ACPI cleanups, this was moved into the mainboard's enable stage, which will prevent the VGA option rom from executing correctly. Move it to the finalize stage to make sure it runs after all initialize functions have been called. Change-Id: I0fcca4d4a95f89382f377ce923f82ecb71467fd8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/6845 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-09-10tegra124: Make tegra124 compilable with serial turned off.Gabe Black
The bootblock and romstage UART consoles were being built in based only on whether or not the bootblock and romstage consoles were selected, ignoring whether serial console support was compiled in generally. Change-Id: I3866519c422a990c44ced66885108eff24894563 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172580 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a4f2dd4902a05884693e6e350b6be29276d16981) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10nyan: Use the new pinmux functions as part of UART setup.Gabe Black
The pins for the UART had been configured manually using hardcoded offsets and values. Now that we have pinmux functions for that sort of thing, we should use that instead. This also provides a very simple test for the pinmux code. Ultimately this code should be wrapped in a function which handles setting up any of the UARTs which is appropriately parameterized and which would be called from the bootblock main instead of being in it, but for now this is sufficient. Old-Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171807 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d29e655b68143e86199ab1d74f89e125b16b67cc) tegra124: Call the set_avp_clock_to_clkm function in the bootblock. We had a hardcoded version of the set_avp_clock_to_clkm function in the bootblock, and we had to use it until now because the real version uses udelay, and until now that hadn't been implemented. Also, replace the delay loop in the hacky_hardcoded_uart_setup_function with a call to the real thing. Old-Change-Id: I6df9421bcad484e0855c67649683d474d78e4883 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4c6dd4c7cade7d922a258e0371e43972bce77249) Squashed two tegra124 bootblock related commits. Change-Id: I0ce6321a04b11b7f1250ef3816fe46732777988d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6861 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-10Exynos5420: Fix up the i2c driver for use with the TPM driverGabe Black
The TPM driver expects to call i2c_read with zero address length. The i2c driver wasn't prepared to handle that particularly in the case of reads because it expected to send an address before switching over to read mode for the data. This change also fixes up the read and write calls to consistently be read32 and write32 instead of readl and writel. Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/175966 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cf686269424ea938d6f953d0f76103182eb71297) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10samus: Fix 8GB SPDDuncan Laurie
The 8GB variant is x16 with 11 column bits and 4Gb density. Change-Id: I3aa647aba88dbc928fefd826cbd01e4fa8273660 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d18462f6fc0d40328e9619525240778ea6b1a426) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6856 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10tpm: Clean up I2C TPM driverStefan Reinauer
Drop a lot of u-boot-isms and share common TIS API between I2C driver and LPC driver. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e Reviewed-on: https://chromium-review.googlesource.com/175670 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3fc8515b9dcef66998658e1aa5c020d22509810c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6855 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10samus: GPIO updates for Proto1bDuncan Laurie
Move NFC_INT to GPIO9 Swap CODEC_INT to GPIO46 and WLAN_DISABLE_L to GPIO42 Swap ACCEL_INT to GPIO45 and PP1800_CODEC_EN to GPIO43 Enable PP1800_CODEC_EN, CODEC_LDOENA, CODEC_RESET_L Old-Change-Id: I5547d34f1b7953808375aa5fe5e0a9640ae7e05e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5bb4bc59e37ee4fe9a0556e08a53402c822e5bd6) samus: Misc fixes from proto1b bringup - NFC interrupt is expected in the kernel as a GPIO now, so set it back to that type - NFC FW update GPIO should be low - Accel/Codec interrupts were still set as GPIO type, they should be set as PIRQ type Old-Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 75a0944f320c80618f12732a23344ce40010a688) Squashed two small patches for samus. Change-Id: I7ec56191fe2b7f19e470df175ad0bbe320a442f5 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10nyan: Add a stub mainboard.Gabe Black
Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170837 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea) nyan: Add a "special-class" for aggregating BCT files into bct.cfg. The config file which cbootimage processes to create a BCT could come from multiple different files, individually selected based on config options, and/or split up into different files for organizational purposes. This change adds a special-class which collects those files and concatenates them all together in a bct.cfg which can be processed more easily by other parts of the build. While the BCT files themselves are potentially very board specific, for instance ones that hold memory timing information, this bit of code which collects them is not. It has to be in each board file instead of alongside the CPU, however, to ensure that the special class is set up before another Makefile tries to use it. If we end up with lots of Tegra based boards which duplicate this code over and over, we might want to revisit how this works. Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170922 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a) nyan: Add bct files for nyan. There's a config option which selects between the emmc and spi config files depending on what the firmware is intended to boot from. These are copied from the files installed by the tegra-bct-nyan ebuild, except that the spi config file has been modified so that there's only one copy of the BCT and so that it only has one configuration. This is to save space in the final image. Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170923 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0) Squashed three commits required to get nyan building since some patches were out of order. Added a select to the nyan mainboard Kconfig to have a rom size of 1024K to match the saved config on the chromium side. Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6669 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-10nvidia-cbootimage: integrate into coreboot makeIsaac Christensen
Add rules for building the nvidia-cbootimage utility and add dependencies to the tegra124 platform. Change-Id: Ia9f26981bccd217fe79e1b5dd432ee7da868d22a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6851 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-10lenovo/t520/acpi/gpe.asl: fix ExpressCard gpe configExpreNicolas Reinecke
ExpressCard is connected to PCIe port 4. Change-Id: I0cffabd9d9435d24a7e9c178c2f96fb1a9390320 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-10lenovo/t520/hda_verb.h: update azalia codec configNicolas Reinecke
Replace codec config copied form T530 with dumped values from T520 /sys/class/sound/card0/hdaudioC0D0/init_pin_configs. Intel Azalia HDMI is always enabled, but DP isn't connected to a connector. Change-Id: Iabdae4a6669ff429d5769a1bb0c0fb1abc12ba82 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6849 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-09-10lenovo/t520/gpio.h: Fix current gpio configurationNicolas Reinecke
Change-Id: I67f321583211efd9ed917276cc3989c6dc4ac649 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6848 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-09-09arm: Update a stale comment in bootblock .S filesDavid Hendricks
This just updates a comment which refers to "board_init_f". We use bootblock main() in coreboot. Change-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0 Reviewed-on: https://chromium-review.googlesource.com/172095 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 65139f29682cedca8dfb58b3dfe67eab64299064) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6791 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-09-09exynos: Install the BL1 and set the checksum in the Makefile.Gabe Black
Install the BL1 and set up the checksum in the Makefile instead of relying on post processing. Import the exynos checksum script, split it in two and simplify it significantly. Stop putting the CBFS header in the midst of the bootblock so that it can be checksummed before CBFS is put together. Stop saving space for it and leaving an anchor in the bootblock which nobody looks for. Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179229 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-09ARMv4: Add a minimal version of cpu.h.Gabe Black
All this version does is define asmlinkage to be nothing. It's required by the threading header file which is brought in by the timer implementation which I think is the hook for thread switching. Change-Id: Id57261d7c2c5ff8be00b0ad71bf7aaa9f3e24c1d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171801 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e00379f54802066fd3e0685b291cdec289078055) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-09tegra124: Switch the bootblock over the ARMv4 impelementation.Gabe Black
The bootblock for the tegra124 runs on the AVP coprocessor which uses the ARMv4 architecture. Switch it over to that architecture. Change-Id: Ie527bbff938e6148c58727d448f9c2e6862da872 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171402 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c1aa76b7607ee40ff848628971a97eea5393aebe) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6784 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-09-09ARM: Add an ARMv4 architecture version.Gabe Black
This is needed for the tegra124's bootblock and includes enough implementation to support that use. No caching is supported, although there are function prototypes and stub implementations to satisfy includes and linking. Change-Id: Ib79dde8c30eda98b3e823cba2ff6115a610bb2e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171401 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 221dc76b3ce4c1d73851c432333e091e1c60f0cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-09getac/p470: Add some more board info dataPatrick Georgi
Change-Id: I7cf47a16928436734df29af951f987db9cf9530d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-08Haswell/falco/peppy/slippy: continue to clean up FUI.Ronald G. Minnich
As a first step towards removing hardcodes from the FUI support, change the haswell call to i915_lightup to panel_lightup, and pass the intel_dp * as a parameter. Get rid of the scalar arguments and make them part of intel_dp. Get rid of file-scope variables and use the ones in the intel_dp struct. In falco, use functions that peppy uses. Drop slippy support for FUI, it's a dead board; if this is ok I'll remove the files next. And, incidentally, fix the broken RGBX constant and change it to BGRX. Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174932 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6833 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-09-08FALCO: stop using the slippy graphics codeRonald G. Minnich
It's time to start cleaning up the falco graphics code, but it needs to have its own files, not slippy's. Change-Id: I7dbe27eafbf247b5c7806819bf0059d8b10e842c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172501 Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 262a0c16a39871d14972a92bff2dbc24de2ca3f0) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Disable SMBus controllerDuncan Laurie
Nothing is connected to this port. Change-Id: If3e466a3053fa694a511c2335c16381f77f56f47 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174089 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5ddb6a444d5c3141868eaf618ecb014b0262a796) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6827 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-08tegra124: return the UART base address based on indexIsaac Christensen
Change-Id: I73a8e56559c7ffdaab39a5c19311221c91565004 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Tweaks from bringupDuncan Laurie
- GPIO29 is no longer connected so we don't need the SMI workaround on the entry to sleep states. - Disable touchscreen wake source until the kernel driver is working so it does not wake immediately. - Update a few GPIOs and disable the codec for now as it is leaking into the 1.8V DDR rail. Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Fix up memory SPD informationDuncan Laurie
The LPDDR3 memory is x32 and dual rank with 14 row bits. In addition the memory is actually elpida, even though they are owned by micron it is confusing to label it as such. And the ram strap options were inverted from what I expected so the memory table needs to be updated. Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6828 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08samus: Add onboard device configurationDuncan Laurie
Change-Id: Ib7b6688982e9f74cffe40d11d4a9ec69acd55d37 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174088 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 41624b073fb59b1372ee5a8eba3ed64c7e633311) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6826 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-08samus: Change thermal behavior to match other haswell platformsDuncan Laurie
Change-Id: Ia835f16b156949f1841210c4a469223d5df28a54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174087 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8e51d1d74cdcadde9cbf10e8321d601b099c46bc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08ARM: Generalize armv7 as arm.Gabe Black
There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2014-09-05Implement ACPI in a per device wayVladimir Serbinenko
This approach avoids having same basic tables 150-lines mantra over 100 times in codebase. Change-Id: I76fb2fbcb9ca0654f2e5fd5d90bd62392165777c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6801 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-05Consolidate intel vga int15 hooksVladimir Serbinenko
Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05i82801gx: Kill unused TCG and SMI1Vladimir Serbinenko
SMI1 is being written to but never read from. Change-Id: I82c0800713e3093eb1317b5e1f6f228771134857 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6808 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05roda/rk886ex: Move device changes to mainboard code from acpi tables codeVladimir Serbinenko
Change-Id: I3d694e5b3092d78bce89f6baa7b2dedffddf3012 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05azalia: Use convenience macros throughoutVladimir Serbinenko
Change-Id: Ic044bf155bfcf93fa7cf3afd7287b7d0b615ef6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-05azalia: Change specific PIN_CFGs to generic AZALIA_PIN_CFGVladimir Serbinenko
Change-Id: I3463d0c283793547b00a7628f27f2f1777c21238 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 10:37:28 +0000