summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-09-16soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC levelSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from specific mainboard (brya) to ensure all Alder Lake mainboards can make use of common TCSS block. BUG=b:187385592 TEST=Type-C pendrive/Gen-2 SSD detected as Super speed. Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16mb/intel/adlrvp: Override Type-C IOM GPIO Pads based on Board IDSubrata Banik
This patch allows ADL-RVP mainboards to set AUX GPIO PADs based on the board id value. Various ADL-P and ADL-M RVPs SKUs demand different GPIO AUX programming hence, this patch implements a helper function inside `adlrvp` mainboard to override devicetree chip config. Note: Different ADL-P/M SKUs (LP4/LP5/DDR4/DDR5) don't have dedicated devicetree for overrides hence, board id is being used for unique SKU identification. Additionally, skip AUX GPIO PAD filling up for Windows SKUs. TEST=Able to override AUX GPIO PADs based on ADL-P RVP board id. Change-Id: I2f0a37c7a8bd69af715551df2a93e6eed89e954a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16soc/intel/common: Make read_pmc_lpm_requirements more clearTim Wawrzynczak
Commit 2eb100dd12 added PMC LPM requirements to the the PEP ACPI objects, but it was not made clear that one of the pointer arguments to the mentioned function is not supposed to be NULL and Coverity complained. Make the intention clear by instead asserting that `info` cannot be NULL. Fixes: Coverity CID 1462119 Change-Id: I9e8862a100d92f4a7ed1826d3970a5110b47f4c4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-16acpi: Generate power resource name instead of default "PRIC"Furquan Shaikh
This change uses a static 8-bit counter in `acpi_device_add_power_res()` to generate the name of power resource object rather using a default name "PRIC". This makes it easier to identify which power resource Linux kernel logs are referring to. If more than 256 power resources are used in the system, then the counter will wrap around to 0. However, 256 seems to be a large enough number for the power resource count. TEST=Verified that Power Resources are named as expected: ``` dmesg | grep ACPI | grep PR [ 0.550921] ACPI: Power Resource [PR00] (on) [ 0.869960] ACPI: Power Resource [PR01] (on) [ 1.013973] ACPI: Power Resource [PR02] (on) ``` No new ACPI errors are seen in dmesg on brya. Change-Id: Ia18f7177b03821ce0f8c989ae5d258f2f83517a5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16soc/qualcomm/common/qup: Add support for QUP common driverRavi Kumar Bokka
copy existing QUP driver from /soc/qualcomm/sc7180 to common folder. This QUP common driver provide QUP configurations, GPI and SE firmware loading and initializations. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I95a0fcf97b3b3a6ed26e62b3084feb4a2369cdc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16mb/google/herobrine: Increase the ROM size to 64 MBShaik Sajida Bhanu
SPI NOR size should match with coreboot ROM size. On QCOM Piglin board SPI NOR size is 64MB and the default coreboot ROM size is 8MB. So, update the coreboot ROM size to match with SPI NOR size. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board and checked basic boot up. Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16mb/google/dedede: Override panel orientation for buggzyTim Wawrzynczak
Buggzy's panel is oriented with its "right" side facing upwards, therefore the firmware screens in depthcharge were incorrectly rotated. This patch changes the orientation of the framebuffer provided by the FSP. BUG=b:194967458 BRANCH=dedede Change-Id: I4a5fbfcfc1c362da1bddd23c7d132416db3691c9 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16soc/intel/common: Add panel_orientation field to common chip configTim Wawrzynczak
When the FSP driver fills out framebuffer information for the coreboot tables, it assumes the orientation is always normal. This patch provides a field for a mainboard to override the panel orientation from the default (LB_FB_ORIENTATION_NORMAL). Later patches will have the FSP driver use this value when filling out framebuffer information. BUG=b:194967458 BRANCH=dedede Change-Id: I559b3d6a076112a1c020ce5e296430d7ccba9ee4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16mb/google/brya/var/redrix: Add privacy screenWisley Chen
Add privacy screen support. BUG=b:198188272 TEST=build and check SSDT Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ied9d9138f68ba45c4d746aed1cd3f828d4ab7fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/57289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-16soc/intel/alderlake: Add igd deviceWisley Chen
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in ssdt. BUG=b:198188272 TEST=emerge-brya coreboot and check ssdt. Change-Id: Id0c50254a8a25b47368e932c99243f4f02250b82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15vboot: Call check_boot_mode before vb2api_fw_phase1Daisuke Nojiri
Currently, check_boot_mode is called after vb2api_fw_phase1, which makes verstage_main exit before reaching check_boot_mode if recovery mode is manually requested. Thus, recovery mode isn't able to test whether VB2_CONTEXT_EC_TRUSTED is set or not. This patch makes verstage_main call check_boot_mode before vb2api_fw_phase1 to fix the issue. BUG=b:180927027, b:187871195 BRANCH=none TEST=build Change-Id: If8524d1513b13fd79320a116a83f6729a820f61f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-15google/trogdor: Fix Mrbland panels to point LEFT_UPJulius Werner
CB:57324 moved panel orientation from panel_serializable_data to the responsibility of the mainboard, but in parallel to that patch we landed support for some new panels on the Trogdor mainboard that should be pointing LEFT_UP. This patch fixes up the panel orientation for those. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I416b6c8804a88b36f723c4690ed78aff928a0f8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2021-09-15mb/google/brya/variants/gimble: update fw_config for next build phaseMark Hsieh
Update audio FW config based on the schematic carbine_adl-p_evt_20210901.pdf BUG=b:199180746 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4f8ee1a97dd92c7aa0131cd0a77b05f851a26b05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57529 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/google/brya/var/felwinter: Add R4/R5 for dmicEric Lai
Based on latest schematic (0903) update the GPIO table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie79ba14859f7fa4ea66a0f0d58287f4515d01baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-15mb/system76/galp5: Add System76 Galago Pro 5Tim Crawford
https://tech-docs.system76.com/models/galp5/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Pop!_OS Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - Discrete/Hybrid graphics - S0ix when a device is attached to the TBT port Change-Id: I0d9052c0b064d4d43812ad837578d4a097149cc8 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15mb/system76/lemp10: Add System76 Lemur Pro 10Tim Crawford
https://tech-docs.system76.com/models/lemp10/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - DIMM slot and onboard RAM - Both M.2 NVMe SSDs - MicroSD card reader - All USB ports - USB-PD - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DP over USB-C output - Internal microphone - Internal speakers - Combined 3.5mm headphone/microphone jack - S0ix suspend* - Booting to Pop!_OS Linux 21.04 and Windows 10 - Flashing with flashrom Not working: - S0ix when a device is attached to the TBT port Change-Id: I15f7a3b6e9af07fcfde9a71d3f4a84ed625159b7 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15soc/broadwell/acpi.c: Fix unresolvable symbol '\DNVS'Matt DeVillier
Fixes: 27c51a0 ("Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"") which reverted the removal of device NVS, but was not boot tested on any Broadwell Chromebooks. It was recently discovered that the DNVS object was not being loaded, due to a weak function setting the size as zero not being defined for the platform/soc. Add the missing overloaded function and required headers. Test: build/boot google/auron variants LULU ans SAMUS, verify touchpad functional and no ACPI errors in kernel boot log. Change-Id: Icd317d117dbb068bb6da80fe56c06c0267c7b2ae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-15mb/google/brya: Add support for romstage GPIO tableTim Wawrzynczak
Some variants may require more complex power sequencing than can be accomodated with just 2 GPIO tables, therefore introduce one in romstage as well. BUG=b:187691798 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7a63a2ee2cd036b9ae5822be9c87d8a026a54922 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-09-15mb/google/brya: Enable USB4 PCIe resources for kanoDavid Wu
Enable USB4 PCIe resources for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iec914db6914116ebc914a2ba9ff67344b202926b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-15soc/intel/block/../tcss: Create enum for TCSS Port0/1/2/3Subrata Banik
Additionally, convert MAX_TYPE_C_PORTS from macro to enum value. Change-Id: I3c596d8a015adc0449b44710c6d517753904ecd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-15brya/gimble: add `get_wifi_sar_cbfs_filename()` in variant.cMark Hsieh
gimble only uses one WiFi SAR table, contained in a file named wifi_sar_0.hex BUG=b:189068477 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ied030b79183cc6f962674260e7a82a7261b317ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/57616 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-15commonlib/cbfs: Fix minor parser edge casesJulius Werner
This patch fixes a few minor CBFS parsing edge cases that could lead to unintended behavior: the CBFS attribute parser could have run into an infinite loop if an attribute's length was (accidentally or maliciously) invalid. A length of 0 would have caused it to read the same attribute over and over again without making forward progress, while a very large length could have caused an overflow that makes it go backwards to find the next attribute. Also, the filename was not guaranteed to be null-terminated which could have resulted in out-of-bounds reads on a few error messages. Finally, clarify the validity guarantees for CBFS header fields offered by cbfs_walk() in the comment explaining cbfs_mdata. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie569786e5bec355b522f6580f53bdd8b16a4d726 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-09-15google/trogdor: add new variant kingoftownKevin Chiu
This patch adds a new variant called kingoftown. it's clamshell only, no FPR, eDP panel. BUG=b:198365759 BRANCH=master TEST=make Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I648664c50dfad11530a854f574f39264158b44e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-14src/soc/intel/jasperlake/spd: Update SPDsTyler Wang
Due to CL:55000 modified MT53E1G32D2NP-046 WT:B settings and CL:56597 add new memory in global_lp4x_mem_parts.json.txt, update SPDs using gen_spd.go for JSL: Modify: 1.MT53E1G32D2NP-046 WT:B(lp4x-spd-5.hex --> lp4x-spd-3.hex) Add: 1.H54G46CYRBX267,lp4x-spd-1.hex 2.H54G56CYRBX247,lp4x-spd-3.hex 3.K4U6E3S4AB-MGCL,lp4x-spd-1.hex 4.K4UBE3D4AB-MGCL,lp4x-spd-3.hex BUG=b:199032134 TEST=emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I45b9275403fc4166fc56ae4c368c7a222141e150 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-14mb/intel/adlrvp_p: Enable TCSS USB ports device pathMeera Ravindranath
TEST=Boot RVP, ensure Type C ports operate correctly. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: Iadc0df2e6e29a5afbcbb7db1ae0be6546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-14mb/up/squared: Undo set primary GPU via FSP optionMaxim Polyakov
This is no longer needed, since now this parameter is already set using the ONBOARD_VGA_IS_PRIMARY config [1]. [1] commit 1a4496e79f21bef12efc8c6748264a8770266a27 Change-Id: I368fa5d13615dc4ee37db596cb6a5eef993fc220 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-14kontron/mal10: Undo set primary GPU via FSP optionMaxim Polyakov
This is no longer needed, since now this parameter is already set using the ONBOARD_VGA_IS_PRIMARY config [1]. [1] commit 1a4496e79f21bef12efc8c6748264a8770266a27 Change-Id: Ie1bd62ecba2155af5c94f043ea7531f32989588f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-14driver/i2c/max98390: add dsm_param_nameWisley Chen
Maxim driver look for "maxim,dsm_param_name" to load dsm parameter file. dsm param file name consist of {dsm_param_file_name} filled in devicetree, {MAINBOARD_VENDOR} and {MAINBOARD_PART_NUMBER}. => {dsm_param_file_name}_{MAINBOARD_VENDOR}_{MAINBOARD_PART_NUMBER}.bin BUG=b:197076844 TEST=build, and check ssdt Change-Id: I006572d6a6ea55298374c688dfd9d877835da82d Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13mb/google/trogdor: Add PANEL_ID to SKU_IDZanxi Chen
In order to distinguish which mipi panel to use, it need to read the PANEL_ID, and combine the PANEL_ID and SKU_ID into a new SKU_ID. BUG=b:197708579,b:191574572,b:198548221 TEST=PANEL_ID should be set correctly. BRANCH=none Change-Id: I018b3f460f9d084d1a3f0dac026f1cd9dde284e2 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-13mb/intel/tglrvp: Enable USB4 resources using SoC KconfigFurquan Shaikh
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` Kconfig to enable USB4 resources and drops the configuration in mainboard. Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13mb/google/volteer: Enable USB4 resources using SoC KconfigFurquan Shaikh
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` Kconfig to enable USB4 resources and drops the configuration in mainboard. Change-Id: Id0951937cab8bf5432fc902ba7af21f56fe98087 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13soc/intel/tgl: Enable USB4 resources based on common KconfigFurquan Shaikh
Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section 7.2.5.1.5 recommends reserving the following resources for each PCIe USB4 root port: - 42 buses - 194 MiB Non-prefetchable memory - 448 MiB Prefetchable memory This change enables reserving of resources for USB4 when mainboard selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES. This is similar to the change for ADL in commit 8d11cdc6fa ("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources"). Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13cbfs: Prevent overflow and infinite loop in cbfs_walkJakub Czapiga
CBFS file with lenth of (UINT32_MAX - cbfs_file.offset + 1) causes overflow, making cbfs_walk() being stuck in an infinite loop, and checking the same file. This patch makes cbfs_walk() skip file headers with incorrect data_offset or data_length. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I70020e347087cbd8134a1a60177fa9eef63fb7bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-13util/kconfig: Add pre-built parserPatrick Georgi
It avoids the dependency on bison/flex, minimally speeds up the build and also works around weird race conditions in some versions of bison that need more investigation. The issue this avoids manifests as a build error when creating parser.tab.c: input in flex scanner failed make: *** [util/kconfig/Makefile.inc:66: build/util/kconfig/parser.tab.c] Error 2 Since the error happens within bison the alternative would be to make bison part of our crossgcc environment to ensure that no broken OS build is used. BUG=b:197515860 TEST=things build with bison not installed Change-Id: Ib35dfb7beafc0a09dc333e962b1e3f33df46a854 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13arch/x86/boot: Add missing includeRaul E Rangel
This file uses the asmlinkage macro. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id5b73c174aa946b8205b4172609729b0548cbd8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13soc/amd/common/block/cpu: Add missing includeRaul E Rangel
We use cpuid_eax to get the cpuid family. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13mb/adlrvp: Add new ADL P board variant for MCHP1727Brandon Breitenstein
Add new board variant to enable MCHP1727 Modular EC Card on RVP BUG=b:179214042 BRANCH=none TEST=emerge brya and verify that adlrvp_p_mchp images boot Change-Id: I9dc96ad5c5db21fedbe480d19fcae8434d3bd169 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56839 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13SMBIOS: Skip `get_smbios_data` for disabled devicesAngel Pons
If a device is disabled, do not call the `get_smbios_data` code. Change-Id: I8960f869e0864f7c82d5fe507f96b62cbd045569 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13SMBIOS: Allow skipping default SMBIOS generationAngel Pons
The call to the `get_smbios_data` device operation is followed by calls to unconditional default functions, which lacks flexibility. Instead, have devices that implement `get_smbios_data` call these default functions as needed. Most `get_smbios_data` implementations are in mainboard code, and are bound to the root device. The default functions only operate with PCI devices because of the `dev->path.type != DEVICE_PATH_PCI` checks, so calling these functions for non-PCI devices is unnecessary. QEMU also implements `get_smbios_data` but binds it to the domain device, which isn't PCI either. Change-Id: Iefbf072b1203d04a98c9d26a30f22cfebe769eb4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13arch/x86/smbios: Add support for large memory capacity in type 16Jingle Hsu
Avoid SMBIOS type 16 Maximum Capacity showing incorrect information when value of maximum capacity exceeds 32 bits by extending the type. Handle 0x0009, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Single-bit ECC Maximum Capacity: 4 TB Error Information Handle: Not Provided Number Of Devices: 6 Tested=On OCP Crater Lake, the SMBIOS type 16 shows expected Maximum Capacity. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: Iaa79cc587808f1eab0a48e2ce1dab089e84e9721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Daocheng Bu <daocheng.bu@intel.com>
2021-09-13spi-generic: Print an error when trying to use a non-existent busJulius Werner
...because I just spent hours chasing a refactoring bug that would have been way more obvious with a little more error transparency in here. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3354ff0370ae79f05e5c37d292ac16d446898606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-13device/dram: Add addtional LPDDR4 speed gradesRob Barnes
Add additonal LPDDR4 speed grades. This is needed because the limited set has casued confusion when the reported speed did not match expectations. There does not seem to be a definitive list of LPDDR4 speed grades, so this list is derieved from JEDEC 209-4C and a survey of commonly used LPDDR4 speed grades. BUG=b:194184950 TEST=Boot, dmidecode -t 17 reports correct speed BRANCH=None Change-Id: Ie7706fd4ad5a7df68c07b8ca43261429ba140c61 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-09-13mb/google/dedede/var/bugzzy: Generate SPD ID for K4U6E3S4AA-MGCRSeunghwan Kim
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. K4U6E3S4AA-MGCR (Samsung) BUG=b:192521391 BRANCH=dedede TEST=Build and boot bugzzy board Change-Id: Ic0b02559c671845a73a71bd57cd7237850c76645 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13mb/prodrive/hermes: Hook up P2SB and PMC in devicetreePatrick Rudolph
Fixes commit bd5b4aa683a634a73a6a63d1f197e2bb74b6a80e "soc/intel/cannonlake: Switch PMC to use device callbacks" as it requires the PCI device 1f.2 to be present in the devicetree. It was missing for this mainboard and caused a boot failure. Change-Id: Iaf508b2d955578efa2a266af50c568f5c0a47aaf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-09-13drivers/analogix/anx7625: prevent video clock jitter on IVO panelsXin Ji
The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz), anx7625 defines K ratio for matching MIPI input video clock and DP output video clock. A bigger k value can match a bigger video data variation. IVO panel has smaller variation than DP CTS spec, so decrease k value to 0x3b. BUG=b:194659777 BRANCH=none TEST=Display is normal on Asurada Change-Id: If3a09811999babda45e9a9a559dd447920109204 Signed-off-by: Xin Ji <xji@analogixsemi.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-11mb/google/brya: Replace white space with tabSubrata Banik
This patch unifies line indentation. Change-Id: Ieeb580057d8abb20afe3a5d73f5f835e6d31c899 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-11mb/google/asurada: fine tune the data lane trail for ANX7625Hung-Te Lin
The ANX7625 display bridge requires customized hs_da_trail time. This patch is based on CB:51433 (commit 6482b16, "mb/google/kukui: fine tune the data lane trail") BUG=b:198558237 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: I0eedb8fa6a1b3dfd9619c7cbf755c9c4071a8484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-09-11mb/google/trogdor: Add mipi panel for mrblandZanxi Chen
Add mipi panel support for mrbland - Setup gpio and modify LCD sequence. - Use the following panel for mrbland: AUO B101UAN08.3 BOE TV101WUM-N53 - Use panel_id to distinguish which mipi panel to use. BUG=b:195516474,b:197300875,b:197300876 BRANCH=none TEST=emerge-strongbad coreboot Change-Id: Ib7cd2da429b114bf6bad5af312044a0f01319b46 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57336 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-11mipi: Make panel init callback work directly on DSI transaction typesJulius Werner
Our MIPI panel initialization framework differentiates between DCS and GENERIC commands, but the exact interpretation of those terms is left to the platform drivers. In practice, the MIPI DSI transaction codes for these are standardized and platforms always need to do the same operation of combining the command length and transfer type into a correct DSI protocol code. This patch factors out the various platform-specific DSI protocol definitions into a single global one and moves the transaction type calculation into the common panel framework. The Qualcomm SC7180 implementation which previously only supported DCS commands is enhanced to (hopefully? untested for now...) also support GENERIC commands. While we're rewriting that whole section also fix some other issues about how exactly long and short commands need to be passed to that hardware which we identified in the meantime. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-10soc/intel/alderlake: Align board type as per FSP v2347_00Ronak Kanabar
This patch adds new board type BOARD_TYPE_ULT_ULX_T4 and changes BOARD_TYPE_SERVER value to 8. BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I48eb0785a209499ee0d90bd541376d9bbacf2390 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-10vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2347_00Ronak Kanabar
The headers added are generated as per FSP v2347_00. Previous FSP version was v2265_01. Changes include: - UserBd UPD description update in FspmUpd.h BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I5e4dd58e5fb1a744b035a4de96986053a02610d3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-10mb/google/guybrush: Invert USB descriptions in devicetreeRob Barnes
The USB descriptions are flipped. Fix by inverting the USB descriptions in devicetree. BUG=None TEST=Build BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I4b33f4de137536c5f3592380da15f6b3a3633bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57538 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10mb/google/guybrush: Document USB mapping in devicetreeRob Barnes
Add a short documenting comment to each usb entry in devicetree so it is clear which function each usb port maps to. BUG=None TEST=Build BRANCH=None Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56725 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10elog: move MAX_EVENT_SIZE to commonlib/bsd/includeRicardo Quesada
Moves MAX_EVENT_SIZE to commonlib/bsd/include, and renames it ELOG_MAX_EVENT_SIZE to give it an "scoped" name. The moving is needed because this defined will be used from util/cbfstool (see next CL in the chain). BUG=b:172210863 TEST=compiles Ok Change-Id: I86b06d257dda5b325a8478a044045b2a63fb1a84 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/common: Delete pep.aslTim Wawrzynczak
After switching to runtime generation of the Intel Power Engine (PEPD) device, this file is no longer required. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2444433f08bfda6f79589a397a2ad2b5a3ecb0ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/skylake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch skylake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7c7cb424278946a9767ea329d18fb03d4e57dce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/common: Add Intel Power Engine support to discoverable PMCTim Wawrzynczak
In order to get rid of pep.asl, skylake also needs to support runtime generation of the Intel Power Engine, therefore add this support to devices that have a discoverable PMC as well. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/elkhartlake: Switch to runtime generation of Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/jasperlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method. soc/intel/jasperlake: Switch to acpigen PEPD Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-10soc/intel/cannonlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch cannonlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-10soc/intel/cannonlake: Switch PMC to use device callbacksTim Wawrzynczak
Now that the PMC device is marked as hidden in devicetrees, the device callbacks can be used instead of BOOT_STATE_INIT_ENTRY callbacks. Note that this moves PMC initialization from BS_DEV_INIT_CHIPS to BS_DEV_ENUMERATE, which aligns with other Intel SoCs. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If292728ad975ba803fed6abea879f6f634470a11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10cannonlake mainboards: Set PMC as hidden in devicetreeTim Wawrzynczak
FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-10soc/intel/tigerlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch tigerlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/tigerlake: Move LPM functions to new fileTim Wawrzynczak
The LPM enable mask is useful to have in more than one place, therefore more the get_disable_mask() function and its helpers to lpm.c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibe83dc106f5f37baf9d5c64f68c47d85ea4e6dd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch alderlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSMTim Wawrzynczak
This patch adds support for the S0ix UUID in the Intel Power Engine _DSM method. This allows the ACPI tables to expose device/IP power states requirements for different system low power states BUG=b:185437326 TEST=Along with following patch on brya0 after resume from s0ix, cat /sys/kernel/debug/pmc_core/substate_requirements Element | S0i2.0 | S0i3.0 | Status | USB2PLL_OFF_STS | Required | Required | Yes | PCIe/USB3.1_Gen2PLL_OFF_STS | Required | Required | Yes | PCIe_Gen3PLL_OFF_STS | Required | Required | Yes | OPIOPLL_OFF_STS | Required | Required | Yes | OCPLL_OFF_STS | Required | Required | Yes | MainPLL_OFF_STS | | Required | | MIPIPLL_OFF_STS | Required | Required | Yes | Fast_XTAL_Osc_OFF_STS | | Required | | AC_Ring_Osc_OFF_STS | Required | Required | Yes | SATAPLL_OFF_STS | Required | Required | Yes | XTAL_USB2PLL_OFF_STS | | Required | Yes | CSME_PG_STS | Required | Required | Yes | SATA_PG_STS | Required | Required | Yes | xHCI_PG_STS | Required | Required | Yes | UFSX2_PG_STS | Required | Required | Yes | OTG_PG_STS | Required | Required | Yes | SPA_PG_STS | Required | Required | Yes | SPB_PG_STS | Required | Required | Yes | SPC_PG_STS | Required | Required | Yes | THC0_PG_STS | Required | Required | Yes | THC1_PG_STS | Required | Required | Yes | GBETSN_PG_STS | Required | Required | Yes | GBE_PG_STS | Required | Required | Yes | LPSS_PG_STS | Required | Required | Yes | ADSP_D3_STS | | Required | Yes | xHCI0_D3_STS | Required | Required | Yes | xDCI1_D3_STS | Required | Required | Yes | IS_D3_STS | Required | Required | Yes | GBE_TSN_D3_STS | Required | Required | Yes | CPU_C10_REQ_STS_0 | Required | Required | Yes | CNVI_REQ_STS_6 | | Required | Yes | ISH_REQ_STS_7 | | Required | Yes | MPHY_Core_DL_REQ_STS_16 | Required | Required | Yes | Break-even_En_REQ_STS_17 | Required | Required | Yes | Auto-demo_En_REQ_STS_18 | Required | Required | Yes | Int_Timer_SS_Wake0_Pol_STS | Required | Required | | Int_Timer_SS_Wake1_Pol_STS | Required | Required | | Int_Timer_SS_Wake2_Pol_STS | Required | Required | | Int_Timer_SS_Wake3_Pol_STS | Required | Required | | Int_Timer_SS_Wake4_Pol_STS | Required | Required | | Int_Timer_SS_Wake5_Pol_STS | Required | Required | | Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56005 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10soc/intel/common/block/acpi: Move pep.asl to acpigenTim Wawrzynczak
There is a use-case for generating the AML bytecode at runtime for the Intel Power Engine device, which comes in a followup patch. BUG=b:185437326 TEST=verified on google/brya and google/dratini by dumping SSDT and verifying the PEPD device matches what was previously in the DSDT: Scope (\_SB.PCI0) { Device (PEPD) { Name (_HID, "INT33A1") Name (_CID, EisaId ("PNP0D80") Method (_DSM, 4, Serialized) { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x63 }) } If ((Local1 == One)) { Return (Package (0x01) { Package (0x03) { \NULL, Zero, Package (0x02) { Zero, Package (0x02) { 0xFF, Zero } } } }) } If ((Local1 == 0x02)){} If ((Local1 == 0x03)){} If ((Local1 == 0x04)){} If ((Local1 == 0x05)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (One) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (One) } If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () } } If ((Local1 == 0x06)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (Zero) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (Zero) } If (CondRefOf (\_SB.PCI0.RGPM)) { \_SB.PCI0.RGPM () } } Return (Buffer (One) { 0x00 }) } Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10acpigen: Add ability to auto-generate _DSM Function 0Tim Wawrzynczak
Since the value returned by _DSM function 0 for a given UUID is trivial to calculate, add the ability to do so to the acpigen_write_dsm() functions. Change-Id: Id9be050442485b42202cf91649aa94e56f35032a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Set LpmStateEnableMask UPDTim Wawrzynczak
Use the get_supported_lpm_states() function to set the respective FSP UPD. TEST=with patchtrain on brya0, /sys/kernel/debug/pmc_core/substate_requirements shows only the substates that are applicable to the design (S0i2.0, S0i3.0). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Add get_adl_cpu_type functionTim Wawrzynczak
This function searches the known MCH device IDs for Alder Lake and returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or unknown. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10mb/google/asurada: enable MIPI_DSI_MODE_LINE_END to fix display issuesHung-Te Lin
The ANX7625 needs explicit LINE_END to output proper display data. This patch is based on CB:51435 (commit b923931, "mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625") BUG=b:198558237 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Id5666fa1bcf96002725509d7436ea1ff5febef93 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57486 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10mb/google/asurada: power on panel after DSI is readyHung-Te Lin
Some bridge chips or panels require DSI signal output before the DSI receiver is ready to work. This patch is based on CB:47380 (commit b32e4d6, "mb/google/kukui: Add panel api after dsi start") BUG=b:198558237 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Id72560caee9352f88db2de7269b1472f56ac1bdf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57485 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-09Revert "soc/amd/common: Skip psp_verstage on S0i3 resume"Karthikeyan Ramasubramanian
This reverts commit b90e6fdd25f7fcc9db6be50a0b117a7509c6fdb1. Latest releases of PSP does not load PSP verstage on S0i3 resume. Hence no need to skip PSP verstage on S0i3 resume. BUG=b:196400450 TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle and then a reboot and ensure that the system boots to OS. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09mb/google/guybrush/var/nipperkin: Add ELAN TS supportKevin Chiu
ELAN TS: eKT3644 BUG=b:194961444 TEST=emerge-guybrush coreboot chromeos-bootimage TS is functional Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Id1601efbbe419bb28233a2678fdde005a55da671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09mb/google/dedede/var/gooey: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Ib458cf47909a2d7a65f086c5f30f85a16f78d589 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitionsFelix Held
Add the pin definitions for the remote GPIOs and the GPIO pin mux values for the GPIO mode of those pins. For now, accessing the remote GPIOs is only supported from the native coreboot code running on the x86 cores and not from verstage on PSP or ACPI. BUG=b:194524995 TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and then toggling that GPIO in an infinite loop in the mainboard's bootblock code results in GPIO 262 toggling as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09soc/amd/common/block/acpi/gpio: add warning for remote GPIO usageFelix Held
Right now the ACPI code doesn't support accessing the remote GPIO block yet, so don't generate invalid remote GPIO access functions and warn about those being unsupported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-09-09soc/amd/common/block/gpio_banks: add remote GPIO supportFelix Held
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't located right after the 4th GPIO bank, but instead at a different location inside the APCIMMIO region. A difference to the first 4 GPIO banks is that the corresponding GPIO MUX registers aren't in a separate bank, but at the end of the remote GPIO region. So this remote GPIO region only supports 48 GPIOs with a 32 bit configuration register each and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the remote GPIO region. For now using the remote GPIOs from verstage on PSP isn't supported. To support this, it would need to map acpimmio_remote_gpio and update the pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a few others. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09wifi: Update deny list entry size to uint16_tSugnan Prabhu S
As per the connectivity document deny list entry size should be uint16 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf Fixes: cc50770cd0("wifi: Add support for wifi time average SAR config") Change-Id: I045c21350cf4c2266df108eede6350d090322ba0 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/kano: Update GPIOs config for kanoDavid Wu
Update the GPIO configuration to match the latest schematic. BUG=b:192370253 BRANCH=None TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I96be95a127f42b005d97a3c02650af13419524a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/primus: update for next build phaseMalik_Hsu
According to the schematic diagram of version C14_MB_20210902A_SB, modify the settings of GPIO and fw_config. BUG=b:197700276 BRANCH=none TEST=emerge-brya coreboot Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I14907faeb631193715b1e0e451e427fb79a68279 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09mb/google/brya/variants/taeko: Add initial fw config for taekoJoey Peng
According to config.star fw mask definition, add initial FW_CONFIG id. BUG=b:194649740 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Cq-Depend: chrome-internal:4072654 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ifef750338d777b76e9710d6bca9a166120db6a0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBMAULIK V VAGHELA
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time. Increasing it over 4 KiB doesn't result in significant improvement, thus keeping the value at 4 KiB as of now. Timing data: Note that before Data is with 1 KiB block size. |------------------------------------------------------| | Stage | Block Size | Before | After | |finished loading body| 4 KiB | 205,187 | 189,947 | |finished loading body| 8 KiB | 205,187 | 188,708 | |finished loading body| 16 KiB | 205,187 | 188,085 | |finished loading body| 32 KiB | 205,187 | 187,793 | |------------------------------------------------------| BUG=b:188577893 BRANCH=None TEST=Boot time for Brya improves by 20 - 25 msec Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09soc/intel/alderlake: Enable Irms UPD for ADLRonak Kanabar
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit is set to non zero. It results VR TDC Input current to be treated as it is root mean square. This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit for TdcEnable UPD. BRANCH=None TEST=Build and boot brya with debug FSP and verify Irms UPD value from logs Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-09-09mb/ocp: Remove superfluous FSP header CPP inclusionArthur Heymans
This is already done in drivers/intel/fsp2_0/Makefile.inc. Change-Id: Idfd15d0a9d2cb15e613881f80bb25c18bd7454bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09intel/xeon_sp/cpx: Hook up public microcode releaseArthur Heymans
Change-Id: I7e575cb17e2004bd931f4fa1d05f17c4cdca29ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-09sb/intel/lynxpoint: Drop `config_t` typedefAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I550198aae22fbe39f4b461332a10de82c78cd191 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57498 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-09sb/intel/lynxpoint/fadt.c: Reuse length fieldsAngel Pons
Compute the bit width of FADT register blocks using their length in bytes, which is readily available from a different field. Change-Id: I4dafa3546714ae46946d6502598e4b945c2a77a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09soc/intel/broadwell: Set FADT `duty_offset` to 0Angel Pons
From ACPI specification, version 6.2 Errata A: A `duty_width` value of 0 indicates that processor duty cycle is not supported and the processor continuously runs at its base frequency. Because Broadwell sets `duty_width` to 0, processor duty cycle is not supported, and the value of `duty_offset` is ignored. For consistency with Lynx Point, set `duty_offset` to 0. Change-Id: I68cb85ec32a6cceda0cea29d76df6c6219b78a40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-09soc/amd/common/block/acpimmio: add remote GPIO bank ACPIMMIO regionFelix Held
Currently coreboot for the AMD SOCs only supports accessing the up to 4 main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne have another GPIO bank in the ACPIMMIO region that can contain up to 48 GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO MUX registers. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-09soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macroFelix Held
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins array that is used for the sb_reset_i2c_peripherals call to bring the I2C buses into a defined state. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09drivers/intel/fsp2_0: Retype loop variable from int to uint32_tAngel Pons
Retype loop variable `i` to `uint32_t` for consistency with the types of the `number_of_phases` and `phase_index` struct fields and the parameter of the `platform_fsp_multi_phase_init_cb()` function. Change-Id: I82916f33c2dc5dab6a31111c9acba2a18a5cfb0b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57491 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08mb/google/dedede/var/magolor: Generate SPD ID for supported partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. MT53E512M32D1NP-046 WT:B BUG=b:199032134 TEST=emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ic9ccee7c0957119a69ee179854cf13d30db40621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08mb/google/dedede/var/cret: Update DPTF parametersDtrain Hsu
Update DPTF parameters from internal thermal team and Intel suggestion. BUG=b:198249129 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I25d3909144d6e38d7a6eb859d33585c319a84b04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-08soc/intel/common: Avoid NULL pointer deferenceJohn Zhao
Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458068, 1458070, 1458971, 1458073, 1458075, 1458076 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ib88fa5f44dd33ad1ad2e763d79438b5c5b78acb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-08soc/amd/cezanne/fsp_m_params: set usb_phy version and length.Julian Schroeder
Setting the usb_phy version and length in the soc code instead of devicetree. That way the devicetree code does not have to reapeat it for different AMD Cezanne based systems. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08mb/google/guybrush/variants/baseboard/devicetree: update usb_phy versionJulian Schroeder
The AMD Cezanne FSP expects a usb phy config structure ID of 0xd 0x6. If the ID does not match, the FSP USB will not set up the phy. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Cq-Depend: chrome-internal:4087511 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08mb/google/brya/var/redrix: Enable SaGv supportWisley Chen
Enable SaGv support for redrix BUG=b:198536984 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I54402dfde5db4106a4e0d891c19592fda39a1099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-08mb/google/dedede/var/cappy2: Add fw_config probe for ALC5682I-VSSunwei Li
Based on commit b9c22e09 (util/sconfig: Compare probe conditions for override device match), add fw_config probe for ALC5682I-VS headphone Audio Codec. BUG=b:197546020 BRANCH=dedede TEST=ALC5682I-VD/VS and CS42l42 work normally according fw_config Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Iac09663b095e758f1bc0cfaf7adb6e84d203788a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57105 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 08:35:49 +0000