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2019-09-22device/pci: Replace add with bitwise-orKyösti Mälkki
Change-Id: I9fbefac3bef7425d6f5ea1bcc01eb21485315c36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-22mb/supermicro/x11ssh: remove unnecessary fsp setting CdClockMichael Niewöhner
CdClock does not need to be set because the board does not use IGD. Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-22soc/intel/skylake: lock down TCO on pch finalizeMichael Niewöhner
Change-Id: I5bd95b3580adc0f4cffa667f8979b7cf08925720 Signed-off-by: Michael Niewöhner <michael.niewoehner@8com.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-09-21soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common fileAndrey Petrov
Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-21mb/ocp/monolake: Implement bank/locator schemeAndrey Petrov
Implement Locator and Bank fields (as reported by dmidecode) to match vendor BIOS. TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches expectation. Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-21soc/fsp_broadwell_de: Use DIMM numbers relative to channelAndrey Petrov
Currently "DIMM numbers" increase monotonically for all the channels. However, commonly DIMMS are numerated on per-channel basis. This change makes numeration match the convention. TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches expectation. Change-Id: I3e7858545471867a0210e1b9ef646529b8e2a31c Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35318 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-21soc/amd/picasso: Use new common SPI codeRichard Spiegel
Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=None, code already tested with grunt. Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21soc/amd/stoneyridge: Use new common SPI codeRichard Spiegel
Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=Build and boot grunt using new SPI code, with debug enabled. Check output. Change-Id: I639973d993316a10daa7564462e689b2c183f536 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21soc/amd/common/block: Create new SPI codeRichard Spiegel
Create a new SPI code that overrides flash operations and uses the SPI controller within the FCH to its fullest. Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public) BUG=b:136595978 TEST=Build and boot grunt using this code, with debug enabled. Check output. Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21drivers/wifi/generic.c: Upper case the AML WiFi name as required by specAndrew McRae
ACPI 6.3, ASL 20.2.2 (Name Objects Encoding) states: LeadNameChar := 'A'-'Z' | '_' NameChar := DigitChar | LeadNameChar Hence, the Intel WiFi names generated in ASL are required to be upper-cased letters. BUG=b:141206986 TEST=Reflash and confirmed SSDT table has correct name. Change-Id: I803b9bc81804eec7bd5220b9dbc6ddd0bb0ecbcc Signed-off-by: Andrew McRae <amcrae@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35466 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-21vboot: extend BOOT_MODE_PCR to SHA256 bank on TPM2Andrey Pronin
With the support of various algorithms and banks in tlcl_extend(), digest_algo parameter of tpm_extend_pcr() started defining the target PCR bank in TPM2 case. The OS expects coreboot to extend the SHA256 bank of BOOT_MODE_PCR. The value that the OS expects coreboot to extend into BOOT_MODE_PCR is the SHA1 digest of mode bits extended to the length of SHA256 digest by appending zero bytes. Thus the correct value for digest_algo passed into tpm_extend_pcr() for BOOT_MODE_PCR is TPM_ALG_SHA256. This didn't matter until adding the support for multiple digest introduced by patches like https://review.coreboot.org/c/coreboot/+/33252, as tlcl_extend always used SHA256 bank before. Change-Id: I834fec24023cd10344cc359117f00fc80c61b80c Signed-off-by: Andrey Pronin <apronin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35476 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20sb/intel/common/fw: Make make aware that it needs binariesNico Huber
As we redirect all `dd` output to /dev/null (it would clutter the console otherwise), there is no error message if a binary to be added isn't found. If we add them as dependency, OTOH, `make` will complain properly. Change-Id: I40c3979b84341cb88c7e9a5084c1a97230ea5503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33327 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mediatek/mt8183: Support more DRAM frequency bootupHuayang Duan
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps. BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-20mediatek/mt8183: Implement the dramc init settingHuayang Duan
This patch implements the dram init setting by replacing the hard-coded init sequence with a series of functions to support calibration for more frequencies. These functions are modified from MediaTek's internal DRAM full calibration source code. BUG=b:80501386 BRANCH=none TEST=1. Kukui boots correctly 2. Stress test (/usr/sbin/memtester 500M) passes on Kukui Change-Id: I756ad37e78cd1384ee0eb97e5e18c5461d73bc7b Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-20mb/supermicro/x11ssh-tf: correct CBFS_SIZEMichael Niewöhner
The specified CBFS_SIZE does not make sense. The boards BIOS region is 0xb00000. Correct the value. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia3014c7fd081030607790ced6bb55323086f1161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35458 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20soc/qualcomm/ipq40xx: Remove unnecessary allocationJacob Garber
The bus variable doesn't live outside the scope of this function, and is only used as a convenient way for passing the pointers to all the sub-functions, so it doesn't need to be allocated. Put it on the stack instead. A similar fix for ipq806x was done in 0f33d8c29a (soc/qualcomm/ipq806x: Remove unnecessary allocation). Change-Id: Ibb1129b92e38a105e100f59e03d107de340b925c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-20nb/intel/nehalem: Enabled VBOOT supportPatrick Rudolph
Tested on Lenovo T410. Change-Id: I86100be79bf2337d65b688edba34b87f3ac18cb6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-20soc/intel/common/intelblocks: Remove PAD_CFG_GPI_GPIO_DRIVER_SCITim Wawrzynczak
Intel's EDS says "1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked." Therefore, the GPI_GPIO_DRIVER_SCI option for pad configuration is meaningless, as any GPE will be masked if the GPIO driver is set as owner. Change-Id: Ia0cd0041dfc985cbe388cb89a4026038c7fb4383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35460 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configurationTim Wawrzynczak
A closer read of the EDS indicates that when GPIO Driver mode is selected, GPIO input event updates are limited to GPI_STS only. GPI_GPE_STS updates are therefore masked, and we don't want to enable this behavior. It masks the GPE and does not allow us to see this GPE as a wake source, obscuring the reason that the system woke up. Also switch the IRQ from level-triggered to edge-triggered, otherwise the system will auto-wake from any sleep state when the pen is ejected from the garage. BUG=b:132981083 BRANCH=none TEST=Wake up system from S0ix using pen eject, verify that mosys eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3 via pen eject, and verify that the wakeup source shows as GPE#8. Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mb/google/hatch: override smbios manufacturer name from CBIWisley Chen
BUG=none TEST=emerge-hatch coreboot, use ectool to write oem name in CBI, and checked smbios manufacturer name. Change-Id: I9be85fbc47031d049b5bd51cfaf6232cab24e9fe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-19sb/intel/ibexpeak: Add define for PRSTS registerAngel Pons
Change-Id: Ia9a6b0c7f2a07796f850acd2349067ba5e5eb735 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-19mb/google/drallion: add sku id base on sensor detectionEric Lai
Implementing logic base on sensor detection to determine SKU id. BUG=b:140472369 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35366 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19mb/google/drallion: Add memory init setup for drallionThejaswani Putta
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-19cpu/intel/common: Extend FSB detection to cover TSCKyösti Mälkki
Use the same CPUID switch block to resolve the multiplier to derive TSC from FSB/BCLK frequency. Do not return 0 as base frequency. Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31340 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/x86/lapic: Refactor timer_fsb()Kyösti Mälkki
Common apic_timer code in cpu/x86 should not depend on intel header files. Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34091 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
To add a common tsc_freq_mhz() implementation, we need to guard againts soc-specific duplicate definitions. Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu,mb,soc: Init missing lb_serial struct fieldsJacob Garber
Initialize the input_hertz and uart_pci_addr fields of the lb_serial struct to prevent later undefined reads in lb_add_serial(). This was done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c: Init new serial struct variables), and this patch finishes the rest. Note that not all of the drivers can have the UART PCI address configured at build time, so a follow-up patch will be needed to correct those ones. Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1354778 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34548 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19src/soc/intel/common/block/cse: Add hmrfpo related functions to cse libSridhar Siricilla
Below new functions are added: * send_hmrfpo_enable_msg() - Sends HMRFPO Enable command to CSE. This API sets ME in SEC_OVERRIDE mode. The mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perfom updates to it. * send_hmrfpo_get_status_msg() - Sends HMRFPO Get Status command to CSE TEST=Verified sending HMRFPO_ENABLE & HMRFPO_GET_STATUS HECI commands on CML RVP & hatch board Change-Id: I559bc4641e12df7ed39b1c97097bf068f9a232db Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-18mb/google/hatch/variants/helios: Add DPTF control for ambient sensorSumeet Pawnikar
Add DPTF based thermal control for ambient sensor for CML based Helios system. Also, update other sensor names information. BUG=b:139335207 BRANCH=None TEST=Build and Boot on Helios board and check all sensor details. Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-18mb/google/hatch/variants/helios: Update DPTF parametersSumeet Pawnikar
Update DPTF thermal temperature threshold values for CML based Helios system. This updates CPU active cooling temperature threshold to appropriate values which addresses the issue of running the Fan at lower CPU temperature as per bug. Also, added active cooling temperature thresholds for other TSR sensors. BUG=b:141087272 BRANCH=None TEST=Build and boot on Helios board to check the fan functionality. Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18cpu/via/nano: Enable TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: Iea51a480fd7c696a6bbccc0b668acdbff6abffb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34203 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18cpu/qemu-x86: Enable TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: I72afb0c0d34157d1d2d9fe4ae6704cd2502f724d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34202 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18x86emu: Drop UDELAY_LAPIC dependencyKyösti Mälkki
It won't build though, since current_time_from() has been removed. Change-Id: I2f7788f626c0504e6354a08b7986e4d18be140a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34201 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/supermicro/x11ssh: drop plus sign/text in nameAngel Pons
There is no board named X11SSH+-TF. Change-Id: Ide01a8d59c09747dfe7d59fd9e17bd5194fb14e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-09-18mb/google/octopus/variants/garg: add LTE sku to config power sequenceKevin Chiu
Add SKU#18 to config power sequence below: GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:134854577,b:137033609 BRANCH=octopus TEST=build Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-18mb/google/drallion: Add SPD files for drallionAmanda Huang
This change adds SPD files for Drallion. Use spd_index matrix to correspond mem_id. This can save the dummy spd index to reduce the size of SPD.bin. BUG=b:139397313 TEST=Compile successfully Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/google/drallion: Enable 360 sensor detectionBernardo Perez Priego
Implementing logic to detect SKU model and enable ISH accordignly. BUG=b:140748790 Change-Id: I22fafb43dce6545851883be556a02d65a01fc386 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35303 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18mb/google/drallion: Update gpio config for drallionVarun Joshi
Source: Pin Schematics BUG=b:139370304 Signed-off-by: Varun Joshi <varun.joshi@intel.com> Change-Id: I78f85a266eb42ea186ff896db5cde0a347339a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35175 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18sb/intel/ibexpeak: Remove superfluous linked filesArthur Heymans
../bd82x6x/early_usb.c: While ibexpeak needs an equivalent of this code, it is not currently hooked up. ../common/gpio.c: Already linked in common/Makefile.inc Change-Id: I980601e2302f2c412e823fef5fb9a69b9e151322 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35437 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17superio/common: Fix types in printfPatrick Georgi
Found by Coverity Scan #1405310 Change-Id: I53146e7fc402500effc63ce276ecfce4d72a4f7f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35433 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controllerBill XIE
Some T430s variants have a Thunderbolt controller wired to PCIe port The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5. TODO: find the correct gpio pin to detect the Thunderbolt controller at runtime. There are 3 variants of mainboard for Thinkpad T430s: Basic type (Wistron LSN-4 11263-1), Boards with an additional discreet GPU, Boards with an additional TB controller (Wistron LSN-4 11271-1), each of which has a different schematic. The gpio27 on the last type is set as set as GPIO-INPUT, compared with GPIO-OUTPUT-HIGH on the basic type boards. Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-17cpu/intel/model_2065x: Don't redefine CPU_ADDR_BITSArthur Heymans
This Kconfig symbol is set at a default of 36 in cpu/x86 and is now only used in the romcc bootblock to set up caching to upgrade the microcode. It's not mainboard specific. Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35436 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17nb/nehalem: Move MMCONF_BASE_ADDRESS to a common placeArthur Heymans
Change-Id: I872959c4a38e28c29220b81c9fe029e7fc553ccf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35435 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17security/vboot: Fix regression with VBOOT_STARTS_IN_ROMSTAGEKyösti Mälkki
Fix regression after commit 21160a7 Add definition for ENV_ROMSTAGE_OR_BEFORE to <rules.h> Builds with VBOOT_STARTS_IN_ROMSTAGE=y would evaluate ENV_ROMSTAGE_OR_BEFORE incorrectly for verstage-class. Follow-up changes for CBMEM console and timestamps, where defined(__PRE_RAM__) tests are replaced, are likely to have caused regressions such that VBOOT console and timestamps are missing. Change-Id: Idc274409c495efea95eeecd0538b2f8b847970ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-17binaryPI: Drop PSP Secure OS from buildKyösti Mälkki
For pcengines/apu2 variants we do not even send DRAM ready message to PSP. Possibly some GFX/DRM depends of running PSP but these devices are headless. And we don't support fTPM inside PSP either. Reduces blob footprint in SPI from 466 KiB to 234KiB. Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-09-17binaryPI: Move Hudson firmware higher in CBFSKyösti Mälkki
Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB. Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions. NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading. Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-09-17binaryPI: Refactor Makefile for PSP directoryKyösti Mälkki
Change-Id: I3c2d528519ac26b24159a46400f232d6acd629e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-09-17google/kukui: Pass reset gpio parameter to BL31Tristan Shieh
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter. Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-17AUTHORS: Move src/device copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Additional cleanup - Unify "Inc" to "Inc." and "LLC." to "LLC" Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie03a3ce1f6085494bd5f38da76e2467970cf301a Reviewed-on: https://review.coreboot.org/c/coreboot/+/35430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-163rdparty/chromeec: Update to latest masterElyes HAOUAS
It's been some time and there are 1420 new commits. Including one that allows reproducible builds \o/ and one that breaks building with empty $(CC) :-/ Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16mb/up/squared: Do RAM config based on SKU IDFelix Singer
TESTED=UP Squared Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16src/soc/intel/{common,cnl,skl,icl}: Move global reset req function to commonSridhar Siricilla
send_heci_reset_req_message() is defined in multiple places, hence move it to common code. TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards. Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228 Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16src/mainboard: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33528 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16mediatek/mt8183: Add soc ARM Trusted Firmware supportkenny liang
Set BL31 platform to mt8183 to link with ARM Trusted Firmware. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui with more patches in ATF. Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3 Signed-off-by: kenny liang <kenny.liang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-16mb/google/kohaku: Update USB port settingsSeunghwan Kim
This change overrides USB port settings for kohaku. Some port settings are same with baseboard, but I'd like to describe all settings here to be aware of current setting and usage of USB ports on kohaku. BUG=none BRANCH=none TEST=built and measured SI of USB ports internally Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-15mb/packardbell/ms2290: Use common SB code to set up GPIO'sArthur Heymans
Change-Id: I6658c53213127db5a46f2ea330d85a3a537c3276 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-15soc/intel/skylake: add some FSP SATA paramsMichael Niewöhner
This adds SATA parameters for SpinUp, HotPlug and TestMode to the Skylake FSP 2.0 interface. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15mb/*/{x201,ms2290}/mainboard.c: Remove superfluous ramstage codeArthur Heymans
Change-Id: I0270c50dea2a2ce6c8e6114ed708f06be9d33c0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-15cpu/intel/microcode: Make microcode lib available in bootblockRizwan Qureshi
Make microcode lib available in bootblock. Now that microcode.c is compiled in bootlock no need to include it explicitly, hence remove its references. Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35278 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15{i945,i82801gx}: Remove unneeded include <cpu/x86/cache.h>Elyes HAOUAS
Change-Id: I4f38be28d81c0c01c0389210552232e63ea55545 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34934 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15src/security: Remove unused #include <fmap.h>Elyes HAOUAS
Change-Id: I9db59d5db2ed3e792251a94b67fb277d9160e4e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33734 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15southbridge: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I8578cf365addc47550e27c9ebed08de340d70ede Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33531 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15src/soc: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33530 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15northbridge: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33529 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15{cpu,device,drivers}: Remove unused include <device/pci_ops.h>Elyes HAOUAS
Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33527 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15src/mainboard: Remove not used #include <elog.h>Elyes HAOUAS
Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33729 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15nb/i945: Remove unused include <cpu/cpu.h>Elyes HAOUAS
Change-Id: I5dff9b7c157b2aba596e95b5fb18a84f7c4e9365 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-15lib/coreboot_table: Show splashscreen in lb_table_initJohanna Schander
Every vga init implementation needs to cache the framebuffer state to be able to fill the lb_framebuffer struct later on in the fill_lb_framebuffer call. Showing the bootsplash afterwards guarantees to have the same interface into all the vga drivers. This is by far from ideal, as it only allows for a single driver at compile-time and should be adapted in the future. It was tested on the wip razer blade stealth using vgabios @ 1280x1024 and also in Qemu @ 1280x1024. By default the qemu framebuffer will be initialized in 800x600@32. This can be overwriten by configuration by setting CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_{X,Y}RES . Change-Id: I4bec06d22423627e8f429c4b47e0dc9920f1464e Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-15soc/amd/common: Remove Picasso display HDA from listMarshall Dawson
The PCO_HDA0 device contains the "ATI" vendor ID 0x1002 and was incorrectly added to this file. It isn't anticipated that the device will need special handling, so remove it from the list of supported IDs. Change-Id: I306a806dc510e3a4ee3d9c0663306dc93b1d936d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-14src/: Replace some __PRE_RAM__ useKyösti Mälkki
Change-Id: Iaa56e7b98aad33eeb876edd7465c56c80fd1ac18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-14ec/acpi: Replace __PRE_RAM__ useKyösti Mälkki
Change-Id: Iae31569f16168ba00ce272e4777f3a69bcd6ee94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-14arch/x86: Replace some __PRE_RAM__ useKyösti Mälkki
Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35390 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14cpu/x86: Drop lapic_remote_read()Kyösti Mälkki
Unused and declaration conflicts with the one amdfam10-15 uses in romstage. Change-Id: Icd454431285b7c423a4f78d2a0085497d052adc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35394 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume()Kyösti Mälkki
Unused since commit d46b8d5. Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35389 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14mb/asrock/h110m: configure SuperIO global registersMaxim Polyakov
Information based on superiotool dump. Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14mb/asrock/h110m: configure GPIOs in SuperIO chipMaxim Polyakov
Enables and configures GPIOs in the NCT6791D chip. The values for registers taken from the superiotool dump. Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14mb/asrock/h110m: enable ACPI LDN in SuperIOMaxim Polyakov
Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14mb/asrock/h110m: set I/O Range for SuperIO HWMMaxim Polyakov
Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35369 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14arm64: Uprev Arm TF and adjust to BL31 parameter changesJulius Werner
This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 42cdeb930). Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. NOTE: This may or may not stop Cavium from booting with the current pinned Trusted Firmware blob. Cavium maintainers are still evaluating whether to fix that later or drop the platform entirely. Tested on GOOGLE_KEVIN (rk3399). Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-13timestamps: Remove TIMESTAMP_CACHE_IN_BSSKyösti Mälkki
This was implemented for LATE_CBMEM_INIT support which has already been deprecated. Change-Id: I39225ba675bc3389e051e15b400a905431969715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35375 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13timestamps: Further simplify timestamp_reinit()Kyösti Mälkki
Allocation of new table always happens in romstage. Change-Id: I089a84b372893fb3018a796fb1e16cd58753bdf4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35374 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13drivers/pc80: Remove some __PRE_RAM__ and __SMM__Kyösti Mälkki
Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35388 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13security/vboot: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Ibaeda2762c733fdbe48979b635cc0cfd7ee4295d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35387 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13intel/broadwell: Replace some __PRE_RAM__ useKyösti Mälkki
Guards are required due to different PCI accessor signatures. Change-Id: I60e87f16a48565917f6ee9d05cc59d2b9373270c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35381 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13intel/haswell: Remove some __PRE_RAM__ useKyösti Mälkki
Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35380 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13soc/intel: Remove some __PRE_RAM__ useKyösti Mälkki
Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35379 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one tablePeichao Wang
BUG=b:140008849, b:140573677 TEST=verify eMMC SKU and SSD SKU will bring up normally. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-13emulation/qemu-i440fx/fw_cfg_if.h: replace macro with enumHimanshu Sahdev
replace multiple existing FW_CFG_* defines with enum fw_cfg_enum. Change-Id: I9699df4aeb2d8b18f933bb9aaed16008d10158ad Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-13drivers/intel/fsp2_0: Allocate cfg_region_size for UPDMarshall Dawson
In FSP-S, the driver constructs its pointer to UPD using the offset in the header. Similarly, use the header's cfg_region_size for allocating memory and copying the default configuration. Add sanity checks for unexpedted configuration and UPD header conditions. TEST=Verify OK on Mandolin, verify a mock error condition BUG=b:140648081 Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13arch/x86/bootblock_crt0.S: Leverage eax in protected mode entryHimanshu Sahdev aka CunningLearner
Leverage already used eax register in bootblock_protected_mode_entry. Avoid another register ebx just for preserving eax value as it is not needed and is not used at all after moving the value into mm0. Allow EBX to be preserved for other usage. Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13drivers/elog: Add elog_boot_notify()Kyösti Mälkki
Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13intel/nehalem: Refactor ACPI S3 detectionKyösti Mälkki
Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-13intel/fsp2_0: Move TS_BEFORE_INITRAMKyösti Mälkki
Exclude FSP-M loading from the timestamps used for RAM detection and training process. Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13mb/google/drallion: Use arcada_ish.bin for arcada_cmlSelma BENSAID
drallion_ish.bin is updated for drallion GPIO changes and not compatible with arcada_cml. TEST=Build and boot arcada_cml Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-13soc/intel/cannonlake: Allow coreboot to reserve stack for fspBora Guvendik
FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack. This change selects common stack config, that enables coreboot to support share stack with FSP. TEST=Boot to OS on WHL platform Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-09-13mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500msPhilip Chen
Even though GT7375P programming guide rev0.4 only requires a reset delay of 120ms, in practice, we have to increase the reset delay to 500ms, or Goodix FW update would fail. This is a workaround. In the long run, we hope Goodix can fix the power sequence in touch firmware. BUG=b:138795891, b:138796844 TEST=boot helios board and verify Goodix FW update succeeded Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13soc/amd/picasso: Refactor AOAC enablingMarshall Dawson
Replace the raw register definitions with device numbers and macros for determining the register offsets. Rewrite the source to refer to AOAC device numbers instead of a structure. Remove the calculated offset for the console UART. Picasso's UARTs are not contiguous so handle them separately. Change-Id: Iffc87f39ebe38394a56d41bb0940e9701fd05db9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-12mb/google/drallion: Update memory mapIvy Jian
This will increase ME region size and reduce the BIOS region size. BUG=b:140665483 TEST='compile successfully' Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-12soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usageSubrata Banik
PchPwrOptEnable FSP UPD is for internal testing and not really available in externally released FSP source hence assigning this UPD using devicetree config dmipwroptimize doesn't do anything. TEST=Build and boot sarien/arcada. Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-12mainboard/sifive/hifive-unleashed: Update devicetreePatrick Rudolph
With the current devicetree the kernel doesn't provide any serial after serial init. Update the devicetree to resolve this issue. Tested on HiFive Unleashed. Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 02:32:27 +0000