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2015-06-22device: Use x86 specific code on x86-64Stefan Reinauer
Change-Id: I4763ce32bb0b0e301401daaeb89440524fcc682e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10584 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-22x86: make PCI MMIO CFG functions 64bit proofStefan Reinauer
Change-Id: Ife94f5324971f4fa03e9139f458b985f6fed9d87 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10577 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-21Remove obsolete EARLY_CONSOLE usageMartin Roth
The EARLY_CONSOLE Kconfig symbol was removed in commit 48713a1b - console: Drop EARLY_CONSOLE option The arm64 and mips directories don't even have early_console.c to include. Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10615 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-21superio/fintek/Kconfig: add newline at end of file.Martin Roth
Kconfig sometimes fails to parse the last line of a file if there's no newline at the end. Add one to be safe. Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10614 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-21Reorder arch & vendorcode in KconfigMartin Roth
Because Kconfig uses the first valid default that it comes across, the 'source' commands to load sub-Kconfigs should be ordered from the most specific (mainboards) to less specific (chipsets) to least specific (architectures). This allows the mainboards to override chipsets and architecture Kconfig files. Because the architecture files were getting loaded ahead of the chipset and cpu Kconfigs, the preferred defaults values for things such as NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set. Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10609 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-06-21Remove old HAVE_UART_MEMORY_MAPPED select statementsMartin Roth
The HAVE_UART_MEMORY_MAPPED symbol is no longer present, so these don't actually select anything. Change-Id: I6d0eb610e48a4506ac7449ac677ee67981d0ff0d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10608 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-20cpu: x86 port to 64bitStefan Reinauer
Change-Id: Ib1c6732d3a338f6d898fadc19e5af59032343451 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10580 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20x86: Make ACPI 64bit cleanStefan Reinauer
Change-Id: I29eaba74185711df055cf56c23ef2bdae0c7b43e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10578 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20x86: Make reading / writing of CRx registers 64bit proofStefan Reinauer
Change-Id: I782007fe9754ec3ae0b5dc31e7865f7e46cfbc74 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-20x86: make memcpy 64bit safeStefan Reinauer
This does not optimize memcpy for 64bit, it merely makes it compile. Change-Id: I69ad6bd0c3d5f617d9222643abf7a2ba7c2a0359 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10575 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-17winent/mb6047: initialize hardware monitor CPUTIN configurationJonathan A. Kollasch
Change-Id: Ic36727104e5c2f620f9b2b7b340de8548b467397 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10547 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17mainboard/bap: Add support for BAP ODE E20XXFabian Kunkel
Adding new board based on AMD Kabini. Most of the code is copied from gizmosphere/gizmo2 Board is developed by BAP - Bruhnspace Advanced Projects: http://www.unibap.com/ (Site is under construction) Special on this board is: -Soldered down memory -SuperIO Fintek F81866D Known bugs: -S3 doesnt work -Serial ports only works for the first boot. Needs power cut. Tested with: -SeaBios as Payload -Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1 -Windows 8 64Bit Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10288 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17pcengines/apu1: Add ACPI led, button and GPIO devices.Tobias Diedrich
Provide ACPI devices with devicetree-compatible annotations for the three leds and the button of the APU1, as well as the GPIO driver. This will cause the Linux kernel to automatically load the following modules: leds_gpio (CONFIG_LEDS_GPIO) gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED) gpio_sb8xx (CONFIG_GPIO_SB8XX) See http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf and https://lwn.net/Articles/612062/ for some more information on how the PRP0001 HID works. To make this usable a Linux GPIO driver for the AMD chipset is also required, which I am currently working on, but have not submitted upstream yet. Leds have been named after the convention in Documentation/leds/leds-class.txt: LED Device Naming ================= Is currently of the form: "devicename:colour:function" For comparison, on an OpenWRT device: GPIOs 0-21, ath79: gpio-1 (tp-link:green:usb ) out hi gpio-2 (tp-link:green:system) out lo gpio-3 (reset ) in hi gpio-5 (tp-link:green:qss ) out lo gpio-7 (qss ) in hi gpio-9 (tp-link:green:wlan ) out lo gpio-18 (rtl8366rb ) in hi gpio-19 (rtl8366rb ) in hi On the apu1: GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver: gpio-475 (switch1 ) in hi gpio-477 (apu1:green:led1 ) out hi gpio-478 (apu1:green:led2 ) out hi gpio-479 (apu1:green:led3 ) out hi Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10540 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17coreboot_tables: Add CBMEM ID and tag for MTCFurquan Shaikh
BUG=chrome-os-partner:41125 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ia95b2a21863df5c3d6c08e9a134618db03a58775 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8462a33c62ab34d0f5049fc3a7c5c2ee8e5e2e4c Original-Change-Id: Ie48a9a776b1c3ad30acf924c3d073acc8f2a8eda Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276779 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10562 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17x86 cpu: Allow some cpuid functions during romstageLee Leahy
Allow calls to cpu_phys_address_size and its support functions during romstage. This enables the proper display of MTRRs during romstage without duplicating this code. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0 Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277392 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10561 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-17PCIe : Adding some error/not-null condition checkingPratik Prajapati
This patch checks for following conditions (1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found then don't enable LTR. (2) 2.1) set_L1_ss_latency is member if ops_pci, which could be NULL. so confirm ops_pci is not NULL before calling its member function. 2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency. BUG=none BRANCH=none TEST=build and boot coreboot with L1 substate enabled on sklrvp3. Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181 Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/10559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-17arm64: Move enabling floating point ahead of dev initJimmy Zhang
This CL is in preparing for tegra mtc that is invoked by dev init. mtc currently requires floating point instructions support. BUG=chrome-os-partner:40999 BRANCH=none TEST=Build and boot smaug Change-Id: I470dfcd86026812d617f9ff4f4fcdce601195857 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e3f7336fc7cedf96dab4eff204616519856f831 Original-Change-Id: I14c0003ce76ddf4b4ebb0cf171ea3c62cab55ef9 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/275112 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10558 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-16x86: Make stdint.h x64 proofStefan Reinauer
Change-Id: Ibcfdc08c9aac02fe263afd629fc262f71da80e9a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8695 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16cpu: add x64 class for cpu_microcodeStefan Reinauer
Change-Id: I1535fea97c676ed6465d777f444b0a1a0e023474 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8694 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16x86: Make x86 architecture makefiles x64 awareStefan Reinauer
Almost all of the code between x86 and x64 can be shared, so select it for either architecture. Change-Id: I681149ed7698c08b702bb19f074f369699cef1bf Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8693 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-16Add x64 support to src/arch/x86/KconfigStefan Reinauer
Change-Id: I81f6d8a21ea0d8218f5a4aab2feb39be32f88e01 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/8692 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-15ck804 ACPI: set duty width in FADT correctlyJonathan A. Kollasch
Change-Id: I12ef633009b5c63b08fbeb76d58cb08c776485ac Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10546 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-14pcengines/apu1: Remove unused smbus.aslTobias Diedrich
The smbus.asl operation regions prevent the Linux i2c driver (i2c_piix4) for this chipset from claiming the ioport ranges and thus it fails to load. The methods defined in smbus.asl are not used in the DSDT and also don't exist in the DSDT of the vendor firmware. In particular due to the following check in i2c-piix4.c will fail unless acpi_enforce_resources=no is explicitly set on the Linux kernel parameters: if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) return -ENODEV; Depending on kernel options the only error message printed is ACPI Warning: SystemIO range 0x0000000000000B00-0x0000000000000B07 conflicts with OpRegion 0x0000000000000B00-0x0000000000000B0B (\SMB0) (20150410/utaddress-254) ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver However since it does not implement a standard interface there is no native ACPI driver for smbus.asl. Change-Id: Id8401e8b36f0e2412d490a92c20540a04d853125 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10539 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14winent/mb6047: Remove redundant P-State generationJonathan A. Kollasch
Recently ck804/lpc.c started generating pstates for us. Change-Id: Ie47fff0516e0e838fdcd5084074ce2cabfe7e290 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/8318 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14mainboard/lenovo/t400: Fix HDA verbs to match hardware layoutMichał Masłowski
The same values are used on my Lenovo R400 as reported by Francis Rowe from his T400 and T500. TEST: Read /proc/asound/card0/codec#0, see that the jack locations correspond to the board layout, e.g. headphone and microphone connectors are on front of the laptop, not right. Read /sys/class/sound/hwC0D0/init_pin_configs, see that it has the same content as with factory firmware. Change-Id: I60e914ca9fab4bb2c99b4ed9e6d81a0580a88b18 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Reviewed-on: http://review.coreboot.org/10431 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-14asrock/e350m1: Remove unused file `acpi/smbus.asl`Paul Menzel
Commit 8d80a3fb (ASRock DSDT: Split the ASRock DSDT) creates the file `acpi/smbus.asl` in the board directory, but includes the identical southbridge file in `dsdt.asl`. So, the file is actually unused. Therefore remove it. Change-Id: I26c5a2eaf3822d37da2402da65b278a3ee6d42f0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10544 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14amd/cimx/sb800/acpi/smbus.asl: Align commentsPaul Menzel
Change-Id: I1ea1b1efedfea2926a24f06beeb8d7d0464057e5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-13Move remap_bsp_lapic to AMD specific codeStefan Reinauer
It's not used outside of very old AMD CPUs. Change-Id: Ide51ef1a526df50d88bf229432d7d36bc777f9eb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10538 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13google/auron: Add mainboardMarc Jones
Add the Google Auron Broadwell Reference Mainboard. It is based on the Google Peppy mainboard. It was merged from the following chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10500 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13southbridge/amd/pi: Add support for new AMD southbridge KernWANG Siyuan
Kern is the southbridge of AMD Merlin Falcon(Carrizo). This add support of HD audio, lpc, sata and usb for Kern. Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10418 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13AMD Merlin Falcon: Add CPU subdirectory files for new AMD processorWANG Siyuan
This adds the AMD Family 15h model 60h CPU. S3 suspend/resume currently is not supported. Tested on the amd/bettong platform. Change-Id: I5dea55a5664d29c07a54937ed1e5c2f84715d8ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10417 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13vendorcode/amd: unify amdlib for binary piStefan Reinauer
Instead of having three copies of amdlib, the glue code for Agesa, let's share the code between all implementations (and come up with a versioned API if needed at some point in the future) Change-Id: I38edffd1bbb04785765d20ca30908a1101c0dda0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10507 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13AMD Merlin Falcon: Add binary PI vendorcode filesWANG Siyuan
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10416 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12superio/fintek: Add support for Fintek F81866AD-IFabian Kunkel
This patch adds support for the Fintek F81866AD-I SuperIO, which is very similar to the fintek/f81865f. This code adds some fan control support, inspired by fintek/f71869ad. Furthermore its possible to change the temp sensor type (thermistor or diode). Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Id2fc1119b37142f8101f71908e394ee69c45041d Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: http://review.coreboot.org/10287 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-12pistachio: add DDR3 initialization codeIonela Voinescu
Initialization for the Winbond W631GG6KB part using Synopsys DDR uMCTL and DDR Phy. This code adds a separate function for DDR3 initialization and moves all the necessary defines in a separate header file. The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following: 1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature, voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state. It was tested on Pistachio bring up board where DDR was initialized properly and ramstage executed correctly Change-Id: I3bcbce2044327a22fce09b184d85ee11228a6b2b Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10529 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12pistachio: Use passive windowing as DQS gating schemeIonela Voinescu
Switching from active windowing DQS gating scheme to passive windowing mode resolves boot stability issues on chips found to have memory corruption issues during boot or memory tests. It was tested on Pistachio bring up board where DDR is initialized properly and ramstage executed correctly; We have cycled units over 12,000 times with no boot errors. This option was chosen over the alternative of using passive windowing mode for DQS training and after switching back to active mode, as this option was recommended by Synopsys. Using the alternative would give different timing values during training that were not longer accurate during normal activity. Change-Id: Ie604eddc0a9a982b2f89198f44deb88a01b7b322 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-12google/jecht: fix MAC address programming when VPD not presentMatt DeVillier
Fix by checking the actual function return value (the search address pointer), rather than the search length value (which isn't guaranteed to be sane or useful). Change-Id: I226c635ddbbc916b02494fcd97df27d141cc2c7f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10516 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-06-12google/panther: fix MAC address programming when VPD not presentMatt DeVillier
Commit 899d13d (cbfs: new API and better program loading) broke panther's lan init when no vpd.bin present from which to read the MAC address. Fix this by checking the validity of the search address pointer, rather than the search length. Change-Id: I8c7ca410d8ce5c5d92242a21c4c2ff4c001a68bd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10509 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-11Clearly define printk log level use cases.Nicky Sielicki
The proper log level for any given printk statement is up to the interpretation of the developer. This results in console output with somewhat inconsistent levels of verbosity. This patch clearly defines each log level and its use case, hopefully resulting in less ambiguity for developers. The concern with this patch might be that it leaves a lot of preexisting printk statements using a log level that is inconsistent with the description. I think that *most* statements map to these extended definitions very nicely. The most discrepancies are between debug and spew, but I'm willing to say that 95% of statements with a level lower than debug are correct by these definitions. There was some discussion dating back to 2010 on the mailing list about renaming these constants to lose the 'BIOS_' prefix and to consolidate some of them into a single constant. I disagree that it is necessary to merge any of them, I think they all have unique use cases. But I do think that if you all agree with these definitions, it might be useful to rename them to reflect their use cases. I also will add that I believe removing BIOS_NEVER is a good idea. I do not see the use case, and it's used in only 4 files. Change-Id: I8aefdd9dee4cb4ad2fc78ee7133a93f8ddf0720b Signed-off-by: Nicky Sielicki <nlsielicki@wisc.edu> Reviewed-on: http://review.coreboot.org/10444 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-11lenovo: Hide SMBIOS configVladimir Serbinenko
It's derived from EEPROM on Lenovo machines and not from user config which is ignored. Change-Id: I54fb76a3160e47cd36d33d2937c4bfaddcd36a69 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7055 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-06-10mips: implement arch_segment_loaded callbackIonela Voinescu
This change adds cache management after loading stages. Before jumping to a new stage we should flush the data caches to memory and invalidate instruction cache. After all segments are loaded CBFS cache is also flushed. With this change all stages of coreboot are now executed successfully. This was tested on Pistachio bring up board, also known as Urara. Change-Id: I86e07432c21a803ef1cfc41b633c5df42b99de90 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10456 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-10mips: CBMEM table reference is passed to payloadIonela Voinescu
The coreboot table address is passed as an argument when jumping to payload. With this change depthcharge is loaded and executed properly on urara. Change-Id: I230d474a91b8d38aff070aa4aac623b6c8f0809c Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10pistachio: sort included header filesIonela Voinescu
Place included header files in alphabetical order. Change-Id: Ice23178d1f07e2cb0178efbc7ce487d54bf3f708 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10459 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10pistachio: initialize cbmem area to be emptyIonela Voinescu
Use cbmem_initialize_empty() after DDR configuration so that cbmem is always initialized from scratch on each boot. Change-Id: Ic9ca34867b26aab82cf3154280694b6fb61ee11f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10458 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-10AMD PI: remove unuseful ACPI codeWANG Siyuan
sata.asl and superio.asl are empty files. Remove them. Change-Id: Icd3e990aa713281e46dcbd8e0847166c77656b1c Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10kconfig: Reorder config includesDuncan Laurie
The default ordering for the base kconfig entries has the CPU directory coming before the SOC directory, which means that the values in the CPU Kconfig take precedence. The first visible consequence of this is that CONFIG_SMM_TSEG_SIZE will be set to 0 on all SOC implementations. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: Ifd56a2ceb73ab335a86126e48d35ff4c749990ac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0cddae37d3de1cbf3dd6afcf4a0707b7af9436fa Original-Change-Id: I98e3bf249650b50667dde62b6be9c1bf587ad0b2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/276189 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10478 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10rockchip: rk3288: add HDMI related iomux configurationhuang lin
BUG=none BRANCH=none TEST=Boot from mickey board Change-Id: I6eadf52bddcf89011a112a8e5dee5e752556add9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e3c865f0bf8567c3183d7948a0f9e8361db70695 Original-Change-Id: I438527ee0870044f48b23a6842986e7cf166e191 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/276290 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/10477 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10google/auron: Add initial mainboard copy from PeppyMarc Jones
Copy the Peppy directory. No changes. Change-Id: I3fa382eaa40f642df8bc09ab69be67cbe9f3671a Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10499 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10mainboard/lenovo/t400: Add initial ATPX ACPI implementationTimothy Pearson
Change-Id: I9b86ebec59ccb63db0e1ba61533d162507a22379 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9320 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-10google/jecht: Remove whitespace at EOLKyösti Mälkki
Change-Id: I707802befe5b8aaafafc34b17cbdfe795777b6f6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10501 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-10smbios: Fix type1 family settingMarc Jones
The type1 family setting from chromium was mis-merged into the type2 function. Move it to the correct type1 function. Bad commit: 51bdc4781635b99d89e6b7a414a2172be8cb690c Change-Id: I72e6ef80bbf185a39fcf169c8247dc16462e6bc3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10498 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-06-10lenovo/t400: Fix buildKyösti Mälkki
Change-Id: I8e8b6e7c123e641749c42a7c706176e285902bb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10502 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-10mainboards/lenovo/t400: Remove X200-specific codeTimothy Pearson
Change-Id: Ic3503938b996bbf31f1417923f019a7bc722b9fd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10429 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-06-10mainboards/lenovo: Copy X200 board to T400 for future expansionTimothy Pearson
Change-Id: If2d48b84fe7bd7b144e96171e54067891e3c4e2e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9316 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10mainboard/lenovo/x200: Add power_on_after_fail NVRAM optionTimothy Pearson
Change-Id: I8e78cbae132566b6ca27e0a68af2656364c82b8f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9332 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-10resource: Refactor IORESOURCE flags useKyösti Mälkki
The type of a resource is really an enumeration but our implementation is as a bitmask. Compare all relevant bits and remove the shadowed declarations of IORESOURCE bits. Change-Id: I7f605d72ea702eb4fa6019ca1297f98d240c4f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8891 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10PCI subsystem: Drop PCI_64BIT_PREF_MEM optionKyösti Mälkki
No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10northbridge/amd/amdfam10: Increase MMIO hole size to 1GBTimothy Pearson
On modern mainboards with multiple PCI-e devices and a single graphics card the default MMIO hole size of 512M is inadequate, leading to resource-hungry PCI-e devices (such as an external graphics card) being assigned invalid MMIO ranges. This, in turn, causes the entire PCI subsystem to become unavailable, leading to a failure to boot. TEST: Booted KGPE-D16 with NVIDIA 7300LE and verified proper operation of PCI/PCI-e devices, including text mode VGA operation via the add-on card and its VGA option ROM. Change-Id: I8d25f4b19f2d0860644ab1ee002c15041437121f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10428 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-10model_2065x: Use common i945-ivy TSEG SMM init.Vladimir Serbinenko
Change-Id: I0302cbaeb45a55a4cfee94692eb7372f2b6b206d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10northbridge/amd/amdmct: Honor MMCONF_BASE_ADDRESSTimothy Pearson
The MMIO hole start address was hardcoded on AMD Family 10h systems. Use the MMCONF_BASE_ADDRESS Kconfig setting instead. Change-Id: I204e904d96d14e99529fa5e524fd73e6ea256dc0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-10model_206ax: Fix APIC map when HT is disabled.Vladimir Serbinenko
Change-Id: Idd05a16bd9bd31438437ef229aa87f55da8489fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10467 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10fsp_model_206ax: Use common i945-ivy tseg SMM init.Vladimir Serbinenko
Change-Id: Iac390b565d709b11bc7a6631b11315994b6e2c3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10466 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-09vboot: add new firmware indiciesAaron Durbin
Some patches landed that didn't introduce the Kconfig options for additional firmware components. Add them. Change-Id: I0a0b7f0291389d126a7c491f710618a278cfb5d7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09x86: remove printk() from init_timer()Aaron Durbin
For console drivers which use udelay() we can deadlock in the printk path on the spinlock. The reason is that on the first call to udelay() from within a console driver it will go back down the printk() path deadlocking oneself. Just remove the printk() as it was asymmetric on romstage vs ramstage. Change-Id: I30fe7d6e5b4684f17d4f353c0816b64f9242de0a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10483 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-09pistachio: increase romstage sizeIonela Voinescu
This change is necessary to support future additions to romstage. Change-Id: Ibb69994847945c7adbafbf2bc677b33821df8146 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/10457 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-09stage_cache: use cbmem init hooksAaron Durbin
Instead of having the chipset code make the approrpiate calls at the appropriate places use the cbmem init hooks to take the appropriate action. That way no chipset code needs to be changed in order to support the external stage cache. Change-Id: If74e6155ae86646bde02b2e1b550ade92b8ba9bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09cbmem: add indicator to hooks if cbmem is being recoveredAaron Durbin
It can be helpful to certain users of the cbmem init hooks to know if recovery was done or not. Therefore, add this as a parameter to the hooks. Change-Id: I049fc191059cfdb8095986d3dc4eee9e25cf5452 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10480 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-09device/device.c: Improve output in `init_dev()`Paul Menzel
Since commit 05294292 (device tree: track init times) there are two lines printed for each init() call of a device, when `HAVE_MONOTONIC_TIMER` is selected. […] CPU_CLUSTER: 0 init 12708 usecs DOMAIN: 0000 init DOMAIN: 0000 init 1 usecs PCI: 00:00.0 init Northbridge init PCI: 00:00.0 init 2 usecs PCI: 00:01.0 init PCI: 00:01.0 init 1 usecs PCI: 00:01.1 init PCI: 00:01.1 init 1 usecs PCI: 00:11.0 init PCI: 00:11.0 init 1 usecs PCI: 00:14.0 init PCI: 00:14.0 init 1 usecs PCI: 00:14.3 init SB800 - Late.c - lpc_init - Start. RTC Init RTC: coreboot checksum invalid SB800 - Late.c - lpc_init - End. […] Improve the output by changing the wording to. %s init ...\n init() %s init finished in %ld usecs\n Note, that `%s init ... done in %ld usecs` is not possible as the function `init()` can also print messages. Change-Id: I7132cd650911dba680f060d6073a5a09c879b24c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-09Create i945-ivy smm tseg init based on ivy code.Vladimir Serbinenko
CPU-side logic is unchanged for this range of CPUs as long as all of them use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while extracting southbridge and APIC code into separate functions. Change-Id: Ib365681d1da8115922c557fddcc59afc156826da Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10465 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-09cbmem: Unify CBMEM init tasks with CBMEM_INIT_HOOK() APIKyösti Mälkki
Squashed and adjusted two changes from chromium.git. Covers CBMEM init for ROMTAGE and RAMSTAGE. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7878 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-09cbmem: Break out CBMEM_ID to a separate header fileMarc Jones
The cbmem util needs the CBMEM_IDs and the strings for reporting and shares the cbmem.h file with coreboot. Split out the IDs so for a simpler sharing and no worries about overlap of standard libraries and other things in the header that coreboot requires, but the tool does not. Change-Id: Iba760c5f99c5e9838ba9426e284b59f02bcc507a Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10430 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-09google/jecht: add new mainboardPatrick Georgi
Taken from CrOS, including everything up to commit da4c33913. Adapted to upstream. Change-Id: I095e6726a220200ba17719fc05fcdc521da484e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10432 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-08x86 SMM: Relocator is intel-onlyKyösti Mälkki
Change-Id: I78519b8f060b1ba81e8b9c7c345820180a14f2fe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10441 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-08southbridge/amd/{agesa,pi}/hudson/lpc.c: Sync togetherEdward O'Callaghan
Resync together, backporting a fix for the initialization of 8254 and 8259, as in commit 8d9a1bd5. Also fix a typo and reduce out useless whitespace differences. Change-Id: I9a9b1fb9083c5417a8d061f90a89074f2a601ddf Signed-off-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reported-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10453 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-08Remove empty lines at end of fileElyes HAOUAS
Used command line to remove empty lines at end of file: find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \; Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/10446 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-07smbios: Use smbios_mainboard_manufacturer instead MAINBOARD_SMBIOS_MANUFACTURER.Vladimir Serbinenko
Be consistent. Change-Id: I13df06fbc86371bfcb4ddd809d07c9e7fb931018 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10381 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-06-07Removed unused SOUTHBRIDGE_INTEL_FSP_I89XX expressionsMartin Roth
The SOUTHBRIDGE_INTEL_FSP_I89XX symbols are never defined in any Kconfig file or used anywhere in the existing coreboot tree. Removing them as unnecessary. If the southbridge code ever gets uploaded, these can be re-added at that point. Change-Id: I36f9ca8e25e08ce154d10ea9d764a73095590244 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10436 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-07macbook21: switch off led before jumping to payloadMono
Mimic vendor BIOS in switching off the led once coreboot has booted successfully. Currently the led behavior is inconsistent. The led turns on during poweron and stays on forever. When entering S3 and during S3 it blinks and turns off after wake from S3. The behavior associated with S3 is the same under vendor BIOS and under coreboot. Switching off the led before jumping to the payload makes the led behavior consistent within coreboot before S3 and after wake from S3 and it makes the led behavior consistent to vendor BIOS. Change-Id: I0dec10b842b83dfc8054cd56d2750b724c4e8576 Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de> Reviewed-on: http://review.coreboot.org/10454 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-06-07veyron_mickey: Update board name to uppercaseMartin Roth
Change the Kconfig board name symbol to uppercase to match other symbols and to match the capitalization in the Kconfig file where it's used in an expression. Change-Id: I04ccb57cc15a6d7430f8d04136beb8384caa6c04 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10440 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-06-07mainboard/ti/beaglebone: Remove unused Kconfig symbolsMartin Roth
Cleaning up unused Kconfig symbols. These symbols are not used anywhere in the coreboot tree as far as I can tell. Change-Id: I4d0b9512a784083dd134a8706b3bd8eca2a3a909 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10439 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-07Fix Kconfig whitespace.Martin Roth
All other Kconfig locations start with tabs. Change-Id: I0ee5f0b0b82f85c8ae58b3626f142f159554efb3 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10438 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-07acpi/sata: add generic sata ssdt port generatorAlexander Couzens
generate_sata_ssdt_ports() generates ports based on sata enable map Change-Id: Ie68e19c93f093d6c61634c4adfde484b88f28a77 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9708 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2015-06-05device_ops: add device_t argument to write_acpi_tablesAlexander Couzens
`device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I1ba4bfa0ac36a09a82b108249158c80c50f9f5fd Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9599 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05device_ops: add device_t argument to acpi_fill_ssdt_generatorAlexander Couzens
`device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05device_ops: add device_t argument to acpi_inject_dsdt_generatorAlexander Couzens
`device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I3fc8e0339fa46fe92cc39f7afa896ffd38c26c8d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9597 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05google/veyron_mickey: Add new mainboardDavid Hendricks
This simply copies veyron_brain to veyron_mickey and makes the minimal set of changes (s/brain/mickey) to make it compile. The follow-up patch will take into account board differences. BUG=none BRANCH=none TEST="emerge-veyron_mickey coreboot" doesn't fail Change-Id: I7d029b36d2fb865446490b896117ade632325a52 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34f6b391290f99caf517d7e98c31c89dc57309be Original-Change-Id: I03a2b80eb441384f363910467180479521765431 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271360 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10408 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-06-05google/veyron_romy: Add new mainboardDavid Hendricks
This simply copies veyron_brain to veyron_romy and makes the minimal set of changes (s/brain/romy) to make it compile. The follow-up patch will take into account board differences. BUG=none BRANCH=none TEST="emerge-veyron_romy coreboot" doesn't fail Change-Id: Ice1bc012bddd6c51b43944747e0df3ffa34207fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ab849178b69cf2323f126e503bd61080048240a Original-Change-Id: I0516ce94fd3c6a38170fae221a070f503ccfaf0f Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271345 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10407 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-06-05lib: Unify log2() and related functionsJulius Werner
This patch adds a few bit counting functions that are commonly needed for certain register calculations. We previously had a log2() implementation already, but it was awkwardly split between some C code that's only available in ramstage and an optimized x86-specific implementation in pre-RAM that prevented other archs from pulling it into earlier stages. Using __builtin_clz() as the baseline allows GCC to inline optimized assembly for most archs (including CLZ on ARM/ARM64 and BSR on x86), and to perform constant-folding if possible. What was previously named log2f on pre-RAM x86 is now ffs, since that's the standard name for that operation and I honestly don't have the slightest idea how it could've ever ended up being called log2f (which in POSIX is 'binary(2) LOGarithm with Float result, whereas the Find First Set operation has no direct correlation to logarithms that I know of). Make ffs result 0-based instead of the POSIX standard's 1-based since that is consistent with clz, log2 and the former log2f, and generally closer to what you want for most applications (a value that can directly be used as a shift to reach the found bit). Call it __ffs() instead of ffs() to avoid problems when importing code, since that's what Linux uses for the 0-based operation. CQ-DEPEND=CL:273023 BRANCH=None BUG=None TEST=Built on Big, Falco, Jerry, Oak and Urara. Compared old and new log2() and __ffs() results on Falco for a bunch of test values. Change-Id: I599209b342059e17b3130621edb6b6bbeae26876 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3701a16ae944ecff9c54fa9a50d28015690fcb2f Original-Change-Id: I60f7cf893792508188fa04d088401a8bca4b4af6 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273008 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05mainboard/lenovo/{t430s,t420s,t520,t530,x220}: Add TPM 1.2 mainboard supportPhilipp Deppenwiese
Every Lenovo Thinkpad includes a Trusted Platform Module, so we can enable it for the sandy-/ivybridge platforms. Change-Id: Icda443ba88c2a49a0033014ce7710dd607fa15dc Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/10411 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-05AMD K8 fam10: Use parent subordinate to track HT enumerationKyösti Mälkki
Change-Id: I930f2beacdc95d0a7edd07db66a1c2e58bb2f3cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8566 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Drop extra HT scan_chain() parametersKyösti Mälkki
Change-Id: Ice7cb89c19585cf725b6f73c33443050f8d65418 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8565 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Drop local is_sblink in scan_chainsKyösti Mälkki
We can define is_sblink = (max == 0) as sblink is always the very first chain we scan. Change-Id: Ibd6b3ea23954ca919ae148604bca2495e9f8753b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8564 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Drop redundant parameters on scan_chain()Kyösti Mälkki
Change-Id: I6041b666e6792cf97b8273ed54832d86af8ed23e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8563 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Refactor HT link connection testKyösti Mälkki
Change-Id: I1e935a6b848a59f7f2e58779bceea599032de9e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8562 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Always have SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
Change-Id: I65fad1cfba95f0ee1ed3f7f7a57d874144da1e40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8561 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8366 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Relocate SB_HT_CHAIN in devicetreeKyösti Mälkki
When we want to scan the HT chain to southbridge first, we relocate it as the first item of dev->link_list of node 0. Change-Id: Ic73ba43aadb3c5e0c8d4b82ed7d41094692ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8560 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0Kyösti Mälkki
Define the default value under northbridge. The list of boards this patchset touches will change to use SB_HT_CHAIN_ON_BUS0 with follow-up patch. Based on code analysis, these boards already scan system bus as the first (active) HT chain, so it is placed as bus 0 even when this option was not explicitly selected. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8353 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0Kyösti Mälkki
Change-Id: I452a93af452073eeac4e6cb9bbc232dc59e911c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8365 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-05AMD K8: Refactor calls for HT configurationKyösti Mälkki
Change-Id: I24ca1dce025e00064f9209affa27586292c7650e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8559 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>