summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2014-09-04drivers/gma: remove unused codeRonald G. Minnich
We had brought this code in from the kernel but found it best to use mainboard- or chipset specific versions. Firmware should strive to be as non-generic as possible. Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172625 Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7dba0dfd25bf9e367f9e5128b15edb018e958c3a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-02acpigen: Correctly handle root scopeVladimir Serbinenko
Change-Id: I9b3c9109b01e348259e64e93a4397212216ab152 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-02smbios.c: Fix mismerge which led to laptop being default typeVladimir Serbinenko
Change-Id: I97ccd08a5e7f094908ed3a85ddae53b158124995 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-02acpi_tables: Remove roda-specific access to 60f [copy-paste error]Vladimir Serbinenko
Change-Id: I12ce0dda823d7733c473ed5ef3b0470d95d794ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6805 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-01google/link: Use common i915_reg.h.Vladimir Serbinenko
Checked by comparing binaries and seeing no differences other than build info. Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-01stout: Kill dead i915 filesVladimir Serbinenko
Not referenced anywhere. Change-Id: I6529f2ecbc34a2fa9ca720fea1224670eb98bdcd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-01lenovo/x60: Remove leftover declarationVladimir Serbinenko
Change-Id: I1ab2118a3127dfacef6a389abd59050493e640fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6817 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-31samus: Change SPD to indicate LPDDRDuncan Laurie
There is some magic new SPD SDRAM type 241 to indicate LPDDR. I cannot find it specificed in any JEDEC document but it is what the reference code uses. Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6777 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-31lenovo/x200: Kill access to nonexisting device [copy-paste error]Vladimir Serbinenko
Change-Id: I1be939e870e8792f5ebb23623fe8f7f119adec36 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6806 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-31iWRainbowG6: Kill unused fileVladimir Serbinenko
Change-Id: I7b9b91519d87d70405b57920b3f1ab98c50526d1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30smbios: reorganise OEM strings handling.Vladimir Serbinenko
OEM strings should not be handled by mobo code but by common code with strings collected from all devices. Change-Id: Ibde61a1ca79845670bc0df87dc6c67fa868d48a9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6788 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-30ec/lenovo/h8: Implement thinkpad-acpi compatible LED functionVladimir Serbinenko
Change-Id: I9998b0b4a1413ab65f1dbdf59b2f84d331ce9c3d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30ec/lenovo/h8: Rename LED to avoid conflicting with thinkpad-acpiVladimir Serbinenko
Change-Id: I9fd7f894d0e611f61e8702e4eacb12d7b81154d8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6789 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30lenovo: Read mainboard version from AT24RF08C.Vladimir Serbinenko
Tablets have different mainboard version than laptop variants. Change-Id: I77a1e2b50d30dcf3fa064e0c378ceca7ccf96e89 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6785 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-30lenovo/h8: Support tablet eventsVladimir Serbinenko
_QXX numbers are determined experimentally, hotkey scancodes from thinkpad-acpi module. Change-Id: I1f7548ef62529ae25dcdcbed0fc74390b7529a2e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6765 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30AMD Steppe Eagle: CPU files for new SoCBruce Griffith
Add the CPU files required to support the Steppe Eagle and Mullins models of Family 16h SoC processors from AMD. This CPU is based on the Jaguar core and is similar to Kabini. Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6679 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30AMD Steppe Eagle: Add northbridge files for new SoC familyBruce Griffith
Add the northbridge file for AMD's new Mullins and Steppe Eagle processor family. Since the processor family name is not the same across AMD's sales and marketing channels, I have elected to use part of the processor ID as the family name. The intent is to reduce confusion since the processor ID is the same for both families. This northbridge support has only been validated on the AMD Embedded variants ("Steppe Eagle"). The AGESA wrappers in coreboot have a function that is intended to mirror the UMA memory allocation performed during memory initialization by AGESA. Update the Steppe Eagle memory allocation to mimic the memory reservation done inside the AGESA BLOB. Change the default CBMEM address, the default video BIOS device ID, and a couple of other defaults to match changes in coreboot community code. The northbridge chip.h specifies how many processor sockets, how many channels, and how many DIMM slots are supported by the northbridge. Steppe Eagle does not permit multisocket systems and has only one memory controller channel. Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6678 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30AMD Steppe Eagle: New integrated southbridge (Avalon)Bruce Griffith
00730F01 contains the Avalon southbridge and a Platform Security Processor (PSP). Supporting the PSP requires specific binaries to be included in the ROM. The fletcher utility is used to sign PSP binaries. The IMC access routines are not accessible for newer AMD parts that use pre-compiled AGESA. Change the Hudson code such that the IMC code is not compiled if IMC is not selected in Kconfig. Disable compilation of resume.c if HAVE_ACPI_RESUME is disabled. The newer AMD mainboards will initially be released without ACPI resume support (S3) due to the use of AGESA internals in the existing Hudson routines. The Makefile change allows newer mainboards to avoid the API issues. Change Kconfig such that the FWM flag is always set for PSP-enabled parts. This has the side effect of forcing the generation of the FWM directory in the absence of GEC, IMC, and xHCI. Change-Id: I6d056f54b60a64300841599490b9fafd561c4a7d Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6677 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30AMD Steppe Eagle: Add binary PI vendorcode filesBruce Griffith
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. The AGESA dispatcher is built using its own rules rather than generic library generation rules in coreboot/Makefile and coreboot/Makefile.inc. The AGESA source files are initially copied from whereever they live into coreboot/build/agesa. They are compiled from there. The binary PI directory has a mandatory structure that places the AGESA BLOB into the same directory as the support headers. These will nominally be placed in the 3rdparty directory in coreboot.org. The copy commands that were added to the the vendorcode Makefile.inc ensure that only one thread will operate on each source file by using a macro to generate the copy targets. After the change, each copy target will operate on exactly one source file. Due to API issues, coreboot has no way to control the IMC to set up fan control. Set a Kconfig flag that removes the ability to install an IMC BLOB into CBFS. Change-Id: I050b72a19086aaeba6cb65ce165297b10e3cfc45 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6595 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30lenovo/x220: New portVladimir Serbinenko
Change-Id: Ic213948e4d31457dda9b9f2d5a4f92cd34d1e57d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6757 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30sandybridge: Add native sandybridgeVladimir Serbinenko
Change-Id: I1b51310b4387e588c4828563620b0e2770598503 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6753 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-29smbios: Define and use enclosure types.Vladimir Serbinenko
Change-Id: Ib5b92120cbe2ca41c9813e8caeb03161f4d3954c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6786 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-29samus: Add ACPI MADT interrupt override for GPIO IRQ 14Duncan Laurie
This interrupt needs to be specified in the MADT before it can be used by the kernel driver. Change-Id: Ic920a792a203cb06cd4529815680584a21532106 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171902 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a330fddb62cb6346ad66ceb5b5c32b66aecd81e2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6778 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-29samus: Add coreboot boardDuncan Laurie
Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-29tegra124: add custom uartGabe Black
tegra124: Add a test function which spams exclamation points on the UART. This function spews characters on the console and, until we have a working console, is an easy way to see whether the system boots to a particular point. For some reason waiting for transmitter to be empty hangs, but transmitting characters still works. Old-Change-Id: I1622c8a58849f4b8bdcaa67500b81042d7346df4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171030 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e0059181958cfe8afec2f3a7ea732e81f5d55e5d) tegra124: Re-enable waiting for the transmitter to empty in the test function. The compiler was emitting code compatible with armv7-a, but the bootblock was running on a core which uses armv4t. By coincidence, it was emitting an instruction which is unavailable on armv4t when checking the value of the UART's LSR register. Now that the bootblock is compiled with more appropriate flags, this code can be re-introduced. Old-Change-Id: I7ecada4138b0889b963d1a8b19a4bab8e0bb1add Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170997 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2a0adceb5029c8ee633d17c82dbb11e48d30349d) tegra124: Seperate out the non-UART specific hardcoded init in the bootblock. The hardcoded init in the test function in the bootblock is actually useful generally because it doesn't belong in the UART driver itself but is necessary for the UART to work. Until we have real implementations for the pinmux, etc., we can use that code to get the UART and console going. Old-Change-Id: I2efe0b571d8b022eb2a2e5569620558540b28373 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171334 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ae7d4d890be1936cc86dc15adeb33f3b46a51ae5) tegra124: Implement and enable serial console support for tegra124. The driver is very similar to the 8250 driver, except it isn't in two parts, and it also spaces its registers 4 bytes apart instead of having them directly adjacent to each other. Also, eliminate the UART test function in the bootblock. It's no longer needed since the actual console output serves the same purpose. Right now the clock divisor is fixed for now, and we'll want to actually figure out what value to use at some point. Old-Change-Id: Idd659222901eb76b0ed8cbb986deb5124096f2f6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171337 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 86f5e2875b18901b349283cfbcd4f8cc88b7a019) Squashed 4 commits related to uart support for tegra124. Modified the new uart.c to look like the uart.c for exynos5420. Change-Id: I490cba014a43d58c30c48ca9ddcae2b00095b7a6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6764 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-29exynos: Fix the name of the chip_operations structures.Gabe Black
The exynos directories had been moved from src/cpu to src/soc, but the name of the chip_operations structure wasn't updated properly. That meant that the SOCs never installed their memory resources and the ram stage would fail to load the payload. Change-Id: Ib60489b6d3434e3ebd13827a804452f762747f1b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172400 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9100d475ebcc4dae23184583a6cc0162577e70d1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6781 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-29arm: libpayload: Make cache invalidation take pointers instead of integersJulius Werner
This minor refactoring patch changes the signature of all limited cache invalidation functions in coreboot and libpayload from unsigned long to void * for the address argument, since that's really what you have in 95% of the cases and I think it's ugly to have casting boilerplate all over the place. Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167338 (cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6623 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28soc/intel/baytrail/Kconfig: Remove empty line at top filePaul Menzel
Change-Id: I932e4566ec6313a7f2dbd58784bde71bca12abd7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6671 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28qemu: log acpi table sizeGerd Hoffmann
Change-Id: Ib2d7a3d9bda94f80886da96c2b766d29fc15a834 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/6772 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28qemu: fix cirrus buildGerd Hoffmann
commit 9518b56 (intel/gma: Clarify code and use dedicated init for Google Peppy) changed "struct edid" and thereby broke the build. Adapt drivers/emulation/qemu/bochs.c to the changes to fix this. Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y. Change-Id: I2d3cecde21d495e9b99ff8d2f741f8a462c75a4d Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/6771 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28qemu: fix bochs buildGerd Hoffmann
commit 9518b56 (intel/gma: Clarify code and use dedicated init for Google Peppy) changed "struct edid" and thereby broke the build. Adapt drivers/emulation/qemu/bochs.c to the changes to fix this. Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y. Change-Id: Ic295c6d31284555e1463af5bca673231b8722d54 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/6769 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28tegra124: Add a custom bootblock implementation.Gabe Black
This implementation is the same as the general one except that it removes all the things that don't work on an ARMv4. Change-Id: I1108a79cc656b26f7d48df20aef3016cf5ae3182 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171019 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1436288d3b025af27a8d28ba94b589940ead504) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-28ARM: Make it possible to use a custom bootblock implementation.Gabe Black
Tegra needs to use a custom bootblock implementation because it starts on a coprocessor which uses ARMv4. It doesn't have the same control registers, caches, etc., and the regular bootblock gets exceptions and dies. Change-Id: Id197db2939bc840ad64244d6e2017fc5c89e0cbd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171018 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a66393fdd6fe68757e394b8a611e610f1938771d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2014-08-28Peppy/Haswell: move more support functions from mainboard to the intel i915 ↵Ronald G. Minnich
driver Move (and rename to make it clearer) the function that computes display parameters from the dpcd and edid. Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171366 Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6768 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-26armv7: Move Exynos from 'cpu' to 'soc'.Hung-Te Lin
The Exynos family and most ARM products are SoC, not just CPU. We used to put ARM code in src/cpu to avoid polluting the code base for what was essentially an experiment at the time. Now that it's past the experimental phase and we're going to see more SoCs (including intel/baytrail) in coreboot. Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c Reviewed-on: https://chromium-review.googlesource.com/170891 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6739 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-26Peppy, Haswell: refactor and create set_translation_table function in ↵Ronald G. Minnich
haswell/gma.c The code to set the graphics translation table has been in the mainboards, but should be in the northbridge support code. Move the function, give it a better name, and enable support for > 4 GiB while we're at it, in the remote possibility that we get some 8 GiB haswell boards. Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/171160 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit d5a429498147c479eb51477927e146de809effce) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6741 Tested-by: build bot (Jenkins)
2014-08-25intel/gma: Clarify code and use dedicated init for Google PeppyRonald G. Minnich
Peppy had some issues with FUI. We decided it was time to create peppy-specific gma.c and i915io.c files. Using yabel and the i915tool, we generated a replay attack, then interpolated against the slippy i915io.c to get something working. Also, in preparation for moving code out of the mainboard gma.c to generic driver code, we got rid of some hardcodes in the mainboard gma.c that have no business being there. The worst were the computation of gmch_[m,n] and it turns out that we had some long-standing bugs related to confusion about 'bpp'. I've killed the word bpp everywhere I could because there are at least 3 things that correspond to bpp. We now have framebuffer, pipe, and panel bpp. The names are long because I want to avoid all the mistakes we've all been making in the last year :-) Sadly, that means a lot of changes not just peppy-related, but they are simple and in a good cause. The test pattern generation is driven by a global variable in mainboard/peppy/gma.c. I've found in the past that it's very useful to have a function like this available, as one can activate it while using a jtag debugger: halt at the right place in ramstage, set the variable to 1, continue. It's not enough code to worry about always including. The last hard-codes for M and N registers are gone, and the function to set from generic intel_dp.c code works. To avoid screen trash on a dev mode boot, which we liked but nobody else did :-), we now take the time to put a pleasing background color that sort of doubles as a power LED. Rough timing is ramstage start is at 2.2, and dev setup is done at 3.3. These new platforms are depressingly slow to boot. Rom init alone is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash prompt. These CPUs are at least 10x faster and take much longer to get going. Future work, once we get this through, is to move more functions to the intel driver, and combine the mainboard i915io.c into the mainboard gma.c. That separation only existed because i915io.c was generated by a tool, and it had lots of ugliness. Most ugliness is gone. Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/170013 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com> (cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d) snow: Fix a typo in devicetree.cb that was breaking the snow build. A typo in a recent change broke the snow build. Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171014 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 154876c126a6690930141df178485658533096d2) Squashed a fix into the initial patch and updated nehalem/gma.c to have a non-static gtt_poll. Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6657 Tested-by: build bot (Jenkins)
2014-08-25sandybridge: Show spew raminit messages only with raminit debugVladimir Serbinenko
Change-Id: Ifbc59c28c8d8bd844801da9cb869c5dfbda09168 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6754 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-25AMD Steppe Eagle: Add northbridge HT link ID to pci_ids.hBruce Griffith
Add a #define for the HT northbridge link ID into the "known PCI device IDs" table. Change-Id: If0a32b2af5df6c20e0fb5af200c06d80fab3637a Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6680 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-25UART 8250: Unconditionally provide register constants and use UART8250 prefix.Gabe Black
The register indexes and bitfield masks were guarded by the UART8250 config options, but it might be (is) necessary to use them in a driver that is UART8250 like without actually using the 8250 driver itself. To avoid any name collision with other drivers, also change the constant prefix from UART_ to UART8250_. Change-Id: Ie606d9e0329132961c3004688176204a829569dc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171336 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a93900be8d8a8260db49e30737608f9161fbf249) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6715 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-25delay: Have mdelay() / delay() available in romstage, tooStefan Reinauer
Some drivers (like the I2C TPM driver) call mdelay instead of udelay. While it's a shame that these chips are so slow, the overhead of having those functions available in romstage is minimal. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I1fa888fc5ca4489def16ac92e2f8260ccc26d792 Reviewed-on: https://chromium-review.googlesource.com/167542 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7083b6b843d803bd4ddbd8a5aaf9c5c05bad2044) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6531 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-25lenovo/t520: update KconfigNicolas Reinecke
override default ivy VGA_BIOS_ID add model & part number Remove ARCH_X86 as is in, fd33781 Move ARCH_* from board/Kconfig to cpu or soc Kconfig. Change-Id: I61dc6434de7af2d8672f784df87a8b9d3f0fb068 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6759 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-25lenovo/t520: fix PCIe interrupt and function disable configNicolas Reinecke
Change-Id: I33e71c0a246583885368dc3d3af761c190b2fb5c Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6758 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-25lenovo/t5x0: replace invalid config DRAM_GATE_GPIONicolas Reinecke
Change-Id: I3b13bddfc127353e0c13d8d2ae7918d5c3deb72c Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6760 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-25lenovo/x230: Add subsystem ids.Vladimir Serbinenko
Change-Id: I917a89da50d8efe998c368ba46206f2a1c580fd0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6756 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-25lenovo/t530: Be safe by disabling blink gpio hw with a writeoutEdward O'Callaghan
This disables the blink hardware as it seems to be in the dump. This is safer as it does not rely on 0 as the reset value when '0x00040000' is the default according to the util/inteltool. As seen: gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6436 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-25sandybridge: Native gfx init.Vladimir Serbinenko
Change-Id: I07590086ffe3b1d068fa6ae6b156039cc2e55893 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6755 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-24lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h headerEdward O'Callaghan
Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6435 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-24lenovo/t530/romstage.c: Trivial - move include to topEdward O'Callaghan
Change-Id: I6b80ad0da39e93072e28b48c40e1c71602133e7b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6750 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-24lenovo/t520: replace dumped GPIO values with gpio.hNicolas Reinecke
GPIO pin wireing information from schematic Change-Id: I2d8dca151b6fbc15e0184ea07596039570843cda Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6740 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: fix devicetreeNicolas Reinecke
SATA Port documentation PCIe unused ports and documentation T520 have no keyboard backlight Change-Id: I517ff8519ea22a9a7a9b6e3136efd15d4a0f8fc4 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6743 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: fix usb config & documentationNicolas Reinecke
Change-Id: I71398ab2d7ef5b9256795861dd2bebbb0cf32d5f Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6742 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-23ec/lenovo/h8/acpi/systemstatus.asl: Fix typo in o*n* in commentPaul Menzel
Change-Id: I655536f64faaa7e1600d4fec62ba80730e2cc45a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6674 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: Remove empty smi.hNicolas Reinecke
Change-Id: I60fa19b72f91f16db5f354aeec631f661e3494d3 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6736 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23lenovo/t520: Fix ExpressCard hotplugNicolas Reinecke
Thinkpad T520 ExpressCard Slot PCIe lanes are connected to port 4. Tested with Serial Port Card. Information read from schematic / lspci Change-Id: I459943d427578d135f9aed1aa66da269ddfeee87 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6735 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23superio/smsc/sch4037: Cleanup and fix .c inclusionEdward O'Callaghan
Clean up both ram and rom stage support and fix board to match. Change-Id: I55e3e7338c0551f0fb663eb9707f16ecdc1aca35 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6509 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-23superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c includeEdward O'Callaghan
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6463 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-22ARM: Overhaul the ARM Makefile.Gabe Black
The ARM Makefile was copied from x86 and then modified, and as a result it was carrying a lot of baggage. On top of that, the extra complication made it inflexible, and we need a lot of flexiblity in order to support the fact that the Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main CPUs. Change-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171017 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 512d942788336c8d52470135b43ee4e6a1c95f6c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-22Remove dead video.aslVladimir Serbinenko
Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6730 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22lenovo/{x230,t530}: Remove empty smi.hVladimir Serbinenko
Change-Id: I26fa6508f50faff7f1c1724884b5ffa30463b896 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6728 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22lenovo/x230: Remove empty mainboard.aslVladimir Serbinenko
Change-Id: Ic877d6285ce3983268b16ddb5b4e15743f5adf86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6727 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22lenovo/x200: Remove empty mainboard.aslVladimir Serbinenko
Change-Id: I560d693d0d72ca8dcd099eff6b0c40716fb0c0b0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6726 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22lenovo/x200: Move video ASL code to northbridge.Vladimir Serbinenko
Change-Id: I58760500252e78da947685c18201b6d446368333 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6729 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22lenovo/x201: Remove empty mainboard.aslVladimir Serbinenko
Change-Id: I37d48279b1b022c4573bd09d3db6bf536d5dab9a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6724 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-22apple/macbook21: Remove useless seabios configVladimir Serbinenko
Change-Id: If771a84f25710e1fb2228816e3ca0139e2f95aa7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6732 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-22lenovo/t530/mainboard.c: Add EC info to SMBIOSEdward O'Callaghan
As is in: 91175bb lenovo/x201 & x230: Add EC info to SMBIOS This is needed for the Linux driver for the Lenovo's to properly attach. Change-Id: Ib910b25f392d9d3d6362b6909ce9fd4eeae9a096 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6399 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-21Merge LCD on nehalemVladimir Serbinenko
Change-Id: I09852ea56495da17e7607064d74d98f2296f34b1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6721 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21Merge LCD on sandy/ivyVladimir Serbinenko
Change-Id: Ibf66d46f47fe465cc805f85de818a77327cd7258 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6722 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945: Support text mode gfx initVladimir Serbinenko
Change-Id: I952fdb113e2696785695b416d9292b7107099994 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6723 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945/gma: don't map the page tableVladimir Serbinenko
Change-Id: I20fb5323cde1f83a3d3adc98251b2f31de25ed24 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6718 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-21i945: Remove GTT avoidance offset.Vladimir Serbinenko
Not needed anymore with GTT at the end of range. Change-Id: I57b02c7d605d3c43ac92bd744bb6472e3c3471e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6717 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-21arm: Get rid of the INTERMEDIATE variable used on exynos.Gabe Black
The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for Exynos SOCs, but we can do that directly without having a special hook. Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170921 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6714 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-20intel/i945/gma: Place GTT below top of memoryPaul Menzel
Since commit 17fec8a0 [1] drm/i915: Use Graphics Base of Stolen Memory on all gen3+ present in the Linux kernel since version 3.12, 3D does not work anymore [2]. Comparing the graphics registers, in this case that means output of `intel_reg_dumper`, the vendor Video BIOS is setting the register PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to `0x3ffc0001` on a system with 1 GB of RAM, while native graphics init sets it to `0x3f800001`. Currently native graphis init sets the GTT right above the base address of stolen memory. The Video BIOS sets it below the top of memory. The Linux Intel driver expects it to be below top of memory, so do it this way, by setting the address to TOM minus the size of the GTT, which is hardcoded to 256 KiB. As `PGETBL_CTL` is zero by default, reading its value in the beginning is not necessary and is only confusing. Make it clear that the code calculates the value. There is still a PTE error reported during boot, but 3D works with Linux 3.12+ and no user visible problems are shown. [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038 [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1_graphics_core_0.pdf Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller Programmer’s Reference Manual Volume 1: Graphics Core Revision 1.0a Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/5927 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-19tegra124: Implement the tegra i2c driver.Gabe Black
This uses the packet mode of the controller since that allows transfering more data at a time. Change-Id: I8329e5f915123cb55464fc28f7df9f9037b0446d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172402 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4444cd626a55c8c2486cda6ac9cfece4e53dd0d3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6703 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.Gabe Black
The pins on tegra are controlled by three different units, the pinmux, the pin group controls, and the GPIO banks. Each of these units controls some aspect of the pins, and they layer together and interact in interesting ways. By default, the GPIOs are configured to pass through the special purpose IO that the pinmux is configured to and so can be ignored unless a GPIO is needed. The pinmux controls which special purpose signal passes through, along with pull ups, downs, and whether the output is tristated. The pingroup controls change the parameters of a group of pins which all have to do with a related function unit. The enum which holds constants related to the pinmux is relatively involved and may not be entirely complete or correct due to slightly inconsistent, incomplete, or missing documentation related to the pinmux. Considerable effort has been made to make it as accurate as possible. It includes a constant which is the index into the pinmux control registers for that pin, what each of the functions supported by that pin are, and which GPIO it corresponds to. The GPIO constant is named after the GPIO and is the pinmux register index for the pin for that GPIO. That way, when you need to turn on a GPIO, you can use that constant along with the pinmux manipulating functions to enable its tristate and pull up/down mode in addition to setting up the GPIO controls. Also, while in general I prefer not to use macros or the preprocessor when writing C code, in this case the set of constants in the enums was too large and cumbersome to manage without them. Since they're being used to construct a table in a straightforward way, hopefully their negative aspects will be minimized. In addition to the low level functions in each driver, the GPIO code also includes some high level functions to set up input or output GPIOs since that will probably be a very common thing to want to do. Old-Change-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171806 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a) tegra124: Add base address for the pinmux and pingroup registers. There weren't any constants for the pinmux or pingroup registers in the address map header. Old-Change-Id: I52b9042c7506cab0bedd7a734f346cc9fe4ac3fe Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172081 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 79b61016bfd702b0ea5221658305d8bd359f4f62) Squashed two related commits. Change-Id: Ifeb6085128bd53f0ef5f82c930eda66a2b59499b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6702 Tested-by: build bot (Jenkins)
2014-08-19tegra124: Pick addresses to load the rom and ram stages.Gabe Black
If these aren't set, the rom and ram stages will attempt to load at address zero which doesn't work. Change-Id: I0b9b37d6363e6b208248d8a1af6ebee4db602486 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/173540 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 6ac5cea39d423bfcf5bbd53c2cc6228ab89f08b2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6704 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19asrock/imb-a180/board_info.txt: add flash fieldsStefan Tauner
Change-Id: Ie686d20811f33c620156c149315807343dde7784 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/6700 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-19macbook21: Support wake on LIDVladimir Serbinenko
Change-Id: Ifa1045abc761bef05977a8020cf6f18db042ad58 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6699 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x20[01]: Don't undock on disconnecting of power from dock stationVladimir Serbinenko
Change-Id: Id55bf259d5af187ba718de7e367395adcfc567b4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6707 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x201: Fix dock recognitionVladimir Serbinenko
Change-Id: I8b210786f660e2b2bae0d9ddd594386fd107cbe4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6706 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-19lenovo/x201: Unpower USB on undockingVladimir Serbinenko
Change-Id: I9b496e8ff92ee575d0b780eab0cb45ea05506d30 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6708 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-19lenovo/x200: Dock supportVladimir Serbinenko
Change-Id: I4e25630ae82e8030a9d6bfccb60844c301b1d635 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6705 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18trustzone: Pull trustzone init out of cpu.c and do it in romstage.Gabe Black
Trustzone needs to be initialized/disabled both on boot and on wake, so it needs to be done before ramstage which doesn't run on wake. cpu.c isn't compiled into romstage and fixing that causes other problems, so the trustzone functions were split out. Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/169817 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18tegra: Change how tegra124 and tegra include files from each other.Gabe Black
A problem with including the tegra124 directory directly in the include path is that it makes all headers in that directory first level headers available everywhere including places that have nothing to do with the SOC, even headers which were only intended for local use by tegra124 code. This change modifies things a bit to be more like the way the arch headers are chosen. In the tegra124 directory, there's an include directory which has an soc subdirectory in it. That include directory is added to the include path, making it possible to have headers private to the tegra124. When files specific to whatever tegra is being built for are needed, you can include <soc/foo.h> and get the version specific to that particular soc. Also, the soc.h header file was overhauled to use enums instead of defines, to consistently name things as far as their prefix (the less cryptic TEGRA instead of NV_PA) and suffixes like "BASE", and to get rid of values which were specific to U-Boot which we don't need. Since the only thing in the file were address constants, I also renamed the file addressmap.h. It would be included as: <soc/addressmap.h> which I think is easy to remember, does what you'd think it does from the name, and won't conflict with other header files just minding their own business in some other directory. Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172080 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6659 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5420: Don't map low addresses that lead nowhereJulius Werner
I just spent half a day (including the time to implement a stack dumper) to figure out that I am reading from a NULL pointer. A problem this simple should be more easy to catch. Let's mark the address range below SRAM as uncached so that the MMU can yell at you right away for being the bad programmer you are when you access a NULL pointer. Change-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170112 Reviewed-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 7316732ea0ccdc0d607bde81dbb38ca9abd29fa9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6650 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18arm/exynos: Allow releasing UART retention for resume.Hung-Te Lin
The UART / serial console is put in retention state by kernel during suspend / resume path, which caused Coreboot not able to print any messages during resume. Sending values to the padret_uart_opt inside PMU may release UART, but that may also cause unexpected output when kernel is back. However, it's still very helpful when we are debugging suspend/resume inside Coreboot. To get UART message on resume, call wakeup_enable_uart() in boot block or romstage (before console_init). Change-Id: Ib5759cb402c6e018d9dba14fad8b61f6a1b1a265 Reviewed-on: https://chromium-review.googlesource.com/170440 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 547fbbfe2eeb6da4e161f36be2caf8099f9eac9b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6649 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18exynos5: Implement support for USB 3.0 DRD PHYs/controllersJulius Werner
This patch adds support for the DesignWare3 USB 3.0 DRD controller and PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the Google Snow and Pit boards to turn these controllers on where applicable. Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169452 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6642 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18console: conditionally include console in bootblockStefan Reinauer
Right now some console specific objects are included in the bootblock even if CONFIG_BOOTBLOCK_CONSOLE is disabled while others are not. Make all of them conditional and also fix a preprocessor misuse in bootblock_simple.c and a stray (useless) die() in the Exynos wakeup code that made inclusion of those files necessary. Change-Id: Ia7f9d17654466f199b0e13afbdc9e14c9706530f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168772 Reviewed-by: David Hendrix <dhendrix@chromium.org> (cherry picked from commit 855da1f07b52898c7edcaffe5baabe9d485bbd83) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6637 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-18macbook11: New mainboard (macbook21 clone)Vladimir Serbinenko
Tested by marcus. Change-Id: Ifce2018ef49619b36fb07e5345d70c358a0397e4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6698 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18azalia: Move shared variable to separate fileVladimir Serbinenko
Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-18mainboard/intel/mohonpeak: code cleanupMartin Roth
Code cleanup requested in commit 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" - Change com2 to COM2 in Kconfig text - clean up includes of headers - fix whitespace Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6607 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth
This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18mainboard/XXX/YYY/dsdt.asl: Whitespace fixMartin Roth
Use tab between "COREBOOT", and comment. This fix was requested in 90957f88 - "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000" Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6601 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18cpu/intel/fsp_model_406dx: code cleanupMartin Roth
Code cleanup requested in commit 09670265 - "cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)" - add guard statements to chip.h - remove excessive includes - whitespace cleanup - add an IS_ENABLED Change-Id: Iaa85bd66953df015f083b23f6fd32949bcfd17bc Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6599 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18apple/macbook21: Fix audio.Vladimir Serbinenko
Change-Id: I0bb939ac377f84431d871b702fdb42651e9a2e96 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5324 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-17Revert "macbook21: Add CST entries"Vladimir Serbinenko
Some of C-states still cause hang. Revert C-states patch. This reverts commit fe661612d8e94d41dc0129533bb02f7c4faaf11a. Change-Id: I7534dac5d27b853d7b93947c38bf3742797fdcc2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6694 Tested-by: build bot (Jenkins) Reviewed-by: Francis Rowe <info@gluglug.org.uk> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-08-17gm45: Declare BIOS memory as RAM.Vladimir Serbinenko
So it's in line with other boards and those addresses are cached for faster access. Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6689 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-17macbook21: Add CST entriesVladimir Serbinenko
Change-Id: I9e8628d879a193e2f6ba561ee17f24ae94435e1a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6693 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-17apple/macbook21: EC handling ACPI implementation.Vladimir Serbinenko
Now battery indicator and lid work. Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5323 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-17A new port apple/macbook21.Mono
Current problems: - Complete lack of EC support (no battery indicator, no temperature, ...) - No audio support Change-Id: I25d09629dd82e01fadca2b6c25f72aaf08eafae1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Axel Holewa <mono@posteo.de> Reviewed-on: http://review.coreboot.org/5321 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 11:24:56 +0000