summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2020-12-20mb/clevo/kbl-u: drop duplicated configuration of UART padsMichael Niewöhner
UART pads already get configured in bootblock by the UART driver in soc code. Thus, drop the duplicated code from the mainboard. Change-Id: I95565a74e19d693a7d5ead81e72592cc4ca2038c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-20mb/clevo/cml-u: drop duplicated configuration of UART padsMichael Niewöhner
UART pads already get configured in bootblock by the UART driver in soc code. Thus, drop the duplicated code from the mainboard. Tested successfully on Clevo L141CU. Change-Id: I05a459b0af79c75c31b1bb26ea1a1a40857ef9bf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-19soc/amd/picasso: move sb_clk_output_48Mhz from acp to fchEric Lai
Move sb_clk_output_48Mhz out of acp. It should be called unconditionally. We may have another device need this clock e.g. superio chip. BUG=b:174121847 BRANCH=zork TEST= build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-18soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flagEric Lai
If we have use external clock source for I2S, we don't need to enable internal one. Add acp_i2s_use_external_48mhz_osc flag for the project which uses external clock source. BUG=b:174121847 BRANCH=zork TEST= build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-18soc/amd/cezanne: add GPIO supportFelix Held
This still uses the common GPIO code that supports setting up SMI/SCI support for the GPIOs in all stages, which will get removed in future patches, so for now the SoC's gpio.c needs to be included in all stages. Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-18soc/amd/cezanne: Add SMI supportZheng Bao
Change-Id: I83b9a91cbab297d032292997a4d5768b89fe97dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48645 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-18vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1512_11Subrata Banik
List of changes: FSP-S Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45 Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-17azalia: Use `azalia_enter_reset` functionAngel Pons
Also tidy up some adjacent comments. Change-Id: I2e881900a52e42ab3f43ffe96cfbdcc63ff02e23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17soc/intel/common/hda_verb.c: Clarify mask usageAngel Pons
The `azalia_set_bits` will mask out all bits, so just use zero for clarity. The resulting behavior is the same in both cases. Change-Id: I27777f1e836fa973859629d48964060bec02c87a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17soc/intel/skylake: Drop duplicate PmConfigPciClockRun configurationBenjamin Doron
coreboot already unconditionally enables CLKRUN_EN in SoC common code. Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN] of LPC is still enabled. Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17soc/amd/cezanne: add GPIO definitionsFelix Held
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-17azalia: Use `azalia_exit_reset` functionAngel Pons
Change-Id: I346040eb6531dac6c066a96cd73033aa17f026d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17device/azalia_device.c: Add codec reset helpersAngel Pons
Many uses of `azalia_set_bits` are used to toggle the reset bit. To avoid having to repeat the register operations and the corresponding comment, create two helpers with self-explanatory names. They will be put to use in subsequent commits, with one change for each function. Change-Id: If0594fdaf99319f08a2e272cd37958f0f216e654 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17device/azalia_device.c: Clarify commentAngel Pons
The `4` here doesn't have to do with the size of u32. Instead, it is because the verb header contains the number of jacks, which is the number of four-verb groups. Change-Id: I3956ce5ec2a7abc29982504cf75b262a1c098af5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Replace `hda_find_verb` usesAngel Pons
This function is equivalent to `azalia_find_verb` in its current form, so replace them. Also, adapt and move the function description comment. Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Make `azalia_find_verb` parametricAngel Pons
Allow to specify which table should the verb list be read from. Change-Id: Id1bc40c4364cda848f416bad9eeab1b8ca3e9512 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Drop unused parameter from `azalia_find_verb`Angel Pons
The `dev` parameter isn't used anywhere. Change-Id: I05643f8201137ffe89ded1e3f989c5a0f04e0af1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Make `find_verb` function non-staticAngel Pons
To allow dropping copies of this function, make it non-static. Also, rename it to `azalia_find_verb` as the function is now globally visible. Finally, replace the copies in chipset code with `azalia_find_verb`. Change-Id: Ie66323b2c62139e86d3d7e003f6653a3def7b5f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17device/azalia_device.c: Remove debug printsAngel Pons
The other five copies of this function in the tree do not have these debug prints. Remove them from here for consistency. Note that this information is already printed elsewhere, so nothing is being lost. Change-Id: I999032af1628bf8d66a057dc72368f02ef6eb8d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Make `set_bits` function non-staticAngel Pons
There's many copies of this function in the tree. Make the copy in azalia_device.c non-static and rename it to `azalia_set_bits`, then replace all other copies with it. Since azalia_device.c is only built when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary. This has the side-effect of building hda_verb.c from the mainboard directory. If this patch happens to break audio on a mainboard, it's because its hda_verb.c was always wrong but wasn't being compiled. Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17mb/intel/coffeelake_rvp: Stop using headers for HDA verbsAngel Pons
One of the variants lacks an hda_verb.h, and hda_verb.c can't be built. Follow-up changes will make mainboard hda_verb.c files always get built through AZALIA_PLUGIN_SUPPORT, and breaks building this contraption. Turn the headers into standalone compilation units to prevent this issue. Since they contain definitions, including them from multiple compilation units wasn't a good idea anyway. Change-Id: I00d968563539a4e1b8d1e12145293439d8358555 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48360 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17mb/google/zork: update USB 2.0 controller Lane Parameter for morphiusKevin Chiu
from AMD USB phy specialist recommended that TXVREFTUNE0 shouldn't over 0xD (the maximum) in order to have enough room to accomdate a safe disconnect threshhold in COMPDISTUNE0. TXVREFTUNE0: 0xf -> 0xd BUG=b:172687208 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ia104454d95e5e8d6a212c97fb09d61125945eeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/48653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-17arch/arm: Replace .id section with build_info in CBFSKyösti Mälkki
For arch/arm[64], the offsets to board identification strings and CONFIG_ROM_SIZE inside .id were never really used; it was only a convenience to have the strings appear near the start of image. Add the same strings in an uncompressed file in CBFS. Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47602 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17arch/ppc64: Remove .id section in bootblockKyösti Mälkki
The strings in .id are expected to match the build for the purpose of identifying the binary image. There is no identified use for the offsets. The files id.ld and prologue.inc were unused. Change-Id: Ida332671e0ace3f6afd11020474ffda04614bad5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-17arch/x86: Remove ID_SECTION_OFFSETKyösti Mälkki
The location is hardcoded inside flashrom and FILO. Only two offsets are supported, 0x10 and 0x80. Change-Id: I8348f2ac0cab969ab78ecb50a55de486eee0cf9b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47598 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 portsV Sowmya
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543 Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-17mb/google/guybrush: Add new mainboardMathew King
Guybrush is a new Google mainboard with an AMD SOC. BUG=b:175143925 TEST=builds Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17soc/intel/cannonlake: Change mainboard_silicon_init_params argumentPatrick Rudolph
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-17drivers: Replace set_vbe_mode_info_validPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple indepent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or fb_new_framebuffer_info_from_edid. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-17mb/google/zork: Add GPIO to Shuboz supportKane Chen
1. AGPIO5 to NC 2. EGPIO141 to NC 3. EGPIO144 to NC BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I51f291476e01982e1a3f92cd1b338a528434112d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48002 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/amd/picasso: Fix the typo in GPIO defineZheng Bao
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16soc/intel/xeon_sp: Move DMICTL lockArthur Heymans
On SKX FSP-M does not return if this is set too early. Tested on OCP/Tiogapass, boots. Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/ocp/tiogapass/devicetree.cb: Add P2SB deviceArthur Heymans
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is accessed to read out or reconfigure the HPET and PCH IOAPIC BDF. Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/amd/common/gpio_banks: Drop underscore in __gpioKyösti Mälkki
The local function names were chosen such that they don't collide with <gpio.h> so the prefix is unnecessary. Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16soc/mediatek/mt8192: Do the dramc pinmux selectionHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16arch/x86: Link gdt_init.S into bootblockKyösti Mälkki
Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset. Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16soc/intel/broadwell: Drop unnecessary `sa_dev`Angel Pons
Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16arch/x86: Clean up bootblock assemblyKyösti Mälkki
We have identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol. Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol. With the romcc bootblock solution, entry32.inc may have been linked into romstage before, but the !ENV_BOOTBLOCK case seems obsolete now. Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16mb/google/dedede/var/magolor: Add Wifi SAR for magolor and magliaRen Kuo
Add wifi sar for magolor and maglia: Using tablet mode of fw config to decide to load custom wifi sar or not. same wifi sar value for magolor and maglia (shared firmware) BUG=b:173001370, b:173001251 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chrome-internal:3453724 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I44ab68c9ee5deced90d3858161571ab4b39b4c8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48448 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/dedede/var/sasuke: Add memory part and generate DRAM IDSeunghwan Kim
This change adds memory part used by variant sasuke to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:172104731 Change-Id: Ie8d66261cb5b4493afb1c677839f807bca994af5 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48451 Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/mediatek/mt8192: Correct return value of VM18 voltageHsin-Hsiung Wang
The voltage of vm18 should be microvolt instead of millivolt. BUG=b:155253454 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Keep CONN MCU in reset stateWeiyi Lu
Keep the CONN MCU in reset state to prevent CONN from asserting the clk26m request to SPM. TEST=clk26m request from conn has been released. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16mb/google/poppy: Fix race condition in acpi camera_pmicRicardo Ribalda
Newer kernels can re-schedule new acpi command calls during a Sleep(). This causes that the following trace fails to detect the cameras: [ 15.764725] drivers/acpi/power.c:358 Power resource [OVFI] turned on start [ 15.772180] drivers/acpi/power.c:358 Power resource [OVTH] turned on start [ 15.834970] drivers/acpi/power.c:362 Power resource [OVFI] turned on start [ 15.852456] drivers/acpi/power.c:415 Power resource [OVFI] turned off start [ 15.955987] drivers/acpi/power.c:420 Power resource [OVFI] turned off end ERROR!! [ 16.030896] drivers/acpi/power.c:362 Power resource [OVTH] turned on end Which can be triggered more frequently if the Sleep() commands in OVTH _ON Method are increased. To avoid the race condition, we create a new Power Resource that handles the common resources of both cameras and make both cameras depend on that resource. This also simplifies the acpi table by removing a Mutex. BRANCH=poppy BUG=b:171955583 TEST=while true; do if ssh $DUT "dmesg | grep \"failed to find sensor\" "; then break; fi; ssh $DUT reboot; sleep 30 ; done Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Change-Id: I25df0225699759c1828b8791c5bdee66529858a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48631 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/zork/: Remove WRDD from VilbozEric Lai
After checked, this project doesn't need this feature. BUG=b:173066178 BRANCH=zork TEST=check no WRDD method in acpi. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9a662953f3047d771f2df919ac80d0440842738e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48621 Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/purism/librem_cnl: Use FMAP-based SPD cacheMatt DeVillier
Use a FMAP region to cache SPD data, providing improvements in boot time and detection of change in DIMM population (which FSP will sometimes fail to detect / fail to invalidate the MRC cache). Adapted from implementation used in google/hatch. Test: build/boot Librem Mini v2, verify SPD cache used, changes in DIMM population properly detected. Change-Id: I15cb9aa8b00d39d098a0f901aee026bac1161a80 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48549 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/mediatek/mt8192: Do dramc init settingsHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/amd/common: Use only byte access for IOMUXKyösti Mälkki
Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/octopus/variants/casta: Add support zinitix touchpadSeunghwan Kim
This change adds support zinitix touchpad for casta/bluebird. BRANCH=firmware-octopus-11297.B BUG=b:175618033 TEST=built and verified touchpad worked on casta Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48634 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/mediatek/mt8192: Enable DCMmtk15698
Enable DCM settings. Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 Signed-off-by: mtk15698 <michael.kao@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: ufs: Disable reference clockWenbin Mei
UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Initialize audio pll tuner frequencyWeiyi Lu
Add AUDPLL TUNER init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15soc/amd/picasso/smi: add missing bits to GEVENT_MASKFelix Held
GEVENT_MASK should cover all GEVENT pins, but was missing SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8. Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-15soc/amd/common,picasso: Place some ENV_X86 guardsKyösti Mälkki
Base address symbols for ACPIMMIO banks that would not get assigned at runtime must not resolve at linker-stage either. The build of PSP-verstage should pass without the preprocessor macros that have x86-centric view of memory space. Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-15soc/amd/common: Move lpc_util to verstage_x86Kyösti Mälkki
The file seems to be all about PCI configuration access. Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15soc/amd/common: Redo ACPIMMIO_BASE and _BANKKyösti Mälkki
Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42894 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15soc/amd/common: Refactor SMBus base argumentsKyösti Mälkki
Replace SMBus base addresses with proper symbols. Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42074 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15soc/intel/xeon_sp: Fix final MTRR usageArthur Heymans
The region top_of_ram -> cbmem_top is used by FSP and cbmem, but is also just regular DRAM. Marking it as such improves the final MTRR solution a lot and fixes MTRR starvation depending on the setup. Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47868 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15mb/purism/librem_mini: Adjust PL1/2 levelsMatt DeVillier
While the Librem Mini (v1/v2) are more than capable of higher PL1/2, they currently ship with a 40W power supply, so set PL1/2 accordingly to avoid power spikes above the PSU rating (which can result in unexpected showdowns/reboots) Change-Id: Ia7f89e885f1af29cbbb67d6fb844257ba2b87417 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-15mb/google/asurada: Initialize displayHuijuan Xie
Enable ANX7625 panel and configure display in mainboard_init() to support display in firmware screen. BUG=b:155713214 BRANCH=none TEST=Recovery screen is shown in recovery mode. Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com> Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15mb/google/kukui: help payload to identify correct speaker amp typeHung-Te Lin
Kukui based devices may use different speaker amplifiers, for example MAX98357A, RT1015, or RT1015Q/automode. To help payloads identifying which component was installed on board, we want to pass the speaker GPIO in different name. This can be set in Kconfig as CONFIG_SPEAKER_GPIO_NAME. BUG=b:174534548 TEST=emerge-kukui coreboot depthcharge chromeos-bootimage BRANCH=kukui Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15soc/mediatek/mt8192: Define DRAM registers and APIsHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ifc64fb6c60d57184c4a2f9febe765b5cb69b39ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/44699 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGLShreesh Chhabbi
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config option. Select CAR_HAS_SF_MASKS for Tigerlake. During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x are not being reset to default as per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5. Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient. Bug=b:171601324 BRANCH=volteer Test=Build and boot to ChromeOS on Delbin. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-14soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config optionShreesh Chhabbi
SF Mask MSRs' Programming which was done under this config selection will be moved under a new config option called CAR_HAS_SF_MASKS. This segregates the eNEM programming sequence based on sub features supported in each processor. Bug=b:171601324 BRANCH=volteer Test=Build volteer build and boot on Delbin EVT. Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14sb/intel/common/smbus_ops.c: Clean up read resourcesAngel Pons
Using `pci_dev_read_resources` works just as well on bd82x6x (the allocator does the same) and allows dropping the i82801gx check. Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48538 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/intel/tglrvp: Enable CNVi Bluetooth for UP4Bora Guvendik
Turn on CNVi Bluetooth for UP4 in devicetree. BUG=none TEST=Boot to OS, check BT enumeration. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I6a3ec7014c41713697e0fcc90e28bc7bbe6aa1e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-12-14mb/prodrive/hermes: Update PCIe slots in devicetreePatrick Rudolph
* Drop PcieRpSlotImplemented on internal slots * Add PCIe port 15 that connected to CNVi/M.2 E Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstageSridhar Siricilla
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync() must be called after DRAM initialization. BUG=b:174694480 Test=Verified on Tigerlake platform Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48281 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstageSridhar Siricilla
This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync() must be called after DRAM initialization. BUG=b:174694480 Test=Verified on Drawlet Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/common: Move CSE Lite driver functionality into romstageSridhar Siricilla
The patch sets up the CSE Lite driver in the romstage instead of ramstage. With this change, CSE Lite driver sets CSE's boot partition and triggers CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM initialization as HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) is expected to be executed after DRAM initialization. With this change, it improves the cold boot time by ~154ms. Test=Verified on JSL and TGL platforms BUG=b:174694480 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/inte/common: Replace #if macro with if C-language constuctSridhar Siricilla
This patch modifies CSE Lite driver to use 'if' C-lanugage construct instead of #if macro and adds 'if SOC_INTEL_CSE_RW_UPDATE' to the prompts of CSE Update related KConfigs to prevent appearing them in the menu. TEST=Built the code for drawcia Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BPSridhar Siricilla
The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob and CSE RW boot are different. TEST=Verified on drawcia. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48423 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/braswell: Use Kconfig value for TSEG sizeAngel Pons
SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also, use SMM_TSEG_SIZE in place of a magic number. Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/braswell: Clean up devicetree settingsAngel Pons
Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero ProbelessTrace dt settingAngel Pons
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero PowerLimit4 dt settingAngel Pons
Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway. Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop never-set DdrFreqLimit dt settingAngel Pons
Only Google Eve uses a non-zero value, but it overwrites in C code. Drop the devicetree setting, since no mainboard uses it. Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/xeon_sp/skx: Hook up microcode blobArthur Heymans
TESTED on ocp/tiagopass: Microcode updates are properly applied (via FIT). Tested with out of tree patches to report the revision. Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-14soc/intel/skylake: Drop unreferenced PttSwitch dt settingAngel Pons
The value for this setting is not used anywhere. Drop it. Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48571 Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/purism/librem_cnl: move setting of FSP-M UPDs into variant.cMatt DeVillier
The upcoming Librem 14 variant won't use the same SATA HSIO adjustments as the Librem Mini, so move these settings into a variant-specific file. Rename existing gpio.h to variant.h, move to board root directory, and use for all variant-specific declarations; adjust references as needed. Add newly-created variant.c to Makefile. Test: build/boot Librem Mini, verify SATA functionality unchanged. Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48519 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/xeon_sp: Configure DPR on all stacksArthur Heymans
Configure DPR to span the region between cbmem_top and TSEG base. This region was already unavailable to the OS. Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-14arch/x86: Combine bootblock linker scriptsKyösti Mälkki
Packing bootblock sections is somewhat easier to understand when these all appear in one .ld file. Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14nb/intel/ironlake: Add comment about MCH scan chainsAngel Pons
Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14nb/intel/ironlake: Remove unused constantAngel Pons
Change-Id: I0a32295e72270cde2e9bd2f8f00358b47ffd3e33 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48562 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14src/lib: Add Kconfig option for SPD cache in FMAPMatt DeVillier
Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14drivers: Replace multiple fill_lb_framebuffer with single instancePatrick Rudolph
Currently it's not possible to add multiple graphics drivers into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics drivers can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace all duplications of fill_fb_framebuffer and provide a single one in edid_fill_fb.c. Should not change the current behaviour as still only one graphic driver can be active at time. Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/tigerlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I5f5da8dfcec7dd35981611830b555cab5d6af3e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48572 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/jasperlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/icelake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: I6ce43071c95eeb41c35ddfdb734db52d863ea8e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/elkhartlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ia928c4bbddd1c160228a9af8faf5d4be787f73f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/cannonlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ia9c8347cad479c6b4e678630921f768e0fdee6d9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14soc/intel/alderlake: Drop unreferenced devicetree settingsAngel Pons
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-14intel/common/block/lpc: Add new device IDs for Emmitsburg PCHJonathan Zhang
Add LPC/eSPI device ID of Emmitsburg (EMB) for setting LPC resources. Refer to Emmitsburg PCH EDS (606161). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie5a5d9ba7e4f664ada2dae2294d6e4d0280a2157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-14mb/google/glados/var/caroline: Drop zero setting from dtAngel Pons
Unset devicetree options already default to zero. Note that this setting is not referenced anywhere else, and will be removed in a follow-up. Change-Id: I7bcc1c66caa9167c2327e1dc782f69c5de0fac2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48579 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/intel/ehlcrb: Remove unrelated Kconfig settingsTan, Lean Sheng
Update Kconfig to remove unrelated configs inheritted from JSL_RVP. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48544 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update IRQ routing settingsTan, Lean Sheng
Update IRQ routing settings. Extra reference: - ACPI spec 6.2.13 _PRT Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-14soc/intel/elkhartlake: Update USB & PCIe devices in ASL filesTan, Lean Sheng
Update USB & PCIe devices in ASL files as per EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-14soc/intel/elkhartlake: Update USB_PORT_MID pin settingsTan, Lean Sheng
Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values for USB_PORT_MID. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48541 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update SerialIO devices detailsTan, Lean Sheng
Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS. Also update device function number for GSPI #2 in asl file. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/intel/elkhartlake: Update HECI Control Status Register settingsTan, Lean Sheng
For EHL, SpiProtectionMode is added to HFSTS register #1. The original Manufacturing Mode is detected via FpfSocConfigLock instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode, and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 09:22:10 +0000